1 /* $NetBSD: stp4020reg.h,v 1.5 2025/08/06 11:11:34 andvar Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 33 #ifndef _STP4020_REG_H 34 #define _STP4020_REG_H 35 36 /* 37 * STP4020: SBus/PCMCIA bridge supporting two Type-3 PCMCIA cards. 38 * Programming information source: 39 * - http://www.sun.com/microelectronics/datasheets/stp4020/ 40 * - SunOS 5.5 header file 41 */ 42 43 /* 44 * General chip attributes. 45 */ 46 #define STP4020_NSOCK 2 /* number of PCCARD sockets per STP4020 */ 47 #define STP4020_NWIN 3 /* number of windows per socket */ 48 49 /* 50 * Socket control registers. 51 * 52 * Each PCMCIA socket has two interface control registers and two interface 53 * status registers associated with it. 54 */ 55 56 /* 57 * Socket Interface Control register 0 58 */ 59 #define STP4020_ICR0_rsvd1 0xc000 /* reserved bits */ 60 #define STP4020_ICR0_PROMEN 0x2000 /* FCode PROM enable */ 61 /* Status change interrupts can be routed to one of two SBus interrupt levels:*/ 62 #define STP4020_ICR0_SCILVL 0x1000 /* card status change interrupt level */ 63 #define STP4020_ICR0_SCILVL_SB0 0x0000 /* interrupt on *SB_INT[0] */ 64 #define STP4020_ICR0_SCILVL_SB1 0x1000 /* interrupt on *SB_INT[1] */ 65 /* Interrupt enable bits: */ 66 #define STP4020_ICR0_CDIE 0x0800 /* card detect interrupt enable */ 67 #define STP4020_ICR0_BVD2IE 0x0400 /* battery voltage detect 2 int en. */ 68 #define STP4020_ICR0_BVD1IE 0x0200 /* battery voltage detect 1 int en. */ 69 #define STP4020_ICR0_RDYIE 0x0100 /* ready/busy interrupt enable */ 70 #define STP4020_ICR0_WPIE 0x0080 /* write protect interrupt enable */ 71 #define STP4020_ICR0_CTOIE 0x0040 /* PC card timeout interrupt enable */ 72 #define STP4020_ICR0_rsvd2 0x0020 /* */ 73 #define STP4020_ICR0_IOIE 0x0010 /* I/O (*IRQ) interrupt enable */ 74 /* PC card I/O interrupts can also be routed to one of two SBus intr levels: */ 75 #define STP4020_ICR0_IOILVL 0x0008 /* I/O (*IRQ) interrupt level (SBus) */ 76 #define STP4020_ICR0_IOILVL_SB0 0x0000 /* interrupt on *SB_INT[0] */ 77 #define STP4020_ICR0_IOILVL_SB1 0x0008 /* interrupt on *SB_INT[1] */ 78 79 #define STP4020_ICR0_SPKREN 0x0004 /* *SPKR_OUT enable */ 80 #define STP4020_ICR0_RESET 0x0002 /* PC card reset */ 81 #define STP4020_ICR0_IFTYPE 0x0001 /* PC card interface type */ 82 #define STP4020_ICR0_IFTYPE_MEM 0x0000 /* MEMORY only */ 83 #define STP4020_ICR0_IFTYPE_IO 0x0001 /* MEMORY and I/O */ 84 #define STP4020_ICR0_BITS "\177\010" \ 85 "b\0IFTYPE\0b\1RESET\0b\2SPKREN\0" \ 86 "b\3IOILVL\0b\4IOIE\0b\6CTOIE\0" \ 87 "b\7WPIE\0b\10RDYIE\0b\11BVD1IE\0b\12BVD2IE\0"\ 88 "b\13CDIE\0b\14SCILV\0b\15PROMEN\0\0" 89 90 /* Shorthand for all status change interrupts enables */ 91 #define STP4020_ICR0_ALL_STATUS_IE ( \ 92 STP4020_ICR0_CDIE | \ 93 STP4020_ICR0_BVD2IE | \ 94 STP4020_ICR0_BVD1IE | \ 95 STP4020_ICR0_RDYIE | \ 96 STP4020_ICR0_WPIE | \ 97 STP4020_ICR0_CTOIE \ 98 ) 99 100 /* 101 * Socket Interface Control register 1 102 */ 103 #define STP4020_ICR1_LPBKEN 0x8000 /* PC card data loopback enable */ 104 #define STP4020_ICR1_CD1DB 0x4000 /* card detect 1 diagnostic bit */ 105 #define STP4020_ICR1_BVD2DB 0x2000 /* battery voltage detect 2 diag bit */ 106 #define STP4020_ICR1_BVD1DB 0x1000 /* battery voltage detect 1 diag bit */ 107 #define STP4020_ICR1_RDYDB 0x0800 /* ready/busy diagnostic bit */ 108 #define STP4020_ICR1_WPDB 0x0400 /* write protect diagnostic bit */ 109 #define STP4020_ICR1_WAITDB 0x0200 /* *WAIT diagnostic bit */ 110 #define STP4020_ICR1_DIAGEN 0x0100 /* diagnostic enable bit */ 111 #define STP4020_ICR1_rsvd1 0x0080 /* reserved */ 112 #define STP4020_ICR1_APWREN 0x0040 /* PC card auto power switch enable */ 113 114 /* 115 * The Vpp controls are two-bit fields which specify which voltage 116 * should be switched onto Vpp for this socket. 117 * 118 * Both of the "no connect" states are equal. 119 */ 120 #define STP4020_ICR1_VPP2EN 0x0030 /* Vpp2 power enable */ 121 #define STP4020_ICR1_VPP2_OFF 0x0000 /* no connect */ 122 #define STP4020_ICR1_VPP2_VCC 0x0010 /* Vcc switched onto Vpp2 */ 123 #define STP4020_ICR1_VPP2_VPP 0x0020 /* Vpp switched onto Vpp2 */ 124 #define STP4020_ICR1_VPP2_ZIP 0x0030 /* no connect */ 125 126 #define STP4020_ICR1_VPP1EN 0x000c /* Vpp1 power enable */ 127 #define STP4020_ICR1_VPP1_OFF 0x0000 /* no connect */ 128 #define STP4020_ICR1_VPP1_VCC 0x0004 /* Vcc switched onto Vpp1 */ 129 #define STP4020_ICR1_VPP1_VPP 0x0008 /* Vpp switched onto Vpp1 */ 130 #define STP4020_ICR1_VPP1_ZIP 0x000c /* no connect */ 131 132 #define STP4020_ICR1_MSTPWR 0x0002 /* PC card master power enable */ 133 #define STP4020_ICR1_PCIFOE 0x0001 /* PC card interface output enable */ 134 135 #define STP4020_ICR1_BITS "\177\010" \ 136 "b\0PCIFOE\0b\1MSTPWR\0f\2\2VPP1EN\0" \ 137 "f\4\2VPP2EN\0b\6APWREN\0b\10DIAGEN\0" \ 138 "b\11WAITDB\0b\12WPDB\0b\13RDYDB\0" \ 139 "b\14BVD1D\0b\15BVD2D\0\16CD1DB\0b\17LPBKEN\0" 140 141 /* 142 * Socket Interface Status register 0 143 * 144 * Some signals in this register change meaning depending on whether 145 * the socket is configured as MEMORY-ONLY or MEMORY & I/O: 146 * mo: valid only if the socket is in memory-only mode 147 * io: valid only if the socket is in memory and I/O mode. 148 * 149 * Pending interrupts are cleared by writing the corresponding status 150 * bit set in the upper half of this register. 151 */ 152 #define STP4020_ISR0_ZERO 0x8000 /* always reads back as zero (mo) */ 153 #define STP4020_ISR0_IOINT 0x8000 /* PC card I/O intr (*IRQ) posted (io)*/ 154 #define STP4020_ISR0_SCINT 0x4000 /* status change interrupt posted */ 155 #define STP4020_ISR0_CDCHG 0x2000 /* card detect status change */ 156 #define STP4020_ISR0_BVD2CHG 0x1000 /* battery voltage detect 2 status change */ 157 #define STP4020_ISR0_BVD1CHG 0x0800 /* battery voltage detect 1 status change */ 158 #define STP4020_ISR0_RDYCHG 0x0400 /* ready/busy status change */ 159 #define STP4020_ISR0_WPCHG 0x0200 /* write protect status change */ 160 #define STP4020_ISR0_PCTO 0x0100 /* PC card access timeout */ 161 162 #define STP4020_ISR0_LIVE 0x00ff /* live status bit mask */ 163 #define STP4020_ISR0_CD2ST 0x0080 /* card detect 2 live status */ 164 #define STP4020_ISR0_CD1ST 0x0040 /* card detect 1 live status */ 165 #define STP4020_ISR0_BVD2ST 0x0020 /* battery voltage detect 2 live status (mo) */ 166 #define STP4020_ISR0_SPKR 0x0020 /* SPKR signal live status (io)*/ 167 #define STP4020_ISR0_BVD1ST 0x0010 /* battery voltage detect 1 live status (mo) */ 168 #define STP4020_ISR0_STSCHG 0x0010 /* I/O *STSCHG signal live status (io)*/ 169 #define STP4020_ISR0_RDYST 0x0008 /* ready/busy live status (mo) */ 170 #define STP4020_ISR0_IOREQ 0x0008 /* I/O *REQ signal live status (io) */ 171 #define STP4020_ISR0_WPST 0x0004 /* write protect live status (mo) */ 172 #define STP4020_ISR0_IOIS16 0x0004 /* IOIS16 signal live status (io) */ 173 #define STP4020_ISR0_WAITST 0x0002 /* wait signal live status */ 174 #define STP4020_ISR0_PWRON 0x0001 /* PC card power status */ 175 176 #define STP4020_ISR0_IOBITS "\177\010" \ 177 "b\0PWRON\0b\1WAITST\0b\2IOIS16\0b\3IOREQ\0" \ 178 "b\4STSCHG\0b\5SPKR\0b\6CD1ST\0b\7CD2ST\0" \ 179 "b\10PCTO\0b\11WPCHG\0b\12RDYCHG\0" \ 180 "b\13BVD1CHG\0b\14BVD2CHG\0b\15CDCHG\0" \ 181 "b\16SCINT\0b\17IOINT\0\0" 182 #define STP4020_ISR0_MOBITS "\177\010" \ 183 "b\0PWRON\0b\1WAITST\0b\2WPST\0b\3RDYST\0" \ 184 "b\4BVD1ST\0b\5BVD2ST\0b\6CD1ST\0b\7CD2ST\0" \ 185 "b\10PCTO\0b\11WPCHG\0b\12RDYCHG\0" \ 186 "b\13BVD1CHG\0b\14BVD2CHG\0b\15CDCHG\0" \ 187 "b\16SCINT\0\0" 188 189 /* 190 * Socket Interface Status register 1 191 */ 192 #define STP4020_ISR1_rsvd 0xffc0 /* reserved */ 193 #define STP4020_ISR1_PCTYPE_M 0x0030 /* PC card type(s) supported bit mask */ 194 #define STP4020_ISR1_PCTYPE_S 4 /* PC card type(s) supported bit shift */ 195 #define STP4020_ISR1_REV_M 0x000f /* ASIC revision level bit mask */ 196 #define STP4020_ISR1_REV_S 0 /* ASIC revision level bit shift */ 197 #define STP4020_ISR1_BITS "\177\010" \ 198 "f\0\4REV\0f\4\2PCTYPE\0\0" \ 199 200 201 /* 202 * Socket window control/status register definitions. 203 * 204 * According to SunOS 5.5: 205 * "Each PCMCIA socket has three windows associated with it; each of 206 * these windows can be programmed to map in either the AM, CM or IO 207 * space on the PC card. Each window can also be programmed with a 208 * starting or base address relative to the PC card's address zero. 209 * Each window is a fixed 1Mb in size. 210 * 211 * Each window has two window control registers associated with it to 212 * control the window's PCMCIA bus timing parameters, PC card address 213 * space that that window maps, and the base address in the 214 * selected PC card's address space." 215 */ 216 #define STP4020_WINDOW_SIZE (1024*1024) /* 1MB */ 217 #define STP4020_WINDOW_SHIFT 20 /* for 1MB */ 218 219 /* 220 * PC card Window Control register 0 221 */ 222 #define STP4020_WCR0_rsvd 0x8000 /* reserved */ 223 #define STP4020_WCR0_CMDLNG_M 0x7c00 /* command strobe length bit mask */ 224 #define STP4020_WCR0_CMDLNG_S 10 /* command strobe length bit shift */ 225 #define STP4020_WCR0_CMDDLY_M 0x0300 /* command strobe delay bit mask */ 226 #define STP4020_WCR0_CMDDLY_S 8 /* command strobe delay bit shift */ 227 #define STP4020_MEM_SPEED_MIN 100 228 #define STP4020_MEM_SPEED_MAX 1370 229 /* 230 * The ASPSEL (Address Space Select) bits control which of the three PC card 231 * address spaces this window maps in. 232 */ 233 #define STP4020_WCR0_ASPSEL_M 0x00c0 /* address space select bit mask */ 234 #define STP4020_WCR0_ASPSEL_AM 0x0000 /* attribute memory */ 235 #define STP4020_WCR0_ASPSEL_CM 0x0040 /* common memory */ 236 #define STP4020_WCR0_ASPSEL_IO 0x0080 /* I/O */ 237 /* 238 * The base address controls which 1MB range in the 64MB card address space 239 * this window maps to. 240 */ 241 #define STP4020_WCR0_BASE_M 0x0003f /* base address bit mask */ 242 #define STP4020_WCR0_BASE_S 0 /* base address bit shift */ 243 244 #define STP4020_ADDR2PAGE(x) ((x) >> 20) 245 246 /* 247 * PC card Window Control register 1 248 */ 249 #define STP4020_WCR1_rsvd 0xffe0 /* reserved */ 250 #define STP4020_WCR1_RECDLY_M 0x0018 /* recovery delay bit mask */ 251 #define STP4020_WCR1_RECDLY_S 3 /* recovery delay bit shift */ 252 #define STP4020_WCR1_WAITDLY_M 0x0006 /* *WAIT signal delay bit mask */ 253 #define STP4020_WCR1_WAITDLY_S 1 /* *WAIT signal delay bit shift */ 254 #define STP4020_WCR1_WAITREQ_M 0x0001 /* *WAIT signal is required bit mask */ 255 #define STP4020_WCR1_WAITREQ_S 0 /* *WAIT signal is required bit shift */ 256 257 #if for_reference_only 258 /* 259 * STP4020 CSR structures 260 * 261 * There is one stp4020_regs_t structure per instance, and it refers to 262 * the complete Stp4020 register set. 263 * 264 * For each socket, there is one stp4020_socket_csr_t structure, which 265 * refers to all the registers for that socket. That structure is 266 * made up of the window register structures as well as the registers 267 * that control overall socket operation. 268 * 269 * For each window, there is one stp4020_window_ctl_t structure, which 270 * refers to all the registers for that window. 271 */ 272 273 /* 274 * per-window CSR structure 275 */ 276 typedef struct stp4020_window_ctl_t { 277 volatile ushort_t ctl0; /* window control register 0 */ 278 volatile ushort_t ctl1; /* window control register 1 */ 279 } stp4020_window_ctl_t; 280 281 /* 282 * per-socket CSR structure 283 */ 284 typedef struct stp4020_socket_csr_t { 285 volatile struct stp4020_window_ctl_t window[STP4020_NWIN]; 286 volatile ushort_t ctl0; /* socket control register 0 */ 287 volatile ushort_t ctl1; /* socket control register 1 */ 288 volatile ushort_t stat0; /* socket status register 0 */ 289 volatile ushort_t stat1; /* socket status register 1 */ 290 volatile uchar_t filler[12]; /* filler space */ 291 } stp4020_socket_csr_t; 292 293 /* 294 * per-instance CSR structure 295 */ 296 typedef struct stp4020_regs_t { 297 struct stp4020_socket_csr_t socket[STP4020_NSOCK]; /* socket CSRs */ 298 } stp4020_regs_t; 299 #endif /* reference */ 300 301 /* Size of control and status register banks */ 302 #define STP4020_SOCKREGS_SIZE 32 303 #define STP4020_WINREGS_SIZE 4 304 305 /* Relative socket control & status register offsets */ 306 #define STP4020_ICR0_IDX 12 307 #define STP4020_ICR1_IDX 14 308 #define STP4020_ISR0_IDX 16 309 #define STP4020_ISR1_IDX 18 310 311 /* Relative Window control register offsets */ 312 #define STP4020_WCR0_IDX 0 313 #define STP4020_WCR1_IDX 2 314 315 /* Socket control and status register offsets */ 316 #define STP4020_ICR0_REG(s) ((32 * (s)) + STP4020_ICR0_IDX) 317 #define STP4020_ICR1_REG(s) ((32 * (s)) + STP4020_ICR1_IDX) 318 #define STP4020_ISR0_REG(s) ((32 * (s)) + STP4020_ISR0_IDX) 319 #define STP4020_ISR1_REG(s) ((32 * (s)) + STP4020_ISR1_IDX) 320 321 /* Window control and status registers; one set per socket */ 322 #define STP4020_WCR0_REG(s,w) ((32 * (s)) + (4 * (w)) + STP4020_WCR0_IDX) 323 #define STP4020_WCR1_REG(s,w) ((32 * (s)) + (4 * (w)) + STP4020_WCR1_IDX) 324 325 #endif /* _STP4020_REG_H */ 326
Indexes created Thu Oct 02 14:10:14 GMT 2025