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      1 /* $NetBSD: sunxi_rsb.c,v 1.16 2025/09/16 11:55:17 thorpej Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2014-2017 Jared McNeill <jmcneill (at) invisible.ca>
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  * SUCH DAMAGE.
     27  */
     28 
     29 #include <sys/cdefs.h>
     30 __KERNEL_RCSID(0, "$NetBSD: sunxi_rsb.c,v 1.16 2025/09/16 11:55:17 thorpej Exp $");
     31 
     32 #include <sys/param.h>
     33 #include <sys/bus.h>
     34 #include <sys/device.h>
     35 #include <sys/intr.h>
     36 #include <sys/systm.h>
     37 #include <sys/kernel.h>
     38 #include <sys/mutex.h>
     39 #include <sys/condvar.h>
     40 
     41 #include <dev/i2c/i2cvar.h>
     42 
     43 #include <dev/fdt/fdtvar.h>
     44 
     45 #include <arm/sunxi/sunxi_rsb.h>
     46 
     47 enum sunxi_rsb_type {
     48 	SUNXI_P2WI,
     49 	SUNXI_RSB,
     50 };
     51 
     52 static const struct device_compatible_entry compat_data[] = {
     53 	{ .compat = "allwinner,sun6i-a31-p2wi",	.value = SUNXI_P2WI },
     54 	{ .compat = "allwinner,sun8i-a23-rsb",	.value = SUNXI_RSB },
     55 	DEVICE_COMPAT_EOL
     56 };
     57 
     58 #define RSB_ADDR_PMIC_PRIMARY	0x3a3
     59 #define RSB_ADDR_PMIC_SECONDARY	0x745
     60 #define RSB_ADDR_PERIPH_IC	0xe89
     61 
     62 /*
     63  * Device address to Run-time address mappings.
     64  *
     65  * Run-time address (RTA) is an 8-bit value used to address the device during
     66  * a read or write transaction. The following are valid RTAs:
     67  *  0x17 0x2d 0x3a 0x4e 0x59 0x63 0x74 0x8b 0x9c 0xa6 0xb1 0xc5 0xd2 0xe8 0xff
     68  *
     69  * Allwinner uses RTA 0x2d for the primary PMIC, 0x3a for the secondary PMIC,
     70  * and 0x4e for the peripheral IC (where applicable).
     71  */
     72 static const struct {
     73 	uint16_t        addr;
     74 	uint8_t         rta;
     75 } rsb_rtamap[] = {
     76 	{ .addr = RSB_ADDR_PMIC_PRIMARY,	.rta = 0x2d },
     77 	{ .addr = RSB_ADDR_PMIC_SECONDARY,	.rta = 0x3a },
     78 	{ .addr = RSB_ADDR_PERIPH_IC,		.rta = 0x4e },
     79 	{ .addr = 0,				.rta = 0 }
     80 };
     81 
     82 struct sunxi_rsb_softc {
     83 	device_t sc_dev;
     84 	bus_space_tag_t sc_bst;
     85 	bus_space_handle_t sc_bsh;
     86 	enum sunxi_rsb_type sc_type;
     87 	struct i2c_controller sc_ic;
     88 	kmutex_t sc_intr_lock;
     89 	kcondvar_t sc_intr_wait;
     90 	device_t sc_i2cdev;
     91 	void *sc_ih;
     92 	uint32_t sc_stat;
     93 	bool sc_busy;
     94 
     95 	uint16_t sc_rsb_last_da;
     96 };
     97 
     98 #define RSB_READ(sc, reg) \
     99     bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
    100 #define RSB_WRITE(sc, reg, val) \
    101     bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
    102 
    103 static int	sunxi_rsb_exec(void *, i2c_op_t, i2c_addr_t, const void *,
    104 			       size_t, void *, size_t, int);
    105 
    106 static int	sunxi_rsb_intr(void *);
    107 static int	sunxi_rsb_wait(struct sunxi_rsb_softc *, int);
    108 static int	sunxi_rsb_rsb_config(struct sunxi_rsb_softc *,
    109 				     uint8_t, i2c_addr_t, int);
    110 
    111 static int	sunxi_rsb_match(device_t, cfdata_t, void *);
    112 static void	sunxi_rsb_attach(device_t, device_t, void *);
    113 
    114 CFATTACH_DECL_NEW(sunxi_rsb, sizeof(struct sunxi_rsb_softc),
    115 	sunxi_rsb_match, sunxi_rsb_attach, NULL, NULL);
    116 
    117 static int
    118 sunxi_rsb_match(device_t parent, cfdata_t cf, void *aux)
    119 {
    120 	struct fdt_attach_args * const faa = aux;
    121 
    122 	return of_compatible_match(faa->faa_phandle, compat_data);
    123 }
    124 
    125 static void
    126 sunxi_rsb_attach(device_t parent, device_t self, void *aux)
    127 {
    128 	struct sunxi_rsb_softc * const sc = device_private(self);
    129 	struct fdt_attach_args * const faa = aux;
    130 	const int phandle = faa->faa_phandle;
    131 	struct fdtbus_reset *rst;
    132 	struct clk *clk;
    133 	char intrstr[128];
    134 	bus_addr_t addr;
    135 	bus_size_t size;
    136 
    137 	if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
    138 		aprint_error(": couldn't get registers\n");
    139 		return;
    140 	}
    141 
    142 	if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) {
    143 		aprint_error(": couldn't decode interrupt\n");
    144 		return;
    145 	}
    146 
    147 	if ((clk = fdtbus_clock_get_index(phandle, 0)) != NULL)
    148 		if (clk_enable(clk) != 0) {
    149 			aprint_error(": couldn't enable clock\n");
    150 			return;
    151 		}
    152 	if ((rst = fdtbus_reset_get_index(phandle, 0)) != NULL)
    153 		if (fdtbus_reset_deassert(rst) != 0) {
    154 			aprint_error(": couldn't de-assert reset\n");
    155 			return;
    156 		}
    157 
    158 	sc->sc_dev = self;
    159 	sc->sc_type = of_compatible_lookup(phandle, compat_data)->value;
    160 	sc->sc_bst = faa->faa_bst;
    161 	if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
    162 		aprint_error(": couldn't map registers\n");
    163 		return;
    164 	}
    165 
    166 	mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED);
    167 	cv_init(&sc->sc_intr_wait, "sunxirsb");
    168 
    169 	aprint_naive("\n");
    170 	aprint_normal(": %s\n", sc->sc_type == SUNXI_P2WI ? "P2WI" : "RSB");
    171 
    172 	sc->sc_ih = fdtbus_intr_establish_xname(phandle, 0, IPL_VM, 0,
    173 	    sunxi_rsb_intr, sc, device_xname(self));
    174 	if (sc->sc_ih == NULL) {
    175 		aprint_error_dev(self, "couldn't establish interrupt on %s\n",
    176 		    intrstr);
    177 		return;
    178 	}
    179 	aprint_normal_dev(self, "interrupting on %s\n", intrstr);
    180 
    181 	iic_tag_init(&sc->sc_ic);
    182 	sc->sc_ic.ic_cookie = sc;
    183 	sc->sc_ic.ic_exec = sunxi_rsb_exec;
    184 
    185 	iicbus_attach(self, &sc->sc_ic);
    186 }
    187 
    188 static int
    189 sunxi_rsb_intr(void *priv)
    190 {
    191 	struct sunxi_rsb_softc *sc = priv;
    192 	uint32_t stat;
    193 
    194 	stat = RSB_READ(sc, RSB_STAT_REG);
    195 	if ((stat & RSB_STAT_MASK) == 0)
    196 		return 0;
    197 
    198 	RSB_WRITE(sc, RSB_STAT_REG, stat & RSB_STAT_MASK);
    199 
    200 	mutex_enter(&sc->sc_intr_lock);
    201 	sc->sc_stat |= stat;
    202 	cv_broadcast(&sc->sc_intr_wait);
    203 	mutex_exit(&sc->sc_intr_lock);
    204 
    205 	return 1;
    206 }
    207 
    208 static int
    209 sunxi_rsb_soft_reset(struct sunxi_rsb_softc *sc)
    210 {
    211 	int retry = 1000;
    212 
    213 	RSB_WRITE(sc, RSB_CTRL_REG, RSB_CTRL_SOFT_RESET);
    214 	while (--retry > 0) {
    215 		if ((RSB_READ(sc, RSB_CTRL_REG) & RSB_CTRL_SOFT_RESET) == 0)
    216 			break;
    217 		delay(10);
    218 	}
    219 	if (retry == 0)
    220 		return EIO;
    221 
    222 	return 0;
    223 }
    224 
    225 static int
    226 sunxi_rsb_wait(struct sunxi_rsb_softc *sc, int flags)
    227 {
    228 	int error = 0, retry;
    229 
    230 	/* Wait up to 5 seconds for a transfer to complete */
    231 	sc->sc_stat = 0;
    232 	for (retry = (flags & I2C_F_POLL) ? 100 : 5; retry > 0; retry--) {
    233 		if (flags & I2C_F_POLL) {
    234 			sc->sc_stat |= RSB_READ(sc, RSB_STAT_REG);
    235 		} else {
    236 			error = cv_timedwait(&sc->sc_intr_wait,
    237 					     &sc->sc_intr_lock, hz);
    238 			if (error && error != EWOULDBLOCK) {
    239 				break;
    240 			}
    241 		}
    242 		if (sc->sc_stat & RSB_STAT_MASK) {
    243 			break;
    244 		}
    245 		if (flags & I2C_F_POLL) {
    246 			delay(10000);
    247 		}
    248 	}
    249 	if (retry == 0)
    250 		error = EAGAIN;
    251 
    252 	if (flags & I2C_F_POLL) {
    253 		RSB_WRITE(sc, RSB_STAT_REG,
    254 		    sc->sc_stat & RSB_STAT_MASK);
    255 	}
    256 
    257 	if (error) {
    258 		/* Abort transaction */
    259 		device_printf(sc->sc_dev, "transfer timeout, error = %d\n",
    260 		    error);
    261 		RSB_WRITE(sc, RSB_CTRL_REG,
    262 		    RSB_CTRL_ABORT_TRANS);
    263 		return error;
    264 	}
    265 
    266 	if (sc->sc_stat & RSB_STAT_LOAD_BSY) {
    267 		device_printf(sc->sc_dev, "transfer busy\n");
    268 		return EBUSY;
    269 	}
    270 	if (sc->sc_stat & RSB_STAT_TRANS_ERR) {
    271 		device_printf(sc->sc_dev, "transfer error, id 0x%02" PRIx64
    272 		    "\n", __SHIFTOUT(sc->sc_stat, RSB_STAT_TRANS_ERR_ID));
    273 		return EIO;
    274 	}
    275 
    276 	return 0;
    277 }
    278 
    279 static int
    280 sunxi_rsb_rsb_config(struct sunxi_rsb_softc *sc, uint8_t rta, i2c_addr_t da,
    281     int flags)
    282 {
    283 	uint32_t dar, ctrl;
    284 
    285 	KASSERT(mutex_owned(&sc->sc_intr_lock));
    286 
    287 	RSB_WRITE(sc, RSB_STAT_REG,
    288 	    RSB_READ(sc, RSB_STAT_REG) & RSB_STAT_MASK);
    289 
    290 	dar = __SHIFTIN(rta, RSB_DAR_RTA);
    291 	dar |= __SHIFTIN(da, RSB_DAR_DA);
    292 	RSB_WRITE(sc, RSB_DAR_REG, dar);
    293 	RSB_WRITE(sc, RSB_CMD_REG, RSB_CMD_IDX_SRTA);
    294 
    295 	/* Make sure the controller is idle */
    296 	ctrl = RSB_READ(sc, RSB_CTRL_REG);
    297 	if (ctrl & RSB_CTRL_START_TRANS) {
    298 		device_printf(sc->sc_dev, "device is busy\n");
    299 		return EBUSY;
    300 	}
    301 
    302 	/* Start the transfer */
    303 	RSB_WRITE(sc, RSB_CTRL_REG,
    304 	    ctrl | RSB_CTRL_START_TRANS);
    305 
    306 	return sunxi_rsb_wait(sc, flags);
    307 }
    308 
    309 static int
    310 sunxi_rsb_exec(void *priv, i2c_op_t op, i2c_addr_t addr,
    311     const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags)
    312 {
    313 	struct sunxi_rsb_softc *sc = priv;
    314 	uint32_t dlen, ctrl;
    315 	uint8_t rta;
    316 	int error, i;
    317 
    318 	if (cmdlen != 1 || (len != 1 && len != 2 && len != 4))
    319 		return EINVAL;
    320 
    321 	mutex_enter(&sc->sc_intr_lock);
    322 
    323 	error = sunxi_rsb_soft_reset(sc);
    324 	if (error != 0) {
    325 		mutex_exit(&sc->sc_intr_lock);
    326 		device_printf(sc->sc_dev, "soft reset timed out\n");
    327 		return error;
    328 	}
    329 
    330 	if ((flags & I2C_F_POLL) == 0) {
    331 		/* Enable interrupts */
    332 		RSB_WRITE(sc, RSB_INTE_REG,
    333 		    RSB_INTE_LOAD_BSY_ENB |
    334 		    RSB_INTE_TRANS_ERR_ENB |
    335 		    RSB_INTE_TRANS_OVER_ENB);
    336 		RSB_WRITE(sc, RSB_CTRL_REG,
    337 		    RSB_CTRL_GLOBAL_INT_ENB);
    338 	}
    339 
    340 	if (sc->sc_type == SUNXI_RSB && sc->sc_rsb_last_da != addr) {
    341 		/* Lookup run-time address for given device address */
    342 		for (rta = 0, i = 0; rsb_rtamap[i].rta != 0; i++)
    343 			if (rsb_rtamap[i].addr == addr) {
    344 				rta = rsb_rtamap[i].rta;
    345 				break;
    346 			}
    347 		if (rta == 0) {
    348 			mutex_exit(&sc->sc_intr_lock);
    349 			device_printf(sc->sc_dev,
    350 			    "RTA not known for address %#x\n", addr);
    351 			return ENXIO;
    352 		}
    353 		error = sunxi_rsb_rsb_config(sc, rta, addr, flags);
    354 		if (error) {
    355 			device_printf(sc->sc_dev,
    356 			    "SRTA failed, flags = %x, error = %d\n",
    357 			    flags, error);
    358 			sc->sc_rsb_last_da = 0;
    359 			goto done;
    360 		}
    361 
    362 		sc->sc_rsb_last_da = addr;
    363 	}
    364 
    365 	/* Data byte register */
    366 	RSB_WRITE(sc, RSB_DADDR0_REG, *(const uint8_t *)cmdbuf);
    367 
    368 	if (I2C_OP_WRITE_P(op)) {
    369 		uint8_t *pbuf = buf;
    370 		uint32_t data;
    371 		/* Write data */
    372 		switch (len) {
    373 		case 1:
    374 			data = pbuf[0];
    375 			break;
    376 		case 2:
    377 			data = pbuf[0] | (pbuf[1] << 8);
    378 			break;
    379 		case 4:
    380 			data = pbuf[0] | (pbuf[1] << 8) |
    381 			    (pbuf[2] << 16) | (pbuf[3] << 24);
    382 			break;
    383 		default:
    384 			error = EINVAL;
    385 			goto done;
    386 		}
    387 		RSB_WRITE(sc, RSB_DATA0_REG, data);
    388 	}
    389 
    390 	if (sc->sc_type == SUNXI_RSB) {
    391 		uint8_t cmd;
    392 		if (I2C_OP_WRITE_P(op)) {
    393 			switch (len) {
    394 			case 1:	cmd = RSB_CMD_IDX_WR8; break;
    395 			case 2: cmd = RSB_CMD_IDX_WR16; break;
    396 			case 4: cmd = RSB_CMD_IDX_WR32; break;
    397 			default: error = EINVAL; goto done;
    398 			}
    399 		} else {
    400 			switch (len) {
    401 			case 1:	cmd = RSB_CMD_IDX_RD8; break;
    402 			case 2: cmd = RSB_CMD_IDX_RD16; break;
    403 			case 4: cmd = RSB_CMD_IDX_RD32; break;
    404 			default: error = EINVAL; goto done;
    405 			}
    406 		}
    407 		RSB_WRITE(sc, RSB_CMD_REG, cmd);
    408 	}
    409 
    410 	/* Program data length register; if reading, set read/write bit */
    411 	dlen = __SHIFTIN(len - 1, RSB_DLEN_ACCESS_LENGTH);
    412 	if (I2C_OP_READ_P(op)) {
    413 		dlen |= RSB_DLEN_READ_WRITE_FLAG;
    414 	}
    415 	RSB_WRITE(sc, RSB_DLEN_REG, dlen);
    416 
    417 	/* Make sure the controller is idle */
    418 	ctrl = RSB_READ(sc, RSB_CTRL_REG);
    419 	if (ctrl & RSB_CTRL_START_TRANS) {
    420 		device_printf(sc->sc_dev, "device is busy\n");
    421 		error = EBUSY;
    422 		goto done;
    423 	}
    424 
    425 	/* Start the transfer */
    426 	RSB_WRITE(sc, RSB_CTRL_REG,
    427 	    ctrl | RSB_CTRL_START_TRANS);
    428 
    429 	error = sunxi_rsb_wait(sc, flags);
    430 	if (error)
    431 		goto done;
    432 
    433 	if (I2C_OP_READ_P(op)) {
    434 		uint32_t data = RSB_READ(sc, RSB_DATA0_REG);
    435 		switch (len) {
    436 		case 4:
    437 			*(uint32_t *)buf = data;
    438 			break;
    439 		case 2:
    440 			*(uint16_t *)buf = data & 0xffff;
    441 			break;
    442 		case 1:
    443 			*(uint8_t *)buf = data & 0xff;
    444 			break;
    445 		default:
    446 			error = EINVAL;
    447 			goto done;
    448 		}
    449 	}
    450 
    451 	error = 0;
    452 
    453 done:
    454 	RSB_WRITE(sc, RSB_CTRL_REG, 0);
    455 	mutex_exit(&sc->sc_intr_lock);
    456 
    457 	return error;
    458 }
    459