| /src/external/apache2/llvm/dist/llvm/lib/DebugInfo/DWARF/ |
| DWARFDie.cpp | 43 uint64_t Shift = countTrailingZeros(Val);
44 assert(Shift < 64 && "undefined behavior");
45 uint64_t Bit = 1ULL << Shift;
|
| /src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| CodeBeadsGen.cpp | 103 unsigned Shift = i % 8;
105 Value |= (static_cast<uint8_t>(B->getValue()) << Shift);
|
| /src/external/apache2/llvm/dist/clang/include/clang/Basic/ |
| OperatorPrecedence.h | 39 Shift = 12, // <<, >>
|
| /src/external/apache2/llvm/dist/llvm/lib/Support/ |
| ScaledNumber.cpp | 46 // Shift as little as possible to maximize precision.
48 int Shift = 64 - LeadingZeros;
50 Upper = Upper << LeadingZeros | Lower >> Shift;
51 return getRounded(Upper, Shift,
52 Shift && (Lower & UINT64_C(1) << (Shift - 1)));
64 int Shift = 0;
66 Shift -= Zeros;
74 return getAdjusted<uint32_t>(Quotient, Shift);
77 return getRounded<uint32_t>(Quotient, Shift, Remainder >= getHalf(Divisor))
[all...] |
| KnownBits.cpp | 171 // If the shift amount is a valid constant then transform LHS directly.
173 unsigned Shift = RHS.getConstant().getZExtValue();
175 Known.Zero <<= Shift;
176 Known.One <<= Shift;
178 Known.Zero.setLowBits(Shift);
182 // No matter the shift amount, the trailing zeros will stay zero.
185 // Minimum shift amount low bits are known zero.
192 // If the maximum shift is in range, then find the common bits from all
198 assert(MinShiftAmount.ult(MaxShiftAmount) && "Illegal shift range");
204 // Skip if the shift amount is impossible
[all...] |
| /src/external/apache2/llvm/dist/clang/include/clang/Tooling/ASTDiff/ |
| ASTDiff.h | 39 int Depth, Height, Shift = 0;
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/ADT/ |
| Bitfields.h | 96 /// undefined operations over signed types (e.g. Bitwise shift operators).
166 static constexpr StorageType Mask = BP::Umax << Bitfield::Shift;
173 Packed |= StorageValue << Bitfield::Shift;
179 const StorageType StorageValue = (Packed & Mask) >> Bitfield::Shift;
227 static constexpr unsigned Shift = Offset;
230 static constexpr unsigned LastBit = Shift + Bits - 1;
231 static constexpr unsigned NextBit = Shift + Bits;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ExpandImm.cpp | 269 unsigned Shift = 0; // LSL amount for high bits with MOVZ/MOVN
274 Shift = (TZ / 16) * 16;
277 unsigned Imm16 = (Imm >> Shift) & Mask;
280 AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift) });
282 if (Shift == LastShift)
291 while (Shift < LastShift) {
292 Shift += 16;
293 Imm16 = (Imm >> Shift) & Mask;
298 AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift) });
312 for (unsigned Shift = 0; Shift < BitSize; Shift += 16)
[all...] |
| AArch64RedundantCopyElimination.cpp | 198 int32_t Shift = PredI.getOperand(3).getImm();
199 KnownImm <<= Shift;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsISelLowering.h | 201 // DSP shift nodes.
459 SDValue Shift = DAG.getNode(ISD::SHL, DL, Ty, HigherPart, Cst);
460 SDValue Add = DAG.getNode(ISD::ADD, DL, Ty, Shift,
|
| MipsLegalizerInfo.cpp | 380 auto Shift = MIRBuilder.buildLShr(s32, Val, C_P2Half_InBits);
381 MIRBuilder.buildStore(Shift, Addr, *RemMemOp);
|
| MicroMipsSizeReduction.cpp | 52 ImmField() : ImmFieldOperand(-1), Shift(0), LBound(0), HBound(0) {}
53 ImmField(uint8_t Shift, int16_t LBound, int16_t HBound,
55 : ImmFieldOperand(ImmFieldOperand), Shift(Shift), LBound(LBound),
58 uint8_t Shift; // Shift value
105 uint8_t Shift() const { return Imm.Shift; }
213 // ImmField(Shift, LBound, HBound, ImmFieldPosition)
326 // bits equal to Shift and if the shifted value is between the bounds
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCCodeEmitter.cpp | 601 unsigned Shift = HexagonMCInstrInfo::getExtentAlignment(MCII, MI);
602 Value = (Value & 0x3f) << Shift;
642 unsigned Shift = HexagonMCInstrInfo::getExtentAlignment(MCII, MI);
647 assert(Shift < array_lengthof(GPRelFixups));
655 FixupKind = GPRelFixups[Shift];
|
| /src/external/apache2/llvm/dist/llvm/tools/obj2yaml/ |
| coff2yaml.cpp | 175 uint32_t Shift = (COFFSection->Characteristics >> 20) & 0xF;
176 NewYAMLSection.Alignment = (1U << Shift) >> 1;
|
| /src/external/bsd/libarchive/dist/libarchive/ |
| archive_ppmd_private.h | 93 #define PPMD_GET_MEAN_SPEC(summ, shift, round) (((summ) + (1 << ((shift) - (round)))) >> (shift))
108 Byte Shift; /* Speed of Freq change; low Shift is for fast change */
109 Byte Count; /* Count to next change of Shift */
113 if ((p)->Shift < PPMD_PERIOD_BITS && --(p)->Count == 0) { \
115 (p)->Count = (Byte)(3 << (p)->Shift++); \
|
| /src/external/apache2/llvm/dist/clang/lib/Format/ |
| WhitespaceManager.cpp | 268 int Shift = 0;
315 Shift = 0;
324 Shift = Column - Changes[i].StartOfTokenColumn;
325 Changes[i].Spaces += Shift;
361 Changes[i].Spaces += Shift;
365 Changes[i].Spaces += Shift;
367 assert(Shift >= 0);
368 Changes[i].StartOfTokenColumn += Shift;
370 Changes[i + 1].PreviousEndOfTokenColumn += Shift;
554 int Shift = 0
[all...] |
| /src/external/apache2/llvm/dist/clang/lib/Tooling/Core/ |
| Replacement.cpp | 536 int Shift = 0;
538 unsigned Offset = R.getOffset() + Shift;
540 Shift += Length - R.getLength();
|
| /src/external/apache2/llvm/dist/llvm/lib/Analysis/ |
| BlockFrequencyInfoImpl.cpp | 214 static uint64_t shiftRightAndRound(uint64_t N, int Shift) {
215 assert(Shift >= 0);
216 assert(Shift < 64);
217 if (!Shift)
219 return (N >> Shift) + (UINT64_C(1) & N >> (Shift - 1));
238 // Determine how much to shift right so that the total fits into 32-bits.
240 // If we shift at all, shift by 1 extra. Otherwise, the lower limit of 1
242 int Shift = 0
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/ |
| RuntimeDyldMachOARM.h | 73 // Now we've got the shifted immediate, shift by 2, sign extend and ret.
406 unsigned Shift = (HalfDiffKindBits & 0x1) ? 16 : 0;
407 uint32_t FullImmVal = (Immediate << Shift) | (OtherHalf << (16 - Shift));
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonStoreWidening.cpp | 401 unsigned Shift = 0;
411 unsigned Val = (SO.getImm() & Mask) << Shift;
413 Shift += NBits;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsMCCodeEmitter.cpp | 58 // If the D<shift> instruction has a shift amount that is greater
59 // than 31 (checked in calling routine), lower it to a D<shift>32 instruction
61 assert(Inst.getNumOperands() == 3 && "Invalid no. of operands for shift!");
64 int64_t Shift = Inst.getOperand(2).getImm();
65 if (Shift <= 31)
67 Shift -= 32;
70 Inst.getOperand(2).setImm(Shift);
75 llvm_unreachable("Unexpected shift instruction");
144 unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/Support/ |
| ScaledNumber.h | 87 // Shift right and round.
88 int Shift = 64 - Width - countLeadingZeros(Digits);
89 return getRounded<DigitsT>(Digits >> Shift, Scale + Shift,
90 Digits & (UINT64_C(1) << (Shift - 1)));
276 /// scales in place. Shift the digits as necessary to form equivalent numbers,
306 // Shift LDigits left as much as possible, then shift RDigits right.
308 assert(ShiftL < getWidth<DigitsT>() && "can't shift more than width");
623 ScaledNumber &operator<<=(int16_t Shift) {
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/MC/ |
| MCAsmStreamer.cpp | 1234 uint64_t Shift = 64 - EmissionSize * 8;
1235 assert(Shift < static_cast<uint64_t>(
1238 ValueToEmit &= ~0ULL >> Shift;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | 206 template<unsigned Bits, unsigned Shift>
217 /// getMveAddrModeQOpValue - Return encoding info for 'reg +/- imm7<<{shift}'
219 template<int shift>
244 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
355 template<unsigned Bits, unsigned Shift>
445 unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
446 EmitByte((Val >> Shift) & 0xff, OS);
1027 template<unsigned Bits, unsigned Shift>
1048 Imm >>= Shift;
1078 template<int shift>
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/ |
| IntegerDivision.cpp | 36 ConstantInt *Shift;
39 Shift = Builder.getInt64(63);
42 Shift = Builder.getInt32(31);
45 // Following instructions are generated for both i32 (shift 31) and
46 // i64 (shift 63).
57 Value *DividendSign = Builder.CreateAShr(Dividend, Shift);
58 Value *DivisorSign = Builder.CreateAShr(Divisor, Shift);
108 ConstantInt *Shift;
111 Shift = Builder.getInt64(63);
114 Shift = Builder.getInt32(31)
[all...] |
