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  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
CalcSpillWeights.cpp 49 unsigned Sub, HSub;
52 Sub = MI->getOperand(0).getSubReg();
56 Sub = MI->getOperand(1).getSubReg();
65 return Sub == HSub ? HReg : Register();
72 // Check if reg:sub matches so that a super register could be hinted.
73 if (Sub)
74 return TRI.getMatchingSuperReg(CopiedPReg, Sub, rc);
  /src/external/apache2/llvm/dist/llvm/lib/MC/MCDisassembler/
MCExternalSymbolizer.cpp 100 const MCExpr *Sub = nullptr;
105 Sub = MCSymbolRefExpr::create(Sym, Ctx);
107 Sub = MCConstantExpr::create((int)SymbolicOp.SubtractSymbol.Value, Ctx);
116 if (Sub) {
119 LHS = MCBinaryExpr::createSub(Add, Sub, Ctx);
121 LHS = MCUnaryExpr::createMinus(Sub, Ctx);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Disassembler/
AArch64ExternalSymbolizer.cpp 182 const MCExpr *Sub = nullptr;
187 Sub = MCSymbolRefExpr::create(Sym, Ctx);
189 Sub = MCConstantExpr::create(SymbolicOp.SubtractSymbol.Value, Ctx);
198 if (Sub) {
201 LHS = MCBinaryExpr::createSub(Add, Sub, Ctx);
203 LHS = MCUnaryExpr::createMinus(Sub, Ctx);
  /src/sys/external/bsd/compiler_rt/dist/lib/sanitizer_common/
sanitizer_allocator_stats.h 39 void Sub(AllocatorStat i, uptr v) {
  /src/external/gpl3/gcc/dist/libsanitizer/sanitizer_common/
sanitizer_allocator_stats.h 33 void Sub(AllocatorStat i, uptr v) {
  /src/external/gpl3/gcc.old/dist/libsanitizer/sanitizer_common/
sanitizer_allocator_stats.h 38 void Sub(AllocatorStat i, uptr v) {
  /src/external/apache2/llvm/dist/clang/lib/AST/Interp/
Interp.h 97 // Add, Sub, Mul
140 bool Sub(InterpState &S, CodePtr OpPC) {
144 return AddSubMulHelper<T, T::sub, std::minus>(S, OpPC, Bits, LHS, RHS);
  /src/external/apache2/llvm/dist/llvm/examples/Fibonacci/
fibonacci.cpp 83 Value *Sub = BinaryOperator::CreateSub(ArgX, One, "arg", RecurseBB);
84 CallInst *CallFibX1 = CallInst::Create(FibF, Sub, "fibx1", RecurseBB);
88 Sub = BinaryOperator::CreateSub(ArgX, Two, "arg", RecurseBB);
89 CallInst *CallFibX2 = CallInst::Create(FibF, Sub, "fibx2", RecurseBB);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsMCInstLower.cpp 209 const MCBinaryExpr *Sub = MCBinaryExpr::createSub(Sym1, Sym2, *Ctx);
211 return MCOperand::createExpr(MipsMCExpr::create(Kind, Sub, *Ctx));
  /src/external/apache2/llvm/dist/llvm/lib/TableGen/
SetTheory.cpp 46 // (sub Add, Sub, ...) Set difference.
53 RecSet Add, Sub;
55 ST.evaluate(Expr->arg_begin() + 1, Expr->arg_end(), Sub, Loc);
57 if (!Sub.count(I))
259 addOperator("sub", std::make_unique<SubOp>());
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonBlockRanges.h 37 unsigned Sub;
40 return Reg < R.Reg || (Reg == R.Reg && Sub < R.Sub);
BitTracker.h 142 RegisterRef(Register R = 0, unsigned S = 0) : Reg(R), Sub(S) {}
144 : Reg(MO.getReg()), Sub(MO.getSubReg()) {}
147 unsigned Sub;
458 // Return a sub-register mask that indicates which bits in Reg belong
459 // to the subregister Sub. These bits are assumed to be contiguous in
460 // the super-register, and have the same ordering in the sub-register
462 // Sub == 0, in this case, the function should return a mask that spans
465 virtual BitMask mask(Register Reg, unsigned Sub) const;
HexagonAsmPrinter.cpp 443 const MCExpr *Sub = MCBinaryExpr::createSub(Expr, One, OutContext);
445 MCOperand::createExpr(HexagonMCExpr::create(Sub, OutContext)));
479 const MCExpr *Sub = MCBinaryExpr::createSub(Expr, One, OutContext);
481 MCOperand::createExpr(HexagonMCExpr::create(Sub, OutContext)));
506 const MCExpr *Sub = MCBinaryExpr::createSub(Expr, One, OutContext);
508 MCOperand::createExpr(HexagonMCExpr::create(Sub, OutContext)));
HexagonExpandCondsets.cpp 180 Sub(Op.getSubReg()) {}
181 RegisterRef(unsigned R = 0, unsigned S = 0) : Reg(R), Sub(S) {}
184 return Reg == RR.Reg && Sub == RR.Sub;
188 return Reg < RR.Reg || (Reg == RR.Reg && Sub < RR.Sub);
192 unsigned Sub;
199 unsigned getMaskForSub(unsigned Sub);
201 LaneBitmask getLaneMask(Register Reg, unsigned Sub);
261 unsigned HexagonExpandCondsets::getMaskForSub(unsigned Sub) {
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86WinAllocaExpander.cpp 44 enum Lowering { TouchAndSub, Sub, Probe };
105 return Sub;
163 case Sub:
230 case Sub:
238 // Sub.
256 // Sub
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
DivRemPairs.cpp 271 Instruction *Sub = BinaryOperator::CreateSub(X, Mul);
283 // %rem = sub %x, %mul
285 // If the division dominates, it's already in the right place. The mul+sub
298 // %rem = sub %x, %mul
306 Sub->insertAfter(Mul);
315 // %rem = sub %x, %mul // %rem = undef - undef = undef
321 Sub->setOperand(0, FrX);
332 // (sub X, (mul (div X, Y), Y)
333 Sub->setName(RemInst->getName() + ".decomposed");
336 RemInst = Sub;
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/
RelLookupTableConverter.cpp 113 Constant *Sub = llvm::ConstantExpr::getSub(Target, Base);
115 llvm::ConstantExpr::getTrunc(Sub, Type::getInt32Ty(M.getContext()));
  /src/external/apache2/llvm/dist/llvm/examples/ParallelJIT/
ParallelJIT.cpp 114 Value *Sub = BinaryOperator::CreateSub(ArgX, One, "arg", RecurseBB);
115 Value *CallFibX1 = CallInst::Create(FibF, Sub, "fibx1", RecurseBB);
118 Sub = BinaryOperator::CreateSub(ArgX, Two, "arg", RecurseBB);
119 Value *CallFibX2 = CallInst::Create(FibF, Sub, "fibx2", RecurseBB);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
SparcAsmPrinter.cpp 97 const MCBinaryExpr *Sub = MCBinaryExpr::createSub(Cur, Start, OutContext);
98 const MCBinaryExpr *Add = MCBinaryExpr::createAdd(GOT, Sub, OutContext);
  /src/external/apache2/llvm/dist/llvm/lib/ExecutionEngine/RuntimeDyld/
RuntimeDyldChecker.cpp 91 Sub,
173 Op = BinOpToken::Sub;
193 case BinOpToken::Sub:
  /src/external/apache2/llvm/dist/clang/include/clang/Analysis/Analyses/
ThreadSafetyTraverse.h 498 void printSExpr(const SExpr *E, StreamType &SS, unsigned P, bool Sub=true) {
503 if (Sub && E->block() && E->opcode() != COP_Variable) {
824 bool Sub = false;
829 Sub = true;
834 self()->printSExpr(E, SS, Prec_MAX, Sub);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Disassembler/
AMDGPUDisassembler.cpp 276 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0);
277 auto Reg = Sub ? Sub : Op.getReg();
  /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
LanaiISelLowering.cpp 142 setTargetDAGCombine(ISD::SUB);
925 // Start by assuming a shift and a add/sub for every non-zero entry (hence
926 // every non-zero entry requires 1 shift and 1 add/sub except for the first
951 // Assemble multiplication from shift, add, sub using NAF form and running
964 Res = DAG.getNode(ISD::SUB, DL, VT, Res, Op);
1030 SDValue Sub = DAG.getNode(ISD::SUB, DL, MVT::i32, StackPointer, Size);
1042 SDValue ArgAdjust = DAG.getNode(LanaiISD::ADJDYNALLOC, DL, MVT::i32, Sub);
1044 // The Sub result contains the new stack start address, so it
1046 SDValue CopyChain = DAG.getCopyToReg(Chain, DL, SPReg, Sub);
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/
InstCombineMulDivRem.cpp 1500 Value *Sub = Builder.CreateSub(Op0, Op1);
1501 return SelectInst::Create(Cmp, Op0, Sub);
  /src/external/apache2/llvm/dist/clang/lib/CodeGen/
CGStmt.cpp 434 /// this captures the expression result of the last sub-statement and returns it
666 const Stmt *Sub = S.getSubStmt();
667 const ReturnStmt *R = cast<ReturnStmt>(Sub);

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