Home | History | Annotate | Line # | Download | only in altboot
      1 /* $NetBSD: wm.c,v 1.3 2021/09/03 21:55:00 andvar Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2007 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Tohru Nishimura.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 #include <sys/param.h>
     33 
     34 #include <netinet/in.h>
     35 #include <netinet/in_systm.h>
     36 
     37 #include <lib/libsa/stand.h>
     38 #include <lib/libsa/net.h>
     39 
     40 #include <dev/pci/if_wmreg.h>
     41 
     42 #include "globals.h"
     43 
     44 /*
     45  * - reverse endian access every CSR.
     46  * - no vtophys() translation, vaddr_t == paddr_t.
     47  * - PIPT writeback cache aware.
     48  */
     49 #define CSR_READ(l, r)		in32rb((l)->csr+(r))
     50 #define CSR_WRITE(l, r, v) 	out32rb((l)->csr+(r), (v))
     51 #define VTOPHYS(va) 		(uint32_t)(va)
     52 #define DEVTOV(pa) 		(uint32_t)(pa)
     53 #define wbinv(adr, siz)		_wbinv(VTOPHYS(adr), (uint32_t)(siz))
     54 #define inv(adr, siz)		_inv(VTOPHYS(adr), (uint32_t)(siz))
     55 #define DELAY(n)		delay(n)
     56 #define ALLOC(T,A)		(T *)allocaligned(sizeof(T),(A))
     57 
     58 struct tdesc {
     59 	uint32_t lo;	/* 31:0 */
     60 	uint32_t hi;	/* 63:32 */
     61 	uint32_t t2;	/* 31:16 command, 15:0 Tx frame length */
     62 	uint32_t t3;	/* 31:16 VTAG, 15:8 opt, 7:0 Tx status */
     63 };
     64 struct rdesc {
     65 	uint32_t lo;	/* 31:0 */
     66 	uint32_t hi;	/* 63:32 */
     67 	uint32_t r2;	/* 31:16 checksum, 15:0 Rx frame length */
     68 	uint32_t r3;	/* 31:16 special, 15:8 errors, 7:0 status */
     69 };
     70 /* T2 command */
     71 #define T2_FLMASK	0xffff		/* 15:0 */
     72 #define T2_DTYP_C	(1U << 20)	/* data descriptor */
     73 #define T2_EOP		(1U << 24)	/* end of packet */
     74 #define T2_IFCS		(1U << 25)	/* insert FCS */
     75 #define T2_RS		(1U << 27)	/* report status */
     76 #define T2_RPS		(1U << 28)	/* report packet sent */
     77 #define T2_DEXT		(1U << 29)	/* descriptor extension */
     78 #define T2_VLE		(1U << 30)	/* VLAN enable */
     79 #define T2_IDE		(1U << 31)	/* interrupt delay enable */
     80 /* T3 status */
     81 #define T3_DD		(1U << 0)	/* 1: Tx has done and vacant */
     82 /* T3 option */
     83 #define T3_IXSM		(1U << 16)	/* generate IP csum */
     84 #define T3_TXSM		(1U << 17)	/* generate TCP/UDP csum */
     85 
     86 #define R2_FLMASK	0xffff		/* 15:0 */
     87 /* R3 status */
     88 #define	R3_DD		(1U << 0)	/* 1: Rx frame loaded and available */
     89 #define R3_EOP		(1U << 1)	/* end of packet */
     90 #define R3_IXSM		(1U << 2)	/* ignore checksum indication */
     91 #define R3_VP		(1U << 3)	/* VLAN packet */
     92 #define R3_TCPCS	(1U << 5)	/* TCP csum performed */
     93 #define R3_IPCS		(1U << 6)	/* IP csum performed */
     94 #define R3_PIF		(1U << 7)	/* passed in-exact filter */
     95 /* R3 error status */
     96 #define R3_CE		(1U << 8)	/* CRC error */
     97 #define R3_SE		(1U << 9)	/* symbol error */
     98 #define R3_SEQ		(1U << 10)	/* sequence error */
     99 #define R3_CXE		(1U << 12)	/* carrier extension error */
    100 #define R3_TCPE		(1U << 13)	/* TCP csum error found */
    101 #define R3_IPE		(1U << 14)	/* IP csum error found */
    102 #define R3_RXE		(1U << 15)	/* Rx data error */
    103 
    104 #define FRAMESIZE	1536
    105 
    106 struct local {
    107 	struct tdesc txd[2];
    108 	struct rdesc rxd[2];
    109 	uint8_t rxstore[2][FRAMESIZE];
    110 	unsigned csr, tx, rx;
    111 	unsigned ctl, tctl, rctl;
    112 	unsigned phy, bmsr, anlpar;
    113 	int sromsft;
    114 };
    115 
    116 static int read_srom(struct local *, int);
    117 static unsigned mii_read(struct local *, int, int);
    118 static void mii_write(struct local *, int, int, int);
    119 static void mii_initphy(struct local *);
    120 static void mii_dealan(struct local *, unsigned);
    121 
    122 int
    123 wm_match(unsigned tag, void *data)
    124 {
    125 	unsigned v;
    126 
    127 	v = pcicfgread(tag, PCI_ID_REG);
    128 	switch (v) {
    129 	case PCI_DEVICE(0x8086, 0x107c):
    130 		return 1;
    131 	}
    132 	return 0;
    133 }
    134 
    135 void *
    136 wm_init(unsigned tag, void *data)
    137 {
    138 	unsigned val, fdx;
    139 	struct local *l;
    140 	struct tdesc *txd;
    141 	struct rdesc *rxd;
    142 	uint8_t *en;
    143 
    144 	l = ALLOC(struct local, 32); /* desc alignment */
    145 	memset(l, 0, sizeof(struct local));
    146 	l->csr = pcicfgread(tag, 0x10); /* use mem space */
    147 
    148 	CSR_WRITE(l, WMREG_TCTL, 0);
    149 	CSR_WRITE(l, WMREG_RCTL, 0);
    150 
    151 	mii_initphy(l);
    152 
    153 	l->sromsft = 6;
    154 	en = data;
    155 	val = read_srom(l, 0); en[0] = val; en[1] = (val >> 8);
    156 	val = read_srom(l, 1); en[2] = val; en[3] = (val >> 8);
    157 	val = read_srom(l, 2); en[4] = val; en[5] = (val >> 8);
    158 
    159 	printf("MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
    160 	    en[0], en[1], en[2], en[3], en[4], en[5]);
    161 	DPRINTF(("PHY %d (%04x.%04x)\n", l->phy,
    162 	    mii_read(l, l->phy, 2), mii_read(l, l->phy, 3)));
    163 
    164 	mii_dealan(l, 5);
    165 
    166 	/* speed and duplexity are found at 82451 internal GPHY reg 17 */
    167 	val = mii_read(l, l->phy, 0x11);
    168 	fdx = !!(val & 0x0200);
    169 	switch (val & 0xc000) {
    170 	case 0x4000: printf("10Mbps"); break;
    171 	case 0x8000: printf("100Mbps"); break;
    172 	case 0xc000: printf("1000Mbps"); break;
    173 	}
    174 	if (fdx)
    175 		printf("-FDX");
    176 	printf("\n");
    177 
    178 	txd = &l->txd[0];
    179 	rxd = &l->rxd[0];
    180 	rxd[0].lo = htole32(VTOPHYS(l->rxstore[0]));
    181 	rxd[0].r2 = 0;
    182 	rxd[0].r3 = 0;
    183 	rxd[1].lo = htole32(VTOPHYS(l->rxstore[1]));
    184 	rxd[1].r2 = 0;
    185 	rxd[0].r3 = 0;
    186 	l->tx = l->rx = 0;
    187 
    188 	CSR_WRITE(l, WMREG_TDBAH, 0);
    189 	CSR_WRITE(l, WMREG_TDBAL, VTOPHYS(txd));
    190 	CSR_WRITE(l, WMREG_TDLEN, sizeof(l->txd));
    191 	CSR_WRITE(l, WMREG_TDH, 0);
    192 	CSR_WRITE(l, WMREG_TDT, 0);
    193 	CSR_WRITE(l, WMREG_TIDV, 64);
    194 	CSR_WRITE(l, WMREG_TADV, 128);
    195 	CSR_WRITE(l, WMREG_TXDCTL, TXDCTL_PTHRESH(0) |
    196 	    TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0));
    197 	CSR_WRITE(l, WMREG_TQSA_LO, 0);
    198 	CSR_WRITE(l, WMREG_TQSA_HI, 0);
    199 
    200 	CSR_WRITE(l, WMREG_RDBAH, 0);
    201 	CSR_WRITE(l, WMREG_RDBAL, VTOPHYS(rxd));
    202 	CSR_WRITE(l, WMREG_RDLEN, sizeof(l->rxd));
    203 	CSR_WRITE(l, WMREG_RDH, 0);
    204 	CSR_WRITE(l, WMREG_RDT, 0);
    205 	CSR_WRITE(l, WMREG_RDTR, 0 | RDTR_FPD);
    206 	CSR_WRITE(l, WMREG_RADV, 128);
    207 	CSR_WRITE(l, WMREG_RXDCTL, RXDCTL_PTHRESH(0) |
    208 	    RXDCTL_HTHRESH(0) | RXDCTL_WTHRESH(1));
    209 
    210 	CSR_WRITE(l, WMREG_VET, 0);
    211 	CSR_WRITE(l, WMREG_IMC, ~0);
    212 	CSR_WRITE(l, WMREG_IMS, 0);
    213 
    214 	l->tctl = TCTL_EN | TCTL_PSP | TCTL_CT(15);
    215 	l->rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2;
    216 	CSR_WRITE(l, WMREG_TCTL, l->tctl);
    217 	CSR_WRITE(l, WMREG_RCTL, l->rctl);
    218 
    219 	return l;
    220 }
    221 
    222 int
    223 wm_send(void *dev, char *buf, unsigned len)
    224 {
    225 	struct local *l = dev;
    226 	volatile struct tdesc *txd;
    227 	unsigned loop;
    228 
    229 	wbinv(buf, len);
    230 	txd = &l->txd[l->tx];
    231 	txd->lo = htole32(VTOPHYS(buf));
    232 	txd->t2 = htole32(T2_EOP|T2_IFCS|T2_RS | (len & T2_FLMASK));
    233 	txd->t3 = 0;
    234 	wbinv(txd, sizeof(struct tdesc));
    235 	CSR_WRITE(l, WMREG_TDT, 0);
    236 	loop = 100;
    237 	do {
    238 		if ((le32toh(txd->t3) & T3_DD) != 0)
    239 			goto done;
    240 		DELAY(10);
    241 		inv(txd, sizeof(struct tdesc));
    242 	} while (--loop > 0);
    243 	printf("xmit failed\n");
    244 	return -1;
    245   done:
    246 	l->tx ^= 1;
    247 	return len;
    248 }
    249 
    250 int
    251 wm_recv(void *dev, char *buf, unsigned maxlen, unsigned timo)
    252 {
    253 	struct local *l = dev;
    254 	volatile struct rdesc *rxd;
    255 	unsigned bound, rxstat, len;
    256 	uint8_t *ptr;
    257 
    258 	bound = 1000 * timo;
    259 printf("recving with %u sec. timeout\n", timo);
    260   again:
    261 	rxd = &l->rxd[l->rx];
    262 	do {
    263 		inv(rxd, sizeof(struct rdesc));
    264 		rxstat = le32toh(rxd->r3);
    265 		if ((rxstat & R3_DD) != 0)
    266 			goto gotone;
    267 		DELAY(1000);	/* 1 milli second */
    268 	} while (--bound > 0);
    269 	errno = 0;
    270 	return -1;
    271   gotone:
    272 	/* expect this has R3_EOP mark */
    273 	if (rxstat & (R3_CE|R3_SE|R3_SEQ|R3_CXE|R3_RXE)) {
    274 		rxd->r2 = 0;
    275 		rxd->r3 = 0;
    276 		wbinv(rxd, sizeof(struct rdesc));
    277 		CSR_WRITE(l, WMREG_RDT, l->rx);
    278 		l->rx ^= 1;
    279 		goto again;
    280 	}
    281 	len = (rxstat & R2_FLMASK) - 4 /* HASFCS */;
    282 	if (len > maxlen)
    283 		len = maxlen;
    284 	ptr = l->rxstore[l->rx];
    285 	inv(ptr, len);
    286 	memcpy(buf, ptr, len);
    287 	rxd->r2 = 0;
    288 	rxd->r3 = 0;
    289 	wbinv(rxd, sizeof(struct rdesc));
    290 	CSR_WRITE(l, WMREG_RDT, l->rx);
    291 	l->rx ^= 1;
    292 	return len;
    293 }
    294 
    295 /*
    296  * bare SEEPROM access with bitbang'ing
    297  */
    298 #define R110	6		/* SEEPROM read op */
    299 #define CS  	(1U << 0)	/* hold chip select */
    300 #define CLK	(1U << 1)	/* clk bit */
    301 #define D1	(1U << 2)	/* bit existence */
    302 #define VV 	(1U << 3)	/* taken 0/1 from SEEPROM */
    303 
    304 static int
    305 read_srom(struct local *l, int off)
    306 {
    307 	unsigned data, v, i;
    308 
    309 	data = off & 0xff;		/* A5/A7-A0 */
    310 	data |= R110 << l->sromsft;	/* 110 for READ */
    311 
    312 	v = CSR_READ(l, WMREG_EECD) & ~(EECD_SK | EECD_DI);
    313 	CSR_WRITE(l, WMREG_EECD, v);
    314 	v |= EECD_CS;			/* hold CS */
    315 	CSR_WRITE(l, WMREG_EECD, v);
    316 	DELAY(2);
    317 
    318 	/* instruct R110 op. at off in MSB first order */
    319 	for (i = (1 << (l->sromsft + 2)); i != 0; i >>= 1) {
    320 		if (data & i)
    321 			v |= EECD_DI;
    322 		else
    323 			v &= ~EECD_DI;
    324 		CSR_WRITE(l, WMREG_EECD, v);
    325 		DELAY(2);
    326 		CSR_WRITE(l, WMREG_EECD, v | EECD_SK);
    327 		DELAY(2);
    328 		CSR_WRITE(l, WMREG_EECD, v);
    329 		DELAY(2);
    330 	}
    331 	v &= ~EECD_DI;
    332 
    333 	/* read 16bit quantity in MSB first order */
    334 	data = 0;
    335 	for (i = 0; i < 16; i++) {
    336 		CSR_WRITE(l, WMREG_EECD, v | EECD_SK);
    337 		DELAY(2);
    338 		data = (data << 1) | !!(CSR_READ(l, WMREG_EECD) & EECD_DO);
    339 		CSR_WRITE(l, WMREG_EECD, v);
    340 		DELAY(2);
    341 	}
    342 	/* turn off chip select */
    343 	v = CSR_READ(l, WMREG_EECD) & ~EECD_CS;
    344 	CSR_WRITE(l, WMREG_EECD, v);
    345 	DELAY(2);
    346 
    347 	return data;
    348 }
    349 
    350 #define MREG(v)		((v)<< 16)
    351 #define MPHY(v)		((v)<< 21)
    352 
    353 unsigned
    354 mii_read(struct local *l, int phy, int reg)
    355 {
    356 	unsigned data;
    357 
    358 	data = (2U << 26) | MPHY(phy) | MREG(reg);
    359 	CSR_WRITE(l, WMREG_MDIC, data);
    360 	do {
    361 		data = CSR_READ(l, WMREG_MDIC);
    362 	} while ((data & (1U << 28)) == 0);
    363 	return data & 0xffff;
    364 }
    365 
    366 void
    367 mii_write(struct local *l, int phy, int reg, int val)
    368 {
    369 	unsigned data;
    370 
    371 	data = (1U << 26) | MPHY(phy) | MREG(reg) | (val & 0xffff);
    372 	CSR_WRITE(l, WMREG_MDIC, data);
    373 	do {
    374 		data = CSR_READ(l, WMREG_MDIC);
    375 	} while ((data & (1U << 28)) == 0);
    376 }
    377 
    378 #define MII_BMCR	0x00	/* Basic mode control register (rw) */
    379 #define  BMCR_RESET	0x8000	/* reset */
    380 #define  BMCR_AUTOEN	0x1000	/* autonegotiation enable */
    381 #define  BMCR_ISO	0x0400	/* isolate */
    382 #define  BMCR_STARTNEG	0x0200	/* restart autonegotiation */
    383 #define MII_BMSR	0x01	/* Basic mode status register (ro) */
    384 #define  BMSR_ACOMP	0x0020	/* Autonegotiation complete */
    385 #define  BMSR_LINK	0x0004	/* Link status */
    386 #define MII_ANAR	0x04	/* Autonegotiation advertisement (rw) */
    387 #define  ANAR_FC	0x0400	/* local device supports PAUSE */
    388 #define  ANAR_TX_FD	0x0100	/* local device supports 100bTx FD */
    389 #define  ANAR_TX	0x0080	/* local device supports 100bTx */
    390 #define  ANAR_10_FD	0x0040	/* local device supports 10bT FD */
    391 #define  ANAR_10	0x0020	/* local device supports 10bT */
    392 #define  ANAR_CSMA	0x0001	/* protocol selector CSMA/CD */
    393 #define MII_ANLPAR	0x05	/* Autonegotiation lnk partner abilities (rw) */
    394 #define MII_GTCR	0x09	/* 1000baseT control */
    395 #define  GANA_1000TFDX	0x0200	/* advertise 1000baseT FDX */
    396 #define  GANA_1000THDX	0x0100	/* advertise 1000baseT HDX */
    397 #define MII_GTSR	0x0a	/* 1000baseT status */
    398 #define  GLPA_1000TFDX	0x0800	/* link partner 1000baseT FDX capable */
    399 #define  GLPA_1000THDX	0x0400	/* link partner 1000baseT HDX capable */
    400 #define  GLPA_ASM_DIR	0x0200	/* link partner asym. pause dir. capable */
    401 
    402 static void
    403 mii_initphy(struct local *l)
    404 {
    405 	int phy, ctl, sts, bound;
    406 
    407 	for (phy = 0; phy < 32; phy++) {
    408 		ctl = mii_read(l, phy, MII_BMCR);
    409 		sts = mii_read(l, phy, MII_BMSR);
    410 		if (ctl != 0xffff && sts != 0xffff)
    411 			goto found;
    412 	}
    413 	printf("MII: no PHY found\n");
    414 	return;
    415   found:
    416 	ctl = mii_read(l, phy, MII_BMCR);
    417 	mii_write(l, phy, MII_BMCR, ctl | BMCR_RESET);
    418 	bound = 100;
    419 	do {
    420 		DELAY(10);
    421 		ctl = mii_read(l, phy, MII_BMCR);
    422 		if (ctl == 0xffff) {
    423 			printf("MII: PHY %d has died after reset\n", phy);
    424 			return;
    425 		}
    426 	} while (bound-- > 0 && (ctl & BMCR_RESET));
    427 	if (bound == 0) {
    428 		printf("PHY %d reset failed\n", phy);
    429 	}
    430 	ctl &= ~BMCR_ISO;
    431 	mii_write(l, phy, MII_BMCR, ctl);
    432 	sts = mii_read(l, phy, MII_BMSR) |
    433 	    mii_read(l, phy, MII_BMSR); /* read twice */
    434 	l->phy = phy;
    435 	l->bmsr = sts;
    436 }
    437 
    438 void
    439 mii_dealan(struct local *l, unsigned timo)
    440 {
    441 	unsigned anar, gtcr, bound;
    442 
    443 	anar = ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA;
    444 	anar |= ANAR_FC;
    445 	gtcr = GANA_1000TFDX | GANA_1000THDX;
    446 	mii_write(l, l->phy, MII_ANAR, anar);
    447 	mii_write(l, l->phy, MII_GTCR, gtcr);
    448 	mii_write(l, l->phy, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG);
    449 	l->anlpar = 0;
    450 	bound = getsecs() + timo;
    451 	do {
    452 		l->bmsr = mii_read(l, l->phy, MII_BMSR) |
    453 		   mii_read(l, l->phy, MII_BMSR); /* read twice */
    454 		if ((l->bmsr & BMSR_LINK) && (l->bmsr & BMSR_ACOMP)) {
    455 			l->anlpar = mii_read(l, l->phy, MII_ANLPAR);
    456 			break;
    457 		}
    458 		DELAY(10 * 1000);
    459 	} while (getsecs() < bound);
    460 	return;
    461 }
    462