| /src/external/gpl2/dtc/dist/tests/ |
| integer-expressions.c | 26 #define TE(expr) { #expr, (expr) }
27 TE(0xdeadbeef),
28 TE(-0x21524111),
29 TE(1+1),
30 TE(2*3),
31 TE(4/2),
32 TE(10/3),
33 TE(19%4),
34 TE(1 << 13),
35 TE(0x1000 >> 4)
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/bfin/ |
| dv-bfin_emac.h | 28 #define TE (1 << 16)
|
| /src/external/gpl3/gdb/dist/sim/bfin/ |
| dv-bfin_emac.h | 28 #define TE (1 << 16)
|
| /src/external/apache2/llvm/dist/clang/lib/StaticAnalyzer/Core/ |
| SValBuilder.cpp | 328 const auto *TE = cast<TypeTraitExpr>(E);
329 return makeTruthVal(TE->getValue(), TE->getType());
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| MachineTraceMetrics.h | 256 Ensemble &TE;
259 unsigned getBlockNum() const { return &TBI - &TE.BlockInfo[0]; }
262 explicit Trace(Ensemble &te, TraceBlockInfo &tbi) : TE(te), TBI(tbi) {}
299 return TE.Cycles.lookup(&MI);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/Utils/ |
| ARMBaseInfo.h | 108 TE = 0b1100,
|
| /src/external/apache2/llvm/dist/clang/lib/Sema/ |
| SemaExprMember.cpp | 644 TypoExpr *&TE) {
701 TE = SemaRef.CorrectTypoDelayed(
717 [=](Sema &SemaRef, TypoExpr *TE, TypoCorrection TC) mutable {
761 TypoExpr *TE = nullptr;
766 SS, TemplateArgs != nullptr, TemplateKWLoc, TE))
768 if (TE)
769 return TE;
1295 TypoExpr *TE = nullptr;
1297 HasTemplateArgs, TemplateKWLoc, TE))
1304 return ExprResult(TE);
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/ADT/ |
| ImmutableSet.h | 449 typename TreeTy::iterator& TE) {
452 if (TI == TE || !I->isElementEqual(&*TI))
629 typename TreeTy::iterator TI = T->begin(), TE = T->end();
630 if (!compareTreeWithSection(TNew, TI, TE))
632 if (TI != TE)
|
| /src/external/apache2/llvm/dist/clang/lib/AST/ |
| ItaniumMangle.cpp | 3814 // ::= Te <name> # dependent elaborated type specifier using
3829 Out << "Te";
4620 const CXXThrowExpr *TE = cast<CXXThrowExpr>(E);
4623 if (TE->getSubExpr()) {
4625 mangleExpression(TE->getSubExpr());
4636 // ::= te <expression> # typeid (expression)
4641 Out << "te";
|
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/Vectorize/ |
| SLPVectorizer.cpp | 1585 isGatherShuffledEntry(const TreeEntry *TE, SmallVectorImpl<int> &Mask,
1878 BundleMember->TE = Last;
2018 TE = nullptr;
2128 TreeEntry *TE = nullptr;
2228 if (TreeEntry *TE = BundleMember->TE) {
2238 auto *In = TE->getMainOp();
2242 In->getNumOperands() == TE->getNumOperands()) &&
2246 for (unsigned OpIdx = 0, NumOperands = TE->getNumOperands();
2248 if (auto *I = dyn_cast<Instruction>(TE->getOperand(OpIdx)[Lane])
[all...] |
| /src/external/gpl3/binutils/dist/opcodes/ |
| ppc-opc.c | 3709 /* The SIMM field in a VX form instruction, and TE in Z form. */
3711 #define TE SIMM
9263 {"dquai", ZRC(59,67,0), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}},
9264 {"dquai.", ZRC(59,67,1), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}},
9783 {"dquaiq", ZRC(63,67,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}},
9784 {"dquaiq.", ZRC(63,67,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}},
|
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| ppc-opc.c | 3709 /* The SIMM field in a VX form instruction, and TE in Z form. */
3711 #define TE SIMM
9198 {"dquai", ZRC(59,67,0), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}},
9199 {"dquai.", ZRC(59,67,1), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}},
9718 {"dquaiq", ZRC(63,67,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}},
9719 {"dquaiq.", ZRC(63,67,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}},
|
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| ppc-opc.c | 3631 /* The SIMM field in a VX form instruction, and TE in Z form. */
3633 #define TE SIMM
9079 {"dquai", ZRC(59,67,0), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}},
9080 {"dquai.", ZRC(59,67,1), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}},
9578 {"dquaiq", ZRC(63,67,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}},
9579 {"dquaiq.", ZRC(63,67,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}},
|
| /src/external/gpl3/gdb/dist/opcodes/ |
| ppc-opc.c | 3709 /* The SIMM field in a VX form instruction, and TE in Z form. */
3711 #define TE SIMM
9220 {"dquai", ZRC(59,67,0), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}},
9221 {"dquai.", ZRC(59,67,1), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}},
9740 {"dquaiq", ZRC(63,67,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}},
9741 {"dquaiq.", ZRC(63,67,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}},
|
