1 /* $NetBSD: tegra186-clock.h,v 1.1.1.2 2017/11/30 19:40:51 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 */ 4 /** @file */ 5 6 #ifndef _MACH_T186_CLK_T186_H 7 #define _MACH_T186_CLK_T186_H 8 9 /** 10 * @defgroup clock_ids Clock Identifiers 11 * @{ 12 * @defgroup extern_input external input clocks 13 * @{ 14 * @def TEGRA186_CLK_OSC 15 * @def TEGRA186_CLK_CLK_32K 16 * @def TEGRA186_CLK_DTV_INPUT 17 * @def TEGRA186_CLK_SOR0_PAD_CLKOUT 18 * @def TEGRA186_CLK_SOR1_PAD_CLKOUT 19 * @def TEGRA186_CLK_I2S1_SYNC_INPUT 20 * @def TEGRA186_CLK_I2S2_SYNC_INPUT 21 * @def TEGRA186_CLK_I2S3_SYNC_INPUT 22 * @def TEGRA186_CLK_I2S4_SYNC_INPUT 23 * @def TEGRA186_CLK_I2S5_SYNC_INPUT 24 * @def TEGRA186_CLK_I2S6_SYNC_INPUT 25 * @def TEGRA186_CLK_SPDIFIN_SYNC_INPUT 26 * @} 27 * 28 * @defgroup extern_output external output clocks 29 * @{ 30 * @def TEGRA186_CLK_EXTPERIPH1 31 * @def TEGRA186_CLK_EXTPERIPH2 32 * @def TEGRA186_CLK_EXTPERIPH3 33 * @def TEGRA186_CLK_EXTPERIPH4 34 * @} 35 * 36 * @defgroup display_clks display related clocks 37 * @{ 38 * @def TEGRA186_CLK_CEC 39 * @def TEGRA186_CLK_DSIC 40 * @def TEGRA186_CLK_DSIC_LP 41 * @def TEGRA186_CLK_DSID 42 * @def TEGRA186_CLK_DSID_LP 43 * @def TEGRA186_CLK_DPAUX1 44 * @def TEGRA186_CLK_DPAUX 45 * @def TEGRA186_CLK_HDA2HDMICODEC 46 * @def TEGRA186_CLK_NVDISPLAY_DISP 47 * @def TEGRA186_CLK_NVDISPLAY_DSC 48 * @def TEGRA186_CLK_NVDISPLAY_P0 49 * @def TEGRA186_CLK_NVDISPLAY_P1 50 * @def TEGRA186_CLK_NVDISPLAY_P2 51 * @def TEGRA186_CLK_NVDISPLAYHUB 52 * @def TEGRA186_CLK_SOR_SAFE 53 * @def TEGRA186_CLK_SOR0 54 * @def TEGRA186_CLK_SOR0_OUT 55 * @def TEGRA186_CLK_SOR1 56 * @def TEGRA186_CLK_SOR1_OUT 57 * @def TEGRA186_CLK_DSI 58 * @def TEGRA186_CLK_MIPI_CAL 59 * @def TEGRA186_CLK_DSIA_LP 60 * @def TEGRA186_CLK_DSIB 61 * @def TEGRA186_CLK_DSIB_LP 62 * @} 63 * 64 * @defgroup camera_clks camera related clocks 65 * @{ 66 * @def TEGRA186_CLK_NVCSI 67 * @def TEGRA186_CLK_NVCSILP 68 * @def TEGRA186_CLK_VI 69 * @} 70 * 71 * @defgroup audio_clks audio related clocks 72 * @{ 73 * @def TEGRA186_CLK_ACLK 74 * @def TEGRA186_CLK_ADSP 75 * @def TEGRA186_CLK_ADSPNEON 76 * @def TEGRA186_CLK_AHUB 77 * @def TEGRA186_CLK_APE 78 * @def TEGRA186_CLK_APB2APE 79 * @def TEGRA186_CLK_AUD_MCLK 80 * @def TEGRA186_CLK_DMIC1 81 * @def TEGRA186_CLK_DMIC2 82 * @def TEGRA186_CLK_DMIC3 83 * @def TEGRA186_CLK_DMIC4 84 * @def TEGRA186_CLK_DSPK1 85 * @def TEGRA186_CLK_DSPK2 86 * @def TEGRA186_CLK_HDA 87 * @def TEGRA186_CLK_HDA2CODEC_2X 88 * @def TEGRA186_CLK_I2S1 89 * @def TEGRA186_CLK_I2S2 90 * @def TEGRA186_CLK_I2S3 91 * @def TEGRA186_CLK_I2S4 92 * @def TEGRA186_CLK_I2S5 93 * @def TEGRA186_CLK_I2S6 94 * @def TEGRA186_CLK_MAUD 95 * @def TEGRA186_CLK_PLL_A_OUT0 96 * @def TEGRA186_CLK_SPDIF_DOUBLER 97 * @def TEGRA186_CLK_SPDIF_IN 98 * @def TEGRA186_CLK_SPDIF_OUT 99 * @def TEGRA186_CLK_SYNC_DMIC1 100 * @def TEGRA186_CLK_SYNC_DMIC2 101 * @def TEGRA186_CLK_SYNC_DMIC3 102 * @def TEGRA186_CLK_SYNC_DMIC4 103 * @def TEGRA186_CLK_SYNC_DMIC5 104 * @def TEGRA186_CLK_SYNC_DSPK1 105 * @def TEGRA186_CLK_SYNC_DSPK2 106 * @def TEGRA186_CLK_SYNC_I2S1 107 * @def TEGRA186_CLK_SYNC_I2S2 108 * @def TEGRA186_CLK_SYNC_I2S3 109 * @def TEGRA186_CLK_SYNC_I2S4 110 * @def TEGRA186_CLK_SYNC_I2S5 111 * @def TEGRA186_CLK_SYNC_I2S6 112 * @def TEGRA186_CLK_SYNC_SPDIF 113 * @} 114 * 115 * @defgroup uart_clks UART clocks 116 * @{ 117 * @def TEGRA186_CLK_AON_UART_FST_MIPI_CAL 118 * @def TEGRA186_CLK_UARTA 119 * @def TEGRA186_CLK_UARTB 120 * @def TEGRA186_CLK_UARTC 121 * @def TEGRA186_CLK_UARTD 122 * @def TEGRA186_CLK_UARTE 123 * @def TEGRA186_CLK_UARTF 124 * @def TEGRA186_CLK_UARTG 125 * @def TEGRA186_CLK_UART_FST_MIPI_CAL 126 * @} 127 * 128 * @defgroup i2c_clks I2C clocks 129 * @{ 130 * @def TEGRA186_CLK_AON_I2C_SLOW 131 * @def TEGRA186_CLK_I2C1 132 * @def TEGRA186_CLK_I2C2 133 * @def TEGRA186_CLK_I2C3 134 * @def TEGRA186_CLK_I2C4 135 * @def TEGRA186_CLK_I2C5 136 * @def TEGRA186_CLK_I2C6 137 * @def TEGRA186_CLK_I2C8 138 * @def TEGRA186_CLK_I2C9 139 * @def TEGRA186_CLK_I2C1 140 * @def TEGRA186_CLK_I2C12 141 * @def TEGRA186_CLK_I2C13 142 * @def TEGRA186_CLK_I2C14 143 * @def TEGRA186_CLK_I2C_SLOW 144 * @def TEGRA186_CLK_VI_I2C 145 * @} 146 * 147 * @defgroup spi_clks SPI clocks 148 * @{ 149 * @def TEGRA186_CLK_SPI1 150 * @def TEGRA186_CLK_SPI2 151 * @def TEGRA186_CLK_SPI3 152 * @def TEGRA186_CLK_SPI4 153 * @} 154 * 155 * @defgroup storage storage related clocks 156 * @{ 157 * @def TEGRA186_CLK_SATA 158 * @def TEGRA186_CLK_SATA_OOB 159 * @def TEGRA186_CLK_SATA_IOBIST 160 * @def TEGRA186_CLK_SDMMC_LEGACY_TM 161 * @def TEGRA186_CLK_SDMMC1 162 * @def TEGRA186_CLK_SDMMC2 163 * @def TEGRA186_CLK_SDMMC3 164 * @def TEGRA186_CLK_SDMMC4 165 * @def TEGRA186_CLK_QSPI 166 * @def TEGRA186_CLK_QSPI_OUT 167 * @def TEGRA186_CLK_UFSDEV_REF 168 * @def TEGRA186_CLK_UFSHC 169 * @} 170 * 171 * @defgroup pwm_clks PWM clocks 172 * @{ 173 * @def TEGRA186_CLK_PWM1 174 * @def TEGRA186_CLK_PWM2 175 * @def TEGRA186_CLK_PWM3 176 * @def TEGRA186_CLK_PWM4 177 * @def TEGRA186_CLK_PWM5 178 * @def TEGRA186_CLK_PWM6 179 * @def TEGRA186_CLK_PWM7 180 * @def TEGRA186_CLK_PWM8 181 * @} 182 * 183 * @defgroup plls PLLs and related clocks 184 * @{ 185 * @def TEGRA186_CLK_PLLREFE_OUT_GATED 186 * @def TEGRA186_CLK_PLLREFE_OUT1 187 * @def TEGRA186_CLK_PLLD_OUT1 188 * @def TEGRA186_CLK_PLLP_OUT0 189 * @def TEGRA186_CLK_PLLP_OUT5 190 * @def TEGRA186_CLK_PLLA 191 * @def TEGRA186_CLK_PLLE_PWRSEQ 192 * @def TEGRA186_CLK_PLLA_OUT1 193 * @def TEGRA186_CLK_PLLREFE_REF 194 * @def TEGRA186_CLK_UPHY_PLL0_PWRSEQ 195 * @def TEGRA186_CLK_UPHY_PLL1_PWRSEQ 196 * @def TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH 197 * @def TEGRA186_CLK_PLLREFE_PEX 198 * @def TEGRA186_CLK_PLLREFE_IDDQ 199 * @def TEGRA186_CLK_PLLC_OUT_AON 200 * @def TEGRA186_CLK_PLLC_OUT_ISP 201 * @def TEGRA186_CLK_PLLC_OUT_VE 202 * @def TEGRA186_CLK_PLLC4_OUT 203 * @def TEGRA186_CLK_PLLREFE_OUT 204 * @def TEGRA186_CLK_PLLREFE_PLL_REF 205 * @def TEGRA186_CLK_PLLE 206 * @def TEGRA186_CLK_PLLC 207 * @def TEGRA186_CLK_PLLP 208 * @def TEGRA186_CLK_PLLD 209 * @def TEGRA186_CLK_PLLD2 210 * @def TEGRA186_CLK_PLLREFE_VCO 211 * @def TEGRA186_CLK_PLLC2 212 * @def TEGRA186_CLK_PLLC3 213 * @def TEGRA186_CLK_PLLDP 214 * @def TEGRA186_CLK_PLLC4_VCO 215 * @def TEGRA186_CLK_PLLA1 216 * @def TEGRA186_CLK_PLLNVCSI 217 * @def TEGRA186_CLK_PLLDISPHUB 218 * @def TEGRA186_CLK_PLLD3 219 * @def TEGRA186_CLK_PLLBPMPCAM 220 * @def TEGRA186_CLK_PLLAON 221 * @def TEGRA186_CLK_PLLU 222 * @def TEGRA186_CLK_PLLC4_VCO_DIV2 223 * @def TEGRA186_CLK_PLL_REF 224 * @def TEGRA186_CLK_PLLREFE_OUT1_DIV5 225 * @def TEGRA186_CLK_UTMIP_PLL_PWRSEQ 226 * @def TEGRA186_CLK_PLL_U_48M 227 * @def TEGRA186_CLK_PLL_U_480M 228 * @def TEGRA186_CLK_PLLC4_OUT0 229 * @def TEGRA186_CLK_PLLC4_OUT1 230 * @def TEGRA186_CLK_PLLC4_OUT2 231 * @def TEGRA186_CLK_PLLC4_OUT_MUX 232 * @def TEGRA186_CLK_DFLLDISP_DIV 233 * @def TEGRA186_CLK_PLLDISPHUB_DIV 234 * @def TEGRA186_CLK_PLLP_DIV8 235 * @} 236 * 237 * @defgroup nafll_clks NAFLL clock sources 238 * @{ 239 * @def TEGRA186_CLK_NAFLL_AXI_CBB 240 * @def TEGRA186_CLK_NAFLL_BCPU 241 * @def TEGRA186_CLK_NAFLL_BPMP 242 * @def TEGRA186_CLK_NAFLL_DISP 243 * @def TEGRA186_CLK_NAFLL_GPU 244 * @def TEGRA186_CLK_NAFLL_ISP 245 * @def TEGRA186_CLK_NAFLL_MCPU 246 * @def TEGRA186_CLK_NAFLL_NVDEC 247 * @def TEGRA186_CLK_NAFLL_NVENC 248 * @def TEGRA186_CLK_NAFLL_NVJPG 249 * @def TEGRA186_CLK_NAFLL_SCE 250 * @def TEGRA186_CLK_NAFLL_SE 251 * @def TEGRA186_CLK_NAFLL_TSEC 252 * @def TEGRA186_CLK_NAFLL_TSECB 253 * @def TEGRA186_CLK_NAFLL_VI 254 * @def TEGRA186_CLK_NAFLL_VIC 255 * @} 256 * 257 * @defgroup mphy MPHY related clocks 258 * @{ 259 * @def TEGRA186_CLK_MPHY_L0_RX_SYMB 260 * @def TEGRA186_CLK_MPHY_L0_RX_LS_BIT 261 * @def TEGRA186_CLK_MPHY_L0_TX_SYMB 262 * @def TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT 263 * @def TEGRA186_CLK_MPHY_L0_RX_ANA 264 * @def TEGRA186_CLK_MPHY_L1_RX_ANA 265 * @def TEGRA186_CLK_MPHY_IOBIST 266 * @def TEGRA186_CLK_MPHY_TX_1MHZ_REF 267 * @def TEGRA186_CLK_MPHY_CORE_PLL_FIXED 268 * @} 269 * 270 * @defgroup eavb EAVB related clocks 271 * @{ 272 * @def TEGRA186_CLK_EQOS_AXI 273 * @def TEGRA186_CLK_EQOS_PTP_REF 274 * @def TEGRA186_CLK_EQOS_RX 275 * @def TEGRA186_CLK_EQOS_RX_INPUT 276 * @def TEGRA186_CLK_EQOS_TX 277 * @} 278 * 279 * @defgroup usb USB related clocks 280 * @{ 281 * @def TEGRA186_CLK_PEX_USB_PAD0_MGMT 282 * @def TEGRA186_CLK_PEX_USB_PAD1_MGMT 283 * @def TEGRA186_CLK_HSIC_TRK 284 * @def TEGRA186_CLK_USB2_TRK 285 * @def TEGRA186_CLK_USB2_HSIC_TRK 286 * @def TEGRA186_CLK_XUSB_CORE_SS 287 * @def TEGRA186_CLK_XUSB_CORE_DEV 288 * @def TEGRA186_CLK_XUSB_FALCON 289 * @def TEGRA186_CLK_XUSB_FS 290 * @def TEGRA186_CLK_XUSB 291 * @def TEGRA186_CLK_XUSB_DEV 292 * @def TEGRA186_CLK_XUSB_HOST 293 * @def TEGRA186_CLK_XUSB_SS 294 * @} 295 * 296 * @defgroup bigblock compute block related clocks 297 * @{ 298 * @def TEGRA186_CLK_GPCCLK 299 * @def TEGRA186_CLK_GPC2CLK 300 * @def TEGRA186_CLK_GPU 301 * @def TEGRA186_CLK_HOST1X 302 * @def TEGRA186_CLK_ISP 303 * @def TEGRA186_CLK_NVDEC 304 * @def TEGRA186_CLK_NVENC 305 * @def TEGRA186_CLK_NVJPG 306 * @def TEGRA186_CLK_SE 307 * @def TEGRA186_CLK_TSEC 308 * @def TEGRA186_CLK_TSECB 309 * @def TEGRA186_CLK_VIC 310 * @} 311 * 312 * @defgroup can CAN bus related clocks 313 * @{ 314 * @def TEGRA186_CLK_CAN1 315 * @def TEGRA186_CLK_CAN1_HOST 316 * @def TEGRA186_CLK_CAN2 317 * @def TEGRA186_CLK_CAN2_HOST 318 * @} 319 * 320 * @defgroup system basic system clocks 321 * @{ 322 * @def TEGRA186_CLK_ACTMON 323 * @def TEGRA186_CLK_AON_APB 324 * @def TEGRA186_CLK_AON_CPU_NIC 325 * @def TEGRA186_CLK_AON_NIC 326 * @def TEGRA186_CLK_AXI_CBB 327 * @def TEGRA186_CLK_BPMP_APB 328 * @def TEGRA186_CLK_BPMP_CPU_NIC 329 * @def TEGRA186_CLK_BPMP_NIC_RATE 330 * @def TEGRA186_CLK_CLK_M 331 * @def TEGRA186_CLK_EMC 332 * @def TEGRA186_CLK_MSS_ENCRYPT 333 * @def TEGRA186_CLK_SCE_APB 334 * @def TEGRA186_CLK_SCE_CPU_NIC 335 * @def TEGRA186_CLK_SCE_NIC 336 * @def TEGRA186_CLK_TSC 337 * @} 338 * 339 * @defgroup pcie_clks PCIe related clocks 340 * @{ 341 * @def TEGRA186_CLK_AFI 342 * @def TEGRA186_CLK_PCIE 343 * @def TEGRA186_CLK_PCIE2_IOBIST 344 * @def TEGRA186_CLK_PCIERX0 345 * @def TEGRA186_CLK_PCIERX1 346 * @def TEGRA186_CLK_PCIERX2 347 * @def TEGRA186_CLK_PCIERX3 348 * @def TEGRA186_CLK_PCIERX4 349 * @} 350 */ 351 352 /** @brief output of gate CLK_ENB_FUSE */ 353 #define TEGRA186_CLK_FUSE 0 354 /** 355 * @brief It's not what you think 356 * @details output of gate CLK_ENB_GPU. This output connects to the GPU 357 * pwrclk. @warning: This is almost certainly not the clock you think 358 * it is. If you're looking for the clock of the graphics engine, see 359 * TEGRA186_GPCCLK 360 */ 361 #define TEGRA186_CLK_GPU 1 362 /** @brief output of gate CLK_ENB_PCIE */ 363 #define TEGRA186_CLK_PCIE 3 364 /** @brief output of the divider IPFS_CLK_DIVISOR */ 365 #define TEGRA186_CLK_AFI 4 366 /** @brief output of gate CLK_ENB_PCIE2_IOBIST */ 367 #define TEGRA186_CLK_PCIE2_IOBIST 5 368 /** @brief output of gate CLK_ENB_PCIERX0*/ 369 #define TEGRA186_CLK_PCIERX0 6 370 /** @brief output of gate CLK_ENB_PCIERX1*/ 371 #define TEGRA186_CLK_PCIERX1 7 372 /** @brief output of gate CLK_ENB_PCIERX2*/ 373 #define TEGRA186_CLK_PCIERX2 8 374 /** @brief output of gate CLK_ENB_PCIERX3*/ 375 #define TEGRA186_CLK_PCIERX3 9 376 /** @brief output of gate CLK_ENB_PCIERX4*/ 377 #define TEGRA186_CLK_PCIERX4 10 378 /** @brief output branch of PLL_C for ISP, controlled by gate CLK_ENB_PLLC_OUT_ISP */ 379 #define TEGRA186_CLK_PLLC_OUT_ISP 11 380 /** @brief output branch of PLL_C for VI, controlled by gate CLK_ENB_PLLC_OUT_VE */ 381 #define TEGRA186_CLK_PLLC_OUT_VE 12 382 /** @brief output branch of PLL_C for AON domain, controlled by gate CLK_ENB_PLLC_OUT_AON */ 383 #define TEGRA186_CLK_PLLC_OUT_AON 13 384 /** @brief output of gate CLK_ENB_SOR_SAFE */ 385 #define TEGRA186_CLK_SOR_SAFE 39 386 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */ 387 #define TEGRA186_CLK_I2S2 42 388 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */ 389 #define TEGRA186_CLK_I2S3 43 390 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDF_IN */ 391 #define TEGRA186_CLK_SPDIF_IN 44 392 /** @brief output of gate CLK_ENB_SPDIF_DOUBLER */ 393 #define TEGRA186_CLK_SPDIF_DOUBLER 45 394 /** @clkdesc{spi_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_SPI3} */ 395 #define TEGRA186_CLK_SPI3 46 396 /** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1} */ 397 #define TEGRA186_CLK_I2C1 47 398 /** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5} */ 399 #define TEGRA186_CLK_I2C5 48 400 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI1 */ 401 #define TEGRA186_CLK_SPI1 49 402 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ISP */ 403 #define TEGRA186_CLK_ISP 50 404 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI */ 405 #define TEGRA186_CLK_VI 51 406 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 */ 407 #define TEGRA186_CLK_SDMMC1 52 408 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2 */ 409 #define TEGRA186_CLK_SDMMC2 53 410 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */ 411 #define TEGRA186_CLK_SDMMC4 54 412 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */ 413 #define TEGRA186_CLK_UARTA 55 414 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTB */ 415 #define TEGRA186_CLK_UARTB 56 416 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */ 417 #define TEGRA186_CLK_HOST1X 57 418 /** 419 * @brief controls the EMC clock frequency. 420 * @details Doing a clk_set_rate on this clock will select the 421 * appropriate clock source, program the source rate and execute a 422 * specific sequence to switch to the new clock source for both memory 423 * controllers. This can be used to control the balance between memory 424 * throughput and memory controller power. 425 */ 426 #define TEGRA186_CLK_EMC 58 427 /* @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4 */ 428 #define TEGRA186_CLK_EXTPERIPH4 73 429 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI4 */ 430 #define TEGRA186_CLK_SPI4 74 431 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */ 432 #define TEGRA186_CLK_I2C3 75 433 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3 */ 434 #define TEGRA186_CLK_SDMMC3 76 435 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTD */ 436 #define TEGRA186_CLK_UARTD 77 437 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */ 438 #define TEGRA186_CLK_I2S1 79 439 /** output of gate CLK_ENB_DTV */ 440 #define TEGRA186_CLK_DTV 80 441 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSEC */ 442 #define TEGRA186_CLK_TSEC 81 443 /** @brief output of gate CLK_ENB_DP2 */ 444 #define TEGRA186_CLK_DP2 82 445 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */ 446 #define TEGRA186_CLK_I2S4 84 447 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */ 448 #define TEGRA186_CLK_I2S5 85 449 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */ 450 #define TEGRA186_CLK_I2C4 86 451 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */ 452 #define TEGRA186_CLK_AHUB 87 453 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X */ 454 #define TEGRA186_CLK_HDA2CODEC_2X 88 455 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1 */ 456 #define TEGRA186_CLK_EXTPERIPH1 89 457 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2 */ 458 #define TEGRA186_CLK_EXTPERIPH2 90 459 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3 */ 460 #define TEGRA186_CLK_EXTPERIPH3 91 461 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW */ 462 #define TEGRA186_CLK_I2C_SLOW 92 463 /** @brief output of the SOR1_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */ 464 #define TEGRA186_CLK_SOR1 93 465 /** @brief output of gate CLK_ENB_CEC */ 466 #define TEGRA186_CLK_CEC 94 467 /** @brief output of gate CLK_ENB_DPAUX1 */ 468 #define TEGRA186_CLK_DPAUX1 95 469 /** @brief output of gate CLK_ENB_DPAUX */ 470 #define TEGRA186_CLK_DPAUX 96 471 /** @brief output of the SOR0_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */ 472 #define TEGRA186_CLK_SOR0 97 473 /** @brief output of gate CLK_ENB_HDA2HDMICODEC */ 474 #define TEGRA186_CLK_HDA2HDMICODEC 98 475 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SATA */ 476 #define TEGRA186_CLK_SATA 99 477 /** @brief output of gate CLK_ENB_SATA_OOB */ 478 #define TEGRA186_CLK_SATA_OOB 100 479 /** @brief output of gate CLK_ENB_SATA_IOBIST */ 480 #define TEGRA186_CLK_SATA_IOBIST 101 481 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA */ 482 #define TEGRA186_CLK_HDA 102 483 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SE */ 484 #define TEGRA186_CLK_SE 103 485 /** @brief output of gate CLK_ENB_APB2APE */ 486 #define TEGRA186_CLK_APB2APE 104 487 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */ 488 #define TEGRA186_CLK_APE 105 489 /** @brief output of gate CLK_ENB_IQC1 */ 490 #define TEGRA186_CLK_IQC1 106 491 /** @brief output of gate CLK_ENB_IQC2 */ 492 #define TEGRA186_CLK_IQC2 107 493 /** divide by 2 version of TEGRA186_CLK_PLLREFE_VCO */ 494 #define TEGRA186_CLK_PLLREFE_OUT 108 495 /** @brief output of gate CLK_ENB_PLLREFE_PLL_REF */ 496 #define TEGRA186_CLK_PLLREFE_PLL_REF 109 497 /** @brief output of gate CLK_ENB_PLLC4_OUT */ 498 #define TEGRA186_CLK_PLLC4_OUT 110 499 /** @brief output of mux xusb_core_clk_switch on page 67 of T186_Clocks_IAS.doc */ 500 #define TEGRA186_CLK_XUSB 111 501 /** controls xusb_dev_ce signal on page 66 and 67 of T186_Clocks_IAS.doc */ 502 #define TEGRA186_CLK_XUSB_DEV 112 503 /** controls xusb_host_ce signal on page 67 of T186_Clocks_IAS.doc */ 504 #define TEGRA186_CLK_XUSB_HOST 113 505 /** controls xusb_ss_ce signal on page 67 of T186_Clocks_IAS.doc */ 506 #define TEGRA186_CLK_XUSB_SS 114 507 /** @brief output of gate CLK_ENB_DSI */ 508 #define TEGRA186_CLK_DSI 115 509 /** @brief output of gate CLK_ENB_MIPI_CAL */ 510 #define TEGRA186_CLK_MIPI_CAL 116 511 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP */ 512 #define TEGRA186_CLK_DSIA_LP 117 513 /** @brief output of gate CLK_ENB_DSIB */ 514 #define TEGRA186_CLK_DSIB 118 515 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP */ 516 #define TEGRA186_CLK_DSIB_LP 119 517 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */ 518 #define TEGRA186_CLK_DMIC1 122 519 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */ 520 #define TEGRA186_CLK_DMIC2 123 521 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */ 522 #define TEGRA186_CLK_AUD_MCLK 124 523 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */ 524 #define TEGRA186_CLK_I2C6 125 525 /**output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL */ 526 #define TEGRA186_CLK_UART_FST_MIPI_CAL 126 527 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VIC */ 528 #define TEGRA186_CLK_VIC 127 529 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM */ 530 #define TEGRA186_CLK_SDMMC_LEGACY_TM 128 531 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC */ 532 #define TEGRA186_CLK_NVDEC 129 533 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG */ 534 #define TEGRA186_CLK_NVJPG 130 535 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVENC */ 536 #define TEGRA186_CLK_NVENC 131 537 /** @brief output of the QSPI_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */ 538 #define TEGRA186_CLK_QSPI 132 539 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C */ 540 #define TEGRA186_CLK_VI_I2C 133 541 /** @brief output of gate CLK_ENB_HSIC_TRK */ 542 #define TEGRA186_CLK_HSIC_TRK 134 543 /** @brief output of gate CLK_ENB_USB2_TRK */ 544 #define TEGRA186_CLK_USB2_TRK 135 545 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MAUD */ 546 #define TEGRA186_CLK_MAUD 136 547 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSECB */ 548 #define TEGRA186_CLK_TSECB 137 549 /** @brief output of gate CLK_ENB_ADSP */ 550 #define TEGRA186_CLK_ADSP 138 551 /** @brief output of gate CLK_ENB_ADSPNEON */ 552 #define TEGRA186_CLK_ADSPNEON 139 553 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB */ 554 #define TEGRA186_CLK_MPHY_L0_RX_SYMB 140 555 /** @brief output of gate CLK_ENB_MPHY_L0_RX_LS_BIT */ 556 #define TEGRA186_CLK_MPHY_L0_RX_LS_BIT 141 557 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB */ 558 #define TEGRA186_CLK_MPHY_L0_TX_SYMB 142 559 /** @brief output of gate CLK_ENB_MPHY_L0_TX_LS_3XBIT */ 560 #define TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT 143 561 /** @brief output of gate CLK_ENB_MPHY_L0_RX_ANA */ 562 #define TEGRA186_CLK_MPHY_L0_RX_ANA 144 563 /** @brief output of gate CLK_ENB_MPHY_L1_RX_ANA */ 564 #define TEGRA186_CLK_MPHY_L1_RX_ANA 145 565 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST */ 566 #define TEGRA186_CLK_MPHY_IOBIST 146 567 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF */ 568 #define TEGRA186_CLK_MPHY_TX_1MHZ_REF 147 569 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED */ 570 #define TEGRA186_CLK_MPHY_CORE_PLL_FIXED 148 571 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB */ 572 #define TEGRA186_CLK_AXI_CBB 149 573 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */ 574 #define TEGRA186_CLK_DMIC3 150 575 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */ 576 #define TEGRA186_CLK_DMIC4 151 577 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */ 578 #define TEGRA186_CLK_DSPK1 152 579 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */ 580 #define TEGRA186_CLK_DSPK2 153 581 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */ 582 #define TEGRA186_CLK_I2S6 154 583 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0 */ 584 #define TEGRA186_CLK_NVDISPLAY_P0 155 585 /** @brief output of the NVDISPLAY_DISP_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP */ 586 #define TEGRA186_CLK_NVDISPLAY_DISP 156 587 /** @brief output of gate CLK_ENB_NVDISPLAY_DSC */ 588 #define TEGRA186_CLK_NVDISPLAY_DSC 157 589 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB */ 590 #define TEGRA186_CLK_NVDISPLAYHUB 158 591 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1 */ 592 #define TEGRA186_CLK_NVDISPLAY_P1 159 593 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2 */ 594 #define TEGRA186_CLK_NVDISPLAY_P2 160 595 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TACH */ 596 #define TEGRA186_CLK_TACH 166 597 /** @brief output of gate CLK_ENB_EQOS */ 598 #define TEGRA186_CLK_EQOS_AXI 167 599 /** @brief output of gate CLK_ENB_EQOS_RX */ 600 #define TEGRA186_CLK_EQOS_RX 168 601 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS */ 602 #define TEGRA186_CLK_UFSHC 178 603 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF */ 604 #define TEGRA186_CLK_UFSDEV_REF 179 605 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI */ 606 #define TEGRA186_CLK_NVCSI 180 607 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP */ 608 #define TEGRA186_CLK_NVCSILP 181 609 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */ 610 #define TEGRA186_CLK_I2C7 182 611 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */ 612 #define TEGRA186_CLK_I2C9 183 613 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C12 */ 614 #define TEGRA186_CLK_I2C12 184 615 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C13 */ 616 #define TEGRA186_CLK_I2C13 185 617 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C14 */ 618 #define TEGRA186_CLK_I2C14 186 619 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */ 620 #define TEGRA186_CLK_PWM1 187 621 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */ 622 #define TEGRA186_CLK_PWM2 188 623 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */ 624 #define TEGRA186_CLK_PWM3 189 625 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */ 626 #define TEGRA186_CLK_PWM5 190 627 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */ 628 #define TEGRA186_CLK_PWM6 191 629 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */ 630 #define TEGRA186_CLK_PWM7 192 631 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */ 632 #define TEGRA186_CLK_PWM8 193 633 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTE */ 634 #define TEGRA186_CLK_UARTE 194 635 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTF */ 636 #define TEGRA186_CLK_UARTF 195 637 /** @deprecated */ 638 #define TEGRA186_CLK_DBGAPB 196 639 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC */ 640 #define TEGRA186_CLK_BPMP_CPU_NIC 197 641 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB */ 642 #define TEGRA186_CLK_BPMP_APB 199 643 /** @brief output of mux controlled by TEGRA186_CLK_SOC_ACTMON */ 644 #define TEGRA186_CLK_ACTMON 201 645 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC */ 646 #define TEGRA186_CLK_AON_CPU_NIC 208 647 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN1 */ 648 #define TEGRA186_CLK_CAN1 210 649 /** @brief output of gate CLK_ENB_CAN1_HOST */ 650 #define TEGRA186_CLK_CAN1_HOST 211 651 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN2 */ 652 #define TEGRA186_CLK_CAN2 212 653 /** @brief output of gate CLK_ENB_CAN2_HOST */ 654 #define TEGRA186_CLK_CAN2_HOST 213 655 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB */ 656 #define TEGRA186_CLK_AON_APB 214 657 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTC */ 658 #define TEGRA186_CLK_UARTC 215 659 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTG */ 660 #define TEGRA186_CLK_UARTG 216 661 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL */ 662 #define TEGRA186_CLK_AON_UART_FST_MIPI_CAL 217 663 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */ 664 #define TEGRA186_CLK_I2C2 218 665 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */ 666 #define TEGRA186_CLK_I2C8 219 667 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C10 */ 668 #define TEGRA186_CLK_I2C10 220 669 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW */ 670 #define TEGRA186_CLK_AON_I2C_SLOW 221 671 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI2 */ 672 #define TEGRA186_CLK_SPI2 222 673 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5 */ 674 #define TEGRA186_CLK_DMIC5 223 675 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH */ 676 #define TEGRA186_CLK_AON_TOUCH 224 677 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */ 678 #define TEGRA186_CLK_PWM4 225 679 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSC. This clock object is read only and is used for all timers in the system. */ 680 #define TEGRA186_CLK_TSC 226 681 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT */ 682 #define TEGRA186_CLK_MSS_ENCRYPT 227 683 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC */ 684 #define TEGRA186_CLK_SCE_CPU_NIC 228 685 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB */ 686 #define TEGRA186_CLK_SCE_APB 230 687 /** @brief output of gate CLK_ENB_DSIC */ 688 #define TEGRA186_CLK_DSIC 231 689 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP */ 690 #define TEGRA186_CLK_DSIC_LP 232 691 /** @brief output of gate CLK_ENB_DSID */ 692 #define TEGRA186_CLK_DSID 233 693 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP */ 694 #define TEGRA186_CLK_DSID_LP 234 695 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP */ 696 #define TEGRA186_CLK_PEX_SATA_USB_RX_BYP 236 697 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT */ 698 #define TEGRA186_CLK_SPDIF_OUT 238 699 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 */ 700 #define TEGRA186_CLK_EQOS_PTP_REF 239 701 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK */ 702 #define TEGRA186_CLK_EQOS_TX 240 703 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK */ 704 #define TEGRA186_CLK_USB2_HSIC_TRK 241 705 /** @brief output of mux xusb_ss_clk_switch on page 66 of T186_Clocks_IAS.doc */ 706 #define TEGRA186_CLK_XUSB_CORE_SS 242 707 /** @brief output of mux xusb_core_dev_clk_switch on page 67 of T186_Clocks_IAS.doc */ 708 #define TEGRA186_CLK_XUSB_CORE_DEV 243 709 /** @brief output of mux xusb_core_falcon_clk_switch on page 67 of T186_Clocks_IAS.doc */ 710 #define TEGRA186_CLK_XUSB_FALCON 244 711 /** @brief output of mux xusb_fs_clk_switch on page 66 of T186_Clocks_IAS.doc */ 712 #define TEGRA186_CLK_XUSB_FS 245 713 /** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */ 714 #define TEGRA186_CLK_PLL_A_OUT0 246 715 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */ 716 #define TEGRA186_CLK_SYNC_I2S1 247 717 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */ 718 #define TEGRA186_CLK_SYNC_I2S2 248 719 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */ 720 #define TEGRA186_CLK_SYNC_I2S3 249 721 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */ 722 #define TEGRA186_CLK_SYNC_I2S4 250 723 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */ 724 #define TEGRA186_CLK_SYNC_I2S5 251 725 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */ 726 #define TEGRA186_CLK_SYNC_I2S6 252 727 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */ 728 #define TEGRA186_CLK_SYNC_DSPK1 253 729 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */ 730 #define TEGRA186_CLK_SYNC_DSPK2 254 731 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */ 732 #define TEGRA186_CLK_SYNC_DMIC1 255 733 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */ 734 #define TEGRA186_CLK_SYNC_DMIC2 256 735 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */ 736 #define TEGRA186_CLK_SYNC_DMIC3 257 737 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */ 738 #define TEGRA186_CLK_SYNC_DMIC4 259 739 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF */ 740 #define TEGRA186_CLK_SYNC_SPDIF 260 741 /** @brief output of gate CLK_ENB_PLLREFE_OUT */ 742 #define TEGRA186_CLK_PLLREFE_OUT_GATED 261 743 /** @brief output of the divider PLLREFE_DIVP in CLK_RST_CONTROLLER_PLLREFE_BASE. PLLREFE has 2 outputs: 744 * * VCO/pdiv defined by this clock object 745 * * VCO/2 defined by TEGRA186_CLK_PLLREFE_OUT 746 */ 747 #define TEGRA186_CLK_PLLREFE_OUT1 262 748 #define TEGRA186_CLK_PLLD_OUT1 267 749 /** @brief output of the divider PLLP_DIVP in CLK_RST_CONTROLLER_PLLP_BASE */ 750 #define TEGRA186_CLK_PLLP_OUT0 269 751 /** @brief output of the divider CLK_RST_CONTROLLER_PLLP_OUTC */ 752 #define TEGRA186_CLK_PLLP_OUT5 270 753 /** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */ 754 #define TEGRA186_CLK_PLLA 271 755 /** @brief output of mux controlled by CLK_RST_CONTROLLER_ACLK_BURST_POLICY divided by the divider controlled by ACLK_CLK_DIVISOR in CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER */ 756 #define TEGRA186_CLK_ACLK 273 757 /** fixed 48MHz clock divided down from TEGRA186_CLK_PLL_U */ 758 #define TEGRA186_CLK_PLL_U_48M 274 759 /** fixed 480MHz clock divided down from TEGRA186_CLK_PLL_U */ 760 #define TEGRA186_CLK_PLL_U_480M 275 761 /** @brief output of the divider PLLC4_DIVP in CLK_RST_CONTROLLER_PLLC4_BASE. Output frequency is TEGRA186_CLK_PLLC4_VCO/PLLC4_DIVP */ 762 #define TEGRA186_CLK_PLLC4_OUT0 276 763 /** fixed /3 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/3 */ 764 #define TEGRA186_CLK_PLLC4_OUT1 277 765 /** fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/5 */ 766 #define TEGRA186_CLK_PLLC4_OUT2 278 767 /** @brief output of mux controlled by PLLC4_CLK_SEL in CLK_RST_CONTROLLER_PLLC4_MISC1 */ 768 #define TEGRA186_CLK_PLLC4_OUT_MUX 279 769 /** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP when DFLLDISP_DIV is selected in NVDISPLAY_DISP_CLK_SRC */ 770 #define TEGRA186_CLK_DFLLDISP_DIV 284 771 /** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP when PLLDISPHUB_DIV is selected in NVDISPLAY_DISP_CLK_SRC */ 772 #define TEGRA186_CLK_PLLDISPHUB_DIV 285 773 /** fixed /8 divider which is used as the input for TEGRA186_CLK_SOR_SAFE */ 774 #define TEGRA186_CLK_PLLP_DIV8 286 775 /** @brief output of divider CLK_RST_CONTROLLER_BPMP_NIC_RATE */ 776 #define TEGRA186_CLK_BPMP_NIC 287 777 /** @brief output of the divider CLK_RST_CONTROLLER_PLLA1_OUT1 */ 778 #define TEGRA186_CLK_PLL_A_OUT1 288 779 /** @deprecated */ 780 #define TEGRA186_CLK_GPC2CLK 289 781 /** A fake clock which must be enabled during KFUSE read operations to ensure adequate VDD_CORE voltage. */ 782 #define TEGRA186_CLK_KFUSE 293 783 /** 784 * @brief controls the PLLE hardware sequencer. 785 * @details This clock only has enable and disable methods. When the 786 * PLLE hw sequencer is enabled, PLLE, will be enabled or disabled by 787 * hw based on the control signals from the PCIe, SATA and XUSB 788 * clocks. When the PLLE hw sequencer is disabled, the state of PLLE 789 * is controlled by sw using clk_enable/clk_disable on 790 * TEGRA186_CLK_PLLE. 791 */ 792 #define TEGRA186_CLK_PLLE_PWRSEQ 294 793 /** fixed 60MHz clock divided down from, TEGRA186_CLK_PLL_U */ 794 #define TEGRA186_CLK_PLLREFE_REF 295 795 /** @brief output of mux controlled by SOR0_CLK_SEL0 and SOR0_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */ 796 #define TEGRA186_CLK_SOR0_OUT 296 797 /** @brief output of mux controlled by SOR1_CLK_SEL0 and SOR1_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */ 798 #define TEGRA186_CLK_SOR1_OUT 297 799 /** @brief fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLREFE_OUT1/5. Used as input for TEGRA186_CLK_EQOS_AXI */ 800 #define TEGRA186_CLK_PLLREFE_OUT1_DIV5 298 801 /** @brief controls the UTMIP_PLL (aka PLLU) hardware sqeuencer */ 802 #define TEGRA186_CLK_UTMIP_PLL_PWRSEQ 301 803 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT */ 804 #define TEGRA186_CLK_PEX_USB_PAD0_MGMT 302 805 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT */ 806 #define TEGRA186_CLK_PEX_USB_PAD1_MGMT 303 807 /** @brief controls the UPHY_PLL0 hardware sqeuencer */ 808 #define TEGRA186_CLK_UPHY_PLL0_PWRSEQ 304 809 /** @brief controls the UPHY_PLL1 hardware sqeuencer */ 810 #define TEGRA186_CLK_UPHY_PLL1_PWRSEQ 305 811 /** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC so the bypass output even be used when the PLL is disabled */ 812 #define TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH 306 813 /** @brief output of the mux controlled by PLLREFE_SEL_CLKIN_PEX in CLK_RST_CONTROLLER_PLLREFE_MISC */ 814 #define TEGRA186_CLK_PLLREFE_PEX 307 815 /** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC to turn on the PLL when enabled */ 816 #define TEGRA186_CLK_PLLREFE_IDDQ 308 817 /** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */ 818 #define TEGRA186_CLK_QSPI_OUT 309 819 /** 820 * @brief GPC2CLK-div-2 821 * @details fixed /2 divider. Output frequency is 822 * TEGRA186_CLK_GPC2CLK/2. The frequency of this clock is the 823 * frequency at which the GPU graphics engine runs. */ 824 #define TEGRA186_CLK_GPCCLK 310 825 /** @brief output of divider CLK_RST_CONTROLLER_AON_NIC_RATE */ 826 #define TEGRA186_CLK_AON_NIC 450 827 /** @brief output of divider CLK_RST_CONTROLLER_SCE_NIC_RATE */ 828 #define TEGRA186_CLK_SCE_NIC 451 829 /** Fixed 100MHz PLL for PCIe, SATA and superspeed USB */ 830 #define TEGRA186_CLK_PLLE 512 831 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC_BASE */ 832 #define TEGRA186_CLK_PLLC 513 833 /** Fixed 408MHz PLL for use by peripheral clocks */ 834 #define TEGRA186_CLK_PLLP 516 835 /** @deprecated */ 836 #define TEGRA186_CLK_PLL_P TEGRA186_CLK_PLLP 837 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD_BASE for use by DSI */ 838 #define TEGRA186_CLK_PLLD 518 839 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD2_BASE for use by HDMI or DP */ 840 #define TEGRA186_CLK_PLLD2 519 841 /** 842 * @brief PLL controlled by CLK_RST_CONTROLLER_PLLREFE_BASE. 843 * @details Note that this clock only controls the VCO output, before 844 * the post-divider. See TEGRA186_CLK_PLLREFE_OUT1 for more 845 * information. 846 */ 847 #define TEGRA186_CLK_PLLREFE_VCO 520 848 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC2_BASE */ 849 #define TEGRA186_CLK_PLLC2 521 850 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC3_BASE */ 851 #define TEGRA186_CLK_PLLC3 522 852 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDP_BASE for use as the DP link clock */ 853 #define TEGRA186_CLK_PLLDP 523 854 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */ 855 #define TEGRA186_CLK_PLLC4_VCO 524 856 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLA1_BASE for use by audio clocks */ 857 #define TEGRA186_CLK_PLLA1 525 858 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLNVCSI_BASE */ 859 #define TEGRA186_CLK_PLLNVCSI 526 860 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDISPHUB_BASE */ 861 #define TEGRA186_CLK_PLLDISPHUB 527 862 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD3_BASE for use by HDMI or DP */ 863 #define TEGRA186_CLK_PLLD3 528 864 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLBPMPCAM_BASE */ 865 #define TEGRA186_CLK_PLLBPMPCAM 531 866 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLAON_BASE for use by IP blocks in the AON domain */ 867 #define TEGRA186_CLK_PLLAON 532 868 /** Fixed frequency 960MHz PLL for USB and EAVB */ 869 #define TEGRA186_CLK_PLLU 533 870 /** fixed /2 divider. Output frequency is TEGRA186_CLK_PLLC4_VCO/2 */ 871 #define TEGRA186_CLK_PLLC4_VCO_DIV2 535 872 /** @brief NAFLL clock source for AXI_CBB */ 873 #define TEGRA186_CLK_NAFLL_AXI_CBB 564 874 /** @brief NAFLL clock source for BPMP */ 875 #define TEGRA186_CLK_NAFLL_BPMP 565 876 /** @brief NAFLL clock source for ISP */ 877 #define TEGRA186_CLK_NAFLL_ISP 566 878 /** @brief NAFLL clock source for NVDEC */ 879 #define TEGRA186_CLK_NAFLL_NVDEC 567 880 /** @brief NAFLL clock source for NVENC */ 881 #define TEGRA186_CLK_NAFLL_NVENC 568 882 /** @brief NAFLL clock source for NVJPG */ 883 #define TEGRA186_CLK_NAFLL_NVJPG 569 884 /** @brief NAFLL clock source for SCE */ 885 #define TEGRA186_CLK_NAFLL_SCE 570 886 /** @brief NAFLL clock source for SE */ 887 #define TEGRA186_CLK_NAFLL_SE 571 888 /** @brief NAFLL clock source for TSEC */ 889 #define TEGRA186_CLK_NAFLL_TSEC 572 890 /** @brief NAFLL clock source for TSECB */ 891 #define TEGRA186_CLK_NAFLL_TSECB 573 892 /** @brief NAFLL clock source for VI */ 893 #define TEGRA186_CLK_NAFLL_VI 574 894 /** @brief NAFLL clock source for VIC */ 895 #define TEGRA186_CLK_NAFLL_VIC 575 896 /** @brief NAFLL clock source for DISP */ 897 #define TEGRA186_CLK_NAFLL_DISP 576 898 /** @brief NAFLL clock source for GPU */ 899 #define TEGRA186_CLK_NAFLL_GPU 577 900 /** @brief NAFLL clock source for M-CPU cluster */ 901 #define TEGRA186_CLK_NAFLL_MCPU 578 902 /** @brief NAFLL clock source for B-CPU cluster */ 903 #define TEGRA186_CLK_NAFLL_BCPU 579 904 /** @brief input from Tegra's CLK_32K_IN pad */ 905 #define TEGRA186_CLK_CLK_32K 608 906 /** @brief output of divider CLK_RST_CONTROLLER_CLK_M_DIVIDE */ 907 #define TEGRA186_CLK_CLK_M 609 908 /** @brief output of divider PLL_REF_DIV in CLK_RST_CONTROLLER_OSC_CTRL */ 909 #define TEGRA186_CLK_PLL_REF 610 910 /** @brief input from Tegra's XTAL_IN */ 911 #define TEGRA186_CLK_OSC 612 912 /** @brief clock recovered from EAVB input */ 913 #define TEGRA186_CLK_EQOS_RX_INPUT 613 914 /** @brief clock recovered from DTV input */ 915 #define TEGRA186_CLK_DTV_INPUT 614 916 /** @brief SOR0 brick output which feeds into SOR0_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0*/ 917 #define TEGRA186_CLK_SOR0_PAD_CLKOUT 615 918 /** @brief SOR1 brick output which feeds into SOR1_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1*/ 919 #define TEGRA186_CLK_SOR1_PAD_CLKOUT 616 920 /** @brief clock recovered from I2S1 input */ 921 #define TEGRA186_CLK_I2S1_SYNC_INPUT 617 922 /** @brief clock recovered from I2S2 input */ 923 #define TEGRA186_CLK_I2S2_SYNC_INPUT 618 924 /** @brief clock recovered from I2S3 input */ 925 #define TEGRA186_CLK_I2S3_SYNC_INPUT 619 926 /** @brief clock recovered from I2S4 input */ 927 #define TEGRA186_CLK_I2S4_SYNC_INPUT 620 928 /** @brief clock recovered from I2S5 input */ 929 #define TEGRA186_CLK_I2S5_SYNC_INPUT 621 930 /** @brief clock recovered from I2S6 input */ 931 #define TEGRA186_CLK_I2S6_SYNC_INPUT 622 932 /** @brief clock recovered from SPDIFIN input */ 933 #define TEGRA186_CLK_SPDIFIN_SYNC_INPUT 623 934 935 /** 936 * @brief subject to change 937 * @details maximum clock identifier value plus one. 938 */ 939 #define TEGRA186_CLK_CLK_MAX 624 940 941 /** @} */ 942 943 #endif 944
Indexes created Mon Oct 06 08:10:01 GMT 2025