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      1 /*	$NetBSD: tegra20-car.h,v 1.1.1.3 2021/11/07 16:49:58 jmcneill Exp $	*/
      2 
      3 /* SPDX-License-Identifier: GPL-2.0 */
      4 /*
      5  * This header provides constants for binding nvidia,tegra20-car.
      6  *
      7  * The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
      8  * registers. These IDs often match those in the CAR's RST_DEVICES registers,
      9  * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
     10  * this case, those clocks are assigned IDs above 95 in order to highlight
     11  * this issue. Implementations that interpret these clock IDs as bit values
     12  * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
     13  * explicitly handle these special cases.
     14  *
     15  * The balance of the clocks controlled by the CAR are assigned IDs of 96 and
     16  * above.
     17  */
     18 
     19 #ifndef _DT_BINDINGS_CLOCK_TEGRA20_CAR_H
     20 #define _DT_BINDINGS_CLOCK_TEGRA20_CAR_H
     21 
     22 #define TEGRA20_CLK_CPU 0
     23 /* 1 */
     24 /* 2 */
     25 #define TEGRA20_CLK_AC97 3
     26 #define TEGRA20_CLK_RTC 4
     27 #define TEGRA20_CLK_TIMER 5
     28 #define TEGRA20_CLK_UARTA 6
     29 /* 7 (register bit affects uart2 and vfir) */
     30 #define TEGRA20_CLK_GPIO 8
     31 #define TEGRA20_CLK_SDMMC2 9
     32 /* 10 (register bit affects spdif_in and spdif_out) */
     33 #define TEGRA20_CLK_I2S1 11
     34 #define TEGRA20_CLK_I2C1 12
     35 #define TEGRA20_CLK_NDFLASH 13
     36 #define TEGRA20_CLK_SDMMC1 14
     37 #define TEGRA20_CLK_SDMMC4 15
     38 #define TEGRA20_CLK_TWC 16
     39 #define TEGRA20_CLK_PWM 17
     40 #define TEGRA20_CLK_I2S2 18
     41 #define TEGRA20_CLK_EPP 19
     42 /* 20 (register bit affects vi and vi_sensor) */
     43 #define TEGRA20_CLK_GR2D 21
     44 #define TEGRA20_CLK_USBD 22
     45 #define TEGRA20_CLK_ISP 23
     46 #define TEGRA20_CLK_GR3D 24
     47 #define TEGRA20_CLK_IDE 25
     48 #define TEGRA20_CLK_DISP2 26
     49 #define TEGRA20_CLK_DISP1 27
     50 #define TEGRA20_CLK_HOST1X 28
     51 #define TEGRA20_CLK_VCP 29
     52 /* 30 */
     53 #define TEGRA20_CLK_CACHE2 31
     54 
     55 #define TEGRA20_CLK_MC 32
     56 #define TEGRA20_CLK_AHBDMA 33
     57 #define TEGRA20_CLK_APBDMA 34
     58 /* 35 */
     59 #define TEGRA20_CLK_KBC 36
     60 #define TEGRA20_CLK_STAT_MON 37
     61 #define TEGRA20_CLK_PMC 38
     62 #define TEGRA20_CLK_FUSE 39
     63 #define TEGRA20_CLK_KFUSE 40
     64 #define TEGRA20_CLK_SBC1 41
     65 #define TEGRA20_CLK_NOR 42
     66 #define TEGRA20_CLK_SPI 43
     67 #define TEGRA20_CLK_SBC2 44
     68 #define TEGRA20_CLK_XIO 45
     69 #define TEGRA20_CLK_SBC3 46
     70 #define TEGRA20_CLK_DVC 47
     71 #define TEGRA20_CLK_DSI 48
     72 /* 49 (register bit affects tvo and cve) */
     73 #define TEGRA20_CLK_MIPI 50
     74 #define TEGRA20_CLK_HDMI 51
     75 #define TEGRA20_CLK_CSI 52
     76 #define TEGRA20_CLK_TVDAC 53
     77 #define TEGRA20_CLK_I2C2 54
     78 #define TEGRA20_CLK_UARTC 55
     79 /* 56 */
     80 #define TEGRA20_CLK_EMC 57
     81 #define TEGRA20_CLK_USB2 58
     82 #define TEGRA20_CLK_USB3 59
     83 #define TEGRA20_CLK_MPE 60
     84 #define TEGRA20_CLK_VDE 61
     85 #define TEGRA20_CLK_BSEA 62
     86 #define TEGRA20_CLK_BSEV 63
     87 
     88 #define TEGRA20_CLK_SPEEDO 64
     89 #define TEGRA20_CLK_UARTD 65
     90 #define TEGRA20_CLK_UARTE 66
     91 #define TEGRA20_CLK_I2C3 67
     92 #define TEGRA20_CLK_SBC4 68
     93 #define TEGRA20_CLK_SDMMC3 69
     94 #define TEGRA20_CLK_PEX 70
     95 #define TEGRA20_CLK_OWR 71
     96 #define TEGRA20_CLK_AFI 72
     97 #define TEGRA20_CLK_CSITE 73
     98 /* 74 */
     99 #define TEGRA20_CLK_AVPUCQ 75
    100 #define TEGRA20_CLK_LA 76
    101 /* 77 */
    102 /* 78 */
    103 /* 79 */
    104 /* 80 */
    105 /* 81 */
    106 /* 82 */
    107 /* 83 */
    108 #define TEGRA20_CLK_IRAMA 84
    109 #define TEGRA20_CLK_IRAMB 85
    110 #define TEGRA20_CLK_IRAMC 86
    111 #define TEGRA20_CLK_IRAMD 87
    112 #define TEGRA20_CLK_CRAM2 88
    113 #define TEGRA20_CLK_AUDIO_2X 89 /* a/k/a audio_2x_sync_clk */
    114 #define TEGRA20_CLK_CLK_D 90
    115 /* 91 */
    116 #define TEGRA20_CLK_CSUS 92
    117 #define TEGRA20_CLK_CDEV2 93
    118 #define TEGRA20_CLK_CDEV1 94
    119 /* 95 */
    120 
    121 #define TEGRA20_CLK_UARTB 96
    122 #define TEGRA20_CLK_VFIR 97
    123 #define TEGRA20_CLK_SPDIF_IN 98
    124 #define TEGRA20_CLK_SPDIF_OUT 99
    125 #define TEGRA20_CLK_VI 100
    126 #define TEGRA20_CLK_VI_SENSOR 101
    127 #define TEGRA20_CLK_TVO 102
    128 #define TEGRA20_CLK_CVE 103
    129 #define TEGRA20_CLK_OSC 104
    130 #define TEGRA20_CLK_CLK_32K 105 /* a/k/a clk_s */
    131 #define TEGRA20_CLK_CLK_M 106
    132 #define TEGRA20_CLK_SCLK 107
    133 #define TEGRA20_CLK_CCLK 108
    134 #define TEGRA20_CLK_HCLK 109
    135 #define TEGRA20_CLK_PCLK 110
    136 /* 111 */
    137 #define TEGRA20_CLK_PLL_A 112
    138 #define TEGRA20_CLK_PLL_A_OUT0 113
    139 #define TEGRA20_CLK_PLL_C 114
    140 #define TEGRA20_CLK_PLL_C_OUT1 115
    141 #define TEGRA20_CLK_PLL_D 116
    142 #define TEGRA20_CLK_PLL_D_OUT0 117
    143 #define TEGRA20_CLK_PLL_E 118
    144 #define TEGRA20_CLK_PLL_M 119
    145 #define TEGRA20_CLK_PLL_M_OUT1 120
    146 #define TEGRA20_CLK_PLL_P 121
    147 #define TEGRA20_CLK_PLL_P_OUT1 122
    148 #define TEGRA20_CLK_PLL_P_OUT2 123
    149 #define TEGRA20_CLK_PLL_P_OUT3 124
    150 #define TEGRA20_CLK_PLL_P_OUT4 125
    151 #define TEGRA20_CLK_PLL_S 126
    152 #define TEGRA20_CLK_PLL_U 127
    153 
    154 #define TEGRA20_CLK_PLL_X 128
    155 #define TEGRA20_CLK_COP 129 /* a/k/a avp */
    156 #define TEGRA20_CLK_AUDIO 130 /* a/k/a audio_sync_clk */
    157 #define TEGRA20_CLK_PLL_REF 131
    158 #define TEGRA20_CLK_TWD 132
    159 #define TEGRA20_CLK_CLK_MAX 133
    160 
    161 #endif	/* _DT_BINDINGS_CLOCK_TEGRA20_CAR_H */
    162