Home | History | Annotate | Line # | Download | only in clock 
      1 /*	$NetBSD: stm32h7-clks.h,v 1.1.1.1 2017/10/28 10:30:32 jmcneill Exp $	*/
      2 
      3 /* SYS, CORE AND BUS CLOCKS */
      4 #define SYS_D1CPRE 0
      5 #define HCLK 1
      6 #define PCLK1 2
      7 #define PCLK2 3
      8 #define PCLK3 4
      9 #define PCLK4 5
     10 #define HSI_DIV 6
     11 #define HSE_1M 7
     12 #define I2S_CKIN 8
     13 #define CK_DSI_PHY 9
     14 #define HSE_CK 10
     15 #define LSE_CK 11
     16 #define CSI_KER_DIV122 12
     17 #define RTC_CK 13
     18 #define CPU_SYSTICK 14
     19 
     20 /* OSCILLATOR BANK */
     21 #define OSC_BANK 18
     22 #define HSI_CK 18
     23 #define HSI_KER_CK 19
     24 #define CSI_CK 20
     25 #define CSI_KER_CK 21
     26 #define RC48_CK 22
     27 #define LSI_CK 23
     28 
     29 /* MCLOCK BANK */
     30 #define MCLK_BANK 28
     31 #define PER_CK 28
     32 #define PLLSRC 29
     33 #define SYS_CK 30
     34 #define TRACEIN_CK 31
     35 
     36 /* ODF BANK */
     37 #define ODF_BANK 32
     38 #define PLL1_P 32
     39 #define PLL1_Q 33
     40 #define PLL1_R 34
     41 #define PLL2_P 35
     42 #define PLL2_Q 36
     43 #define PLL2_R 37
     44 #define PLL3_P 38
     45 #define PLL3_Q 39
     46 #define PLL3_R 40
     47 
     48 /* MCO BANK */
     49 #define MCO_BANK 41
     50 #define MCO1 41
     51 #define MCO2 42
     52 
     53 /* PERIF BANK */
     54 #define PERIF_BANK 50
     55 #define D1SRAM1_CK 50
     56 #define ITCM_CK 51
     57 #define DTCM2_CK 52
     58 #define DTCM1_CK 53
     59 #define FLITF_CK 54
     60 #define JPGDEC_CK 55
     61 #define DMA2D_CK 56
     62 #define MDMA_CK 57
     63 #define USB2ULPI_CK 58
     64 #define USB1ULPI_CK 59
     65 #define ETH1RX_CK 60
     66 #define ETH1TX_CK 61
     67 #define ETH1MAC_CK 62
     68 #define ART_CK 63
     69 #define DMA2_CK 64
     70 #define DMA1_CK 65
     71 #define D2SRAM3_CK 66
     72 #define D2SRAM2_CK 67
     73 #define D2SRAM1_CK 68
     74 #define HASH_CK 69
     75 #define CRYPT_CK 70
     76 #define CAMITF_CK 71
     77 #define BKPRAM_CK 72
     78 #define HSEM_CK 73
     79 #define BDMA_CK 74
     80 #define CRC_CK 75
     81 #define GPIOK_CK 76
     82 #define GPIOJ_CK 77
     83 #define GPIOI_CK 78
     84 #define GPIOH_CK 79
     85 #define GPIOG_CK 80
     86 #define GPIOF_CK 81
     87 #define GPIOE_CK 82
     88 #define GPIOD_CK 83
     89 #define GPIOC_CK 84
     90 #define GPIOB_CK 85
     91 #define GPIOA_CK 86
     92 #define WWDG1_CK 87
     93 #define DAC12_CK 88
     94 #define WWDG2_CK 89
     95 #define TIM14_CK 90
     96 #define TIM13_CK 91
     97 #define TIM12_CK 92
     98 #define TIM7_CK 93
     99 #define TIM6_CK 94
    100 #define TIM5_CK 95
    101 #define TIM4_CK 96
    102 #define TIM3_CK 97
    103 #define TIM2_CK 98
    104 #define MDIOS_CK 99
    105 #define OPAMP_CK 100
    106 #define CRS_CK 101
    107 #define TIM17_CK 102
    108 #define TIM16_CK 103
    109 #define TIM15_CK 104
    110 #define TIM8_CK 105
    111 #define TIM1_CK 106
    112 #define TMPSENS_CK 107
    113 #define RTCAPB_CK 108
    114 #define VREF_CK 109
    115 #define COMP12_CK 110
    116 #define SYSCFG_CK 111
    117 
    118 /* KERNEL BANK */
    119 #define KERN_BANK 120
    120 #define SDMMC1_CK 120
    121 #define QUADSPI_CK 121
    122 #define FMC_CK 122
    123 #define USB2OTG_CK 123
    124 #define USB1OTG_CK 124
    125 #define ADC12_CK 125
    126 #define SDMMC2_CK 126
    127 #define RNG_CK 127
    128 #define ADC3_CK 128
    129 #define DSI_CK 129
    130 #define LTDC_CK 130
    131 #define USART8_CK 131
    132 #define USART7_CK 132
    133 #define HDMICEC_CK 133
    134 #define I2C3_CK 134
    135 #define I2C2_CK 135
    136 #define I2C1_CK 136
    137 #define UART5_CK 137
    138 #define UART4_CK 138
    139 #define USART3_CK 139
    140 #define USART2_CK 140
    141 #define SPDIFRX_CK 141
    142 #define SPI3_CK 142
    143 #define SPI2_CK 143
    144 #define LPTIM1_CK 144
    145 #define FDCAN_CK 145
    146 #define SWP_CK 146
    147 #define HRTIM_CK 147
    148 #define DFSDM1_CK 148
    149 #define SAI3_CK 149
    150 #define SAI2_CK 150
    151 #define SAI1_CK 151
    152 #define SPI5_CK 152
    153 #define SPI4_CK 153
    154 #define SPI1_CK 154
    155 #define USART6_CK 155
    156 #define USART1_CK 156
    157 #define SAI4B_CK 157
    158 #define SAI4A_CK 158
    159 #define LPTIM5_CK 159
    160 #define LPTIM4_CK 160
    161 #define LPTIM3_CK 161
    162 #define LPTIM2_CK 162
    163 #define I2C4_CK 163
    164 #define SPI6_CK 164
    165 #define LPUART1_CK 165
    166 
    167 #define STM32H7_MAX_CLKS 166
    168