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    Searched defs:TIMER_WRITE (Results 1 - 5 of 5) sorted by relevancy

  /src/sys/arch/arm/nvidia/
tegra_timer.c 69 #define TIMER_WRITE(sc, reg, val) \
146 TIMER_WRITE(sc, TMR1_PTV_REG,
148 TIMER_WRITE(sc, TMR1_PCR_REG, TMR_PCR_INTR_CLR);
159 TIMER_WRITE(sc, TMR1_PCR_REG, TMR_PCR_INTR_CLR);
  /src/sys/arch/arm/amlogic/
meson6_timer.c 59 #define TIMER_WRITE(sc, reg, val) \
150 TIMER_WRITE(sc, MESON_TIMER_MUX, mask);
  /src/sys/arch/arm/imx/
imx23_timrot.c 110 #define TIMER_WRITE(sc, reg, val) \
260 TIMER_WRITE(sc, TIMER_CTRL, ctrl);
275 TIMER_WRITE(timer_sc[SYS_TIMER], TIMER_CTRL_CLR, IRQ);
285 TIMER_WRITE(timer_sc[STAT_TIMER], TIMER_CTRL_CLR, IRQ);
  /src/sys/arch/arm/sunxi/
sunxi_hstimer.c 98 #define TIMER_WRITE(sc, reg, val) \
110 TIMER_WRITE(sc, HS_TMR_IRQ_STAS_REG, stas);
167 TIMER_WRITE(sc, HS_TMR_IRQ_EN_REG, 0);
168 TIMER_WRITE(sc, HS_TMR_IRQ_STAS_REG, TIMER_READ(sc, HS_TMR_IRQ_STAS_REG));
170 TIMER_WRITE(sc, HS_TMR0_CTRL_REG, 0);
171 TIMER_WRITE(sc, HS_TMR0_INTV_LO_REG, ~0u);
172 TIMER_WRITE(sc, HS_TMR0_INTV_HI_REG, ~0u);
173 TIMER_WRITE(sc, HS_TMR0_CTRL_REG,
sunxi_timer.c 112 #define TIMER_WRITE(sc, reg, val) \
127 TIMER_WRITE(sc, TMR_IRQ_STAS_REG, stas);
156 TIMER_WRITE(sc, TMR_IRQ_EN_REG, irq_en | TMR_IRQ_EN(0));
221 TIMER_WRITE(sc, TMR_IRQ_EN_REG, 0);
222 TIMER_WRITE(sc, TMR_IRQ_STAS_REG, TIMER_READ(sc, TMR_IRQ_STAS_REG));
224 TIMER_WRITE(sc, TMR0_INTV_VALUE_REG, rate / hz);
225 TIMER_WRITE(sc, TMR0_CTRL_REG,
229 TIMER_WRITE(sc, TMR2_INTV_VALUE_REG, ~0u);
230 TIMER_WRITE(sc, TMR2_CTRL_REG,
234 TIMER_WRITE(sc, TMR4_INTV_VALUE_REG, ~0u)
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