1 /* $NetBSD: if_alc.c,v 1.57 2026/10/02 18:53:06 riastradh Exp $ */ 2 /* $OpenBSD: if_alc.c,v 1.1 2009/08/08 09:31:13 kevlo Exp $ */ 3 /*- 4 * Copyright (c) 2009, Pyun YongHyeon <yongari (at) FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* Driver for Atheros AR813x/AR815x PCIe Ethernet. */ 31 32 #ifdef _KERNEL_OPT 33 #include "vlan.h" 34 #endif 35 36 #include <sys/param.h> 37 #include <sys/proc.h> 38 #include <sys/endian.h> 39 #include <sys/systm.h> 40 #include <sys/types.h> 41 #include <sys/sockio.h> 42 #include <sys/mbuf.h> 43 #include <sys/queue.h> 44 #include <sys/kernel.h> 45 #include <sys/device.h> 46 #include <sys/callout.h> 47 #include <sys/socket.h> 48 #include <sys/module.h> 49 50 #include <sys/bus.h> 51 52 #include <net/bpf.h> 53 #include <net/if.h> 54 #include <net/if_dl.h> 55 #include <net/if_llc.h> 56 #include <net/if_media.h> 57 #include <net/if_ether.h> 58 59 #ifdef INET 60 #include <netinet/in.h> 61 #include <netinet/in_systm.h> 62 #include <netinet/in_var.h> 63 #include <netinet/ip.h> 64 #endif 65 66 #include <net/if_types.h> 67 #include <net/if_vlanvar.h> 68 69 #include <dev/mii/mii.h> 70 #include <dev/mii/miivar.h> 71 72 #include <dev/pci/pcireg.h> 73 #include <dev/pci/pcivar.h> 74 #include <dev/pci/pcidevs.h> 75 76 #include <dev/pci/if_alcreg.h> 77 78 /* 79 * Devices supported by this driver. 80 */ 81 static const struct alc_ident alc_ident_table[] = { 82 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8131, 9 * 1024, 83 "Atheros AR8131 PCIe Gigabit Ethernet" }, 84 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8132, 9 * 1024, 85 "Atheros AR8132 PCIe Fast Ethernet" }, 86 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8151, 6 * 1024, 87 "Atheros AR8151 v1.0 PCIe Gigabit Ethernet" }, 88 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8151_V2, 6 * 1024, 89 "Atheros AR8151 v2.0 PCIe Gigabit Ethernet" }, 90 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8152_B, 6 * 1024, 91 "Atheros AR8152 v1.1 PCIe Fast Ethernet" }, 92 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8152_B2, 6 * 1024, 93 "Atheros AR8152 v2.0 PCIe Fast Ethernet" }, 94 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8161, 9 * 1024, 95 "Atheros AR8161 PCIe Gigabit Ethernet" }, 96 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8162, 9 * 1024, 97 "Atheros AR8162 PCIe Fast Ethernet" }, 98 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8171, 9 * 1024, 99 "Atheros AR8171 PCIe Gigabit Ethernet" }, 100 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8172, 9 * 1024, 101 "Atheros AR8172 PCIe Fast Ethernet" }, 102 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_E2200, 9 * 1024, 103 "Killer E2200 Gigabit Ethernet" }, 104 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_E2400, 9 * 1024, 105 "Killer E2400 Gigabit Ethernet" }, 106 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_E2500, 9 * 1024, 107 "Killer E2500 Gigabit Ethernet" }, 108 { 0, 0, 0, NULL }, 109 }; 110 111 static int alc_match(device_t, cfdata_t, void *); 112 static void alc_attach(device_t, device_t, void *); 113 static int alc_detach(device_t, int); 114 115 static int alc_init(struct ifnet *); 116 static int alc_init_backend(struct ifnet *, bool); 117 static void alc_start(struct ifnet *); 118 static int alc_ioctl(struct ifnet *, u_long, void *); 119 static void alc_watchdog(struct ifnet *); 120 static int alc_mediachange(struct ifnet *); 121 static void alc_mediastatus(struct ifnet *, struct ifmediareq *); 122 123 static void alc_aspm(struct alc_softc *, int, int); 124 static void alc_aspm_813x(struct alc_softc *, int); 125 static void alc_aspm_816x(struct alc_softc *, int); 126 static void alc_disable_l0s_l1(struct alc_softc *); 127 static int alc_dma_alloc(struct alc_softc *); 128 static void alc_dma_free(struct alc_softc *); 129 static void alc_dsp_fixup(struct alc_softc *, int); 130 static int alc_encap(struct alc_softc *, struct mbuf **); 131 static const struct alc_ident * 132 alc_find_ident(struct pci_attach_args *); 133 static void alc_get_macaddr(struct alc_softc *); 134 static void alc_get_macaddr_813x(struct alc_softc *); 135 static void alc_get_macaddr_816x(struct alc_softc *); 136 static void alc_get_macaddr_par(struct alc_softc *); 137 static void alc_init_cmb(struct alc_softc *); 138 static void alc_init_rr_ring(struct alc_softc *); 139 static int alc_init_rx_ring(struct alc_softc *, bool); 140 static void alc_init_smb(struct alc_softc *); 141 static void alc_init_tx_ring(struct alc_softc *); 142 static int alc_intr(void *); 143 static void alc_mac_config(struct alc_softc *); 144 static int alc_mii_readreg_813x(struct alc_softc *, int, int, uint16_t *); 145 static int alc_mii_readreg_816x(struct alc_softc *, int, int, uint16_t *); 146 static int alc_mii_writereg_813x(struct alc_softc *, int, int, uint16_t); 147 static int alc_mii_writereg_816x(struct alc_softc *, int, int, uint16_t); 148 static int alc_miibus_readreg(device_t, int, int, uint16_t *); 149 static void alc_miibus_statchg(struct ifnet *); 150 static int alc_miibus_writereg(device_t, int, int, uint16_t); 151 static int alc_miidbg_readreg(struct alc_softc *, int, uint16_t *); 152 static int alc_miidbg_writereg(struct alc_softc *, int, uint16_t); 153 static int alc_miiext_readreg(struct alc_softc *, int, int, uint16_t *); 154 static int alc_miiext_writereg(struct alc_softc *, int, int, uint16_t); 155 static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *, bool); 156 static void alc_phy_down(struct alc_softc *); 157 static void alc_phy_reset(struct alc_softc *); 158 static void alc_phy_reset_813x(struct alc_softc *); 159 static void alc_phy_reset_816x(struct alc_softc *); 160 static void alc_reset(struct alc_softc *); 161 static void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 162 static int alc_rxintr(struct alc_softc *); 163 static void alc_iff(struct alc_softc *); 164 static void alc_rxvlan(struct alc_softc *); 165 static void alc_start_queue(struct alc_softc *); 166 static void alc_stats_clear(struct alc_softc *); 167 static void alc_stats_update(struct alc_softc *); 168 static void alc_stop(struct ifnet *, int); 169 static void alc_stop_mac(struct alc_softc *); 170 static void alc_stop_queue(struct alc_softc *); 171 static void alc_tick(void *); 172 static void alc_txeof(struct alc_softc *); 173 static void alc_init_pcie(struct alc_softc *); 174 175 static const uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0, 0 }; 176 177 CFATTACH_DECL_NEW(alc, sizeof(struct alc_softc), 178 alc_match, alc_attach, alc_detach, NULL); 179 180 int alcdebug = 0; 181 #define DPRINTF(x) do { if (alcdebug) printf x; } while (0) 182 183 #define ALC_CSUM_FEATURES (M_CSUM_TCPv4 | M_CSUM_UDPv4) 184 185 static int 186 alc_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 187 { 188 struct alc_softc *sc = device_private(dev); 189 int v; 190 191 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 192 v = alc_mii_readreg_816x(sc, phy, reg, val); 193 else 194 v = alc_mii_readreg_813x(sc, phy, reg, val); 195 return (v); 196 } 197 198 static int 199 alc_mii_readreg_813x(struct alc_softc *sc, int phy, int reg, uint16_t *val) 200 { 201 uint32_t v; 202 int i; 203 204 if (phy != sc->alc_phyaddr) 205 return -1; 206 207 /* 208 * For AR8132 fast ethernet controller, do not report 1000baseT 209 * capability to mii(4). Even though AR8132 uses the same 210 * model/revision number of F1 gigabit PHY, the PHY has no 211 * ability to establish 1000baseT link. 212 */ 213 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && reg == MII_EXTSR) { 214 *val = 0; 215 return 0; 216 } 217 218 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 219 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 220 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 221 DELAY(5); 222 v = CSR_READ_4(sc, ALC_MDIO); 223 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 224 break; 225 } 226 227 if (i == 0) { 228 printf("%s: phy read timeout: phy %d, reg %d\n", 229 device_xname(sc->sc_dev), phy, reg); 230 return ETIMEDOUT; 231 } 232 233 *val = (v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT; 234 return 0; 235 } 236 237 static int 238 alc_mii_readreg_816x(struct alc_softc *sc, int phy, int reg, uint16_t *val) 239 { 240 uint32_t clk, v; 241 int i; 242 243 if (phy != sc->alc_phyaddr) 244 return -1; 245 246 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 247 clk = MDIO_CLK_25_128; 248 else 249 clk = MDIO_CLK_25_4; 250 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 251 MDIO_SUP_PREAMBLE | clk | MDIO_REG_ADDR(reg)); 252 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 253 DELAY(5); 254 v = CSR_READ_4(sc, ALC_MDIO); 255 if ((v & MDIO_OP_BUSY) == 0) 256 break; 257 } 258 259 if (i == 0) { 260 printf("%s: phy read timeout: phy %d, reg %d\n", 261 device_xname(sc->sc_dev), phy, reg); 262 return ETIMEDOUT; 263 } 264 265 *val = (v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT; 266 return 0; 267 } 268 269 static int 270 alc_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 271 { 272 struct alc_softc *sc = device_private(dev); 273 int rv; 274 275 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 276 rv = alc_mii_writereg_816x(sc, phy, reg, val); 277 else 278 rv = alc_mii_writereg_813x(sc, phy, reg, val); 279 280 return rv; 281 } 282 283 static int 284 alc_mii_writereg_813x(struct alc_softc *sc, int phy, int reg, uint16_t val) 285 { 286 uint32_t v; 287 int i; 288 289 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 290 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 291 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 292 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 293 DELAY(5); 294 v = CSR_READ_4(sc, ALC_MDIO); 295 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 296 break; 297 } 298 299 if (i == 0) { 300 printf("%s: phy write timeout: phy %d, reg %d\n", 301 device_xname(sc->sc_dev), phy, reg); 302 return ETIMEDOUT; 303 } 304 305 return 0; 306 } 307 308 static int 309 alc_mii_writereg_816x(struct alc_softc *sc, int phy, int reg, uint16_t val) 310 { 311 uint32_t clk, v; 312 int i; 313 314 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 315 clk = MDIO_CLK_25_128; 316 else 317 clk = MDIO_CLK_25_4; 318 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 319 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | MDIO_REG_ADDR(reg) | 320 MDIO_SUP_PREAMBLE | clk); 321 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 322 DELAY(5); 323 v = CSR_READ_4(sc, ALC_MDIO); 324 if ((v & MDIO_OP_BUSY) == 0) 325 break; 326 } 327 328 if (i == 0) { 329 printf("%s: phy write timeout: phy %d, reg %d\n", 330 device_xname(sc->sc_dev), phy, reg); 331 return ETIMEDOUT; 332 } 333 334 return 0; 335 } 336 337 static void 338 alc_miibus_statchg(struct ifnet *ifp) 339 { 340 struct alc_softc *sc = ifp->if_softc; 341 struct mii_data *mii = &sc->sc_miibus; 342 uint32_t reg; 343 344 if ((ifp->if_flags & IFF_RUNNING) == 0) 345 return; 346 347 sc->alc_flags &= ~ALC_FLAG_LINK; 348 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 349 (IFM_ACTIVE | IFM_AVALID)) { 350 switch (IFM_SUBTYPE(mii->mii_media_active)) { 351 case IFM_10_T: 352 case IFM_100_TX: 353 sc->alc_flags |= ALC_FLAG_LINK; 354 break; 355 case IFM_1000_T: 356 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 357 sc->alc_flags |= ALC_FLAG_LINK; 358 break; 359 default: 360 break; 361 } 362 } 363 /* Stop Rx/Tx MACs. */ 364 alc_stop_mac(sc); 365 366 /* Program MACs with resolved speed/duplex/flow-control. */ 367 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 368 alc_start_queue(sc); 369 alc_mac_config(sc); 370 /* Re-enable Tx/Rx MACs. */ 371 reg = CSR_READ_4(sc, ALC_MAC_CFG); 372 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 373 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 374 } 375 alc_aspm(sc, 0, IFM_SUBTYPE(mii->mii_media_active)); 376 alc_dsp_fixup(sc, IFM_SUBTYPE(mii->mii_media_active)); 377 } 378 379 static int 380 alc_miidbg_readreg(struct alc_softc *sc, int reg, uint16_t *val) 381 { 382 int rv; 383 384 *val = 0; 385 386 rv = alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 387 reg); 388 if (rv != 0) 389 return rv; 390 391 return (alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 392 ALC_MII_DBG_DATA, val)); 393 } 394 395 static int 396 alc_miidbg_writereg(struct alc_softc *sc, int reg, uint16_t val) 397 { 398 int rv; 399 400 rv = alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 401 reg); 402 if (rv != 0) 403 return rv; 404 405 rv = alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 406 val); 407 408 return rv; 409 } 410 411 static int 412 alc_miiext_readreg(struct alc_softc *sc, int devaddr, int reg, uint16_t *val) 413 { 414 uint32_t clk, v; 415 int i; 416 417 *val = 0; 418 419 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 420 EXT_MDIO_DEVADDR(devaddr)); 421 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 422 clk = MDIO_CLK_25_128; 423 else 424 clk = MDIO_CLK_25_4; 425 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 426 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 427 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 428 DELAY(5); 429 v = CSR_READ_4(sc, ALC_MDIO); 430 if ((v & MDIO_OP_BUSY) == 0) 431 break; 432 } 433 434 if (i == 0) { 435 printf("%s: phy ext read timeout: %d\n", 436 device_xname(sc->sc_dev), reg); 437 return ETIMEDOUT; 438 } 439 440 *val = (v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT; 441 return 0; 442 } 443 444 static int 445 alc_miiext_writereg(struct alc_softc *sc, int devaddr, int reg, uint16_t val) 446 { 447 uint32_t clk, v; 448 int i; 449 450 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 451 EXT_MDIO_DEVADDR(devaddr)); 452 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 453 clk = MDIO_CLK_25_128; 454 else 455 clk = MDIO_CLK_25_4; 456 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 457 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | 458 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 459 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 460 DELAY(5); 461 v = CSR_READ_4(sc, ALC_MDIO); 462 if ((v & MDIO_OP_BUSY) == 0) 463 break; 464 } 465 466 if (i == 0) { 467 printf("%s: phy ext write timeout: reg %d\n", 468 device_xname(sc->sc_dev), reg); 469 return ETIMEDOUT; 470 } 471 472 return 0; 473 } 474 475 static void 476 alc_dsp_fixup(struct alc_softc *sc, int media) 477 { 478 uint16_t agc, len, val; 479 480 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 481 return; 482 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_C0) 483 return; 484 485 /* 486 * Vendor PHY magic. 487 * 1000BT/AZ, wrong cable length 488 */ 489 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 490 alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL6, &len); 491 len = (len >> EXT_CLDCTL6_CAB_LEN_SHIFT) & 492 EXT_CLDCTL6_CAB_LEN_MASK; 493 /* XXX: used to be (alc >> shift) & mask which is 0 */ 494 alc_miidbg_readreg(sc, MII_DBG_AGC, &agc); 495 agc &= DBG_AGC_2_VGA_MASK; 496 agc >>= DBG_AGC_2_VGA_SHIFT; 497 if ((media == IFM_1000_T && len > EXT_CLDCTL6_CAB_LEN_SHORT1G && 498 agc > DBG_AGC_LONG1G_LIMT) || 499 (media == IFM_100_TX && len > DBG_AGC_LONG100M_LIMT && 500 agc > DBG_AGC_LONG1G_LIMT)) { 501 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 502 DBG_AZ_ANADECT_LONG); 503 alc_miiext_readreg(sc, MII_EXT_ANEG, 504 MII_EXT_ANEG_AFE, &val); 505 val |= ANEG_AFEE_10BT_100M_TH; 506 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 507 val); 508 } else { 509 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 510 DBG_AZ_ANADECT_DEFAULT); 511 alc_miiext_readreg(sc, MII_EXT_ANEG, 512 MII_EXT_ANEG_AFE, &val); 513 val &= ~ANEG_AFEE_10BT_100M_TH; 514 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 515 val); 516 } 517 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 518 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 519 if (media == IFM_1000_T) { 520 /* 521 * Giga link threshold, raise the tolerance of 522 * noise 50%. 523 */ 524 alc_miidbg_readreg(sc, MII_DBG_MSE20DB, &val); 525 val &= ~DBG_MSE20DB_TH_MASK; 526 val |= (DBG_MSE20DB_TH_HI << 527 DBG_MSE20DB_TH_SHIFT); 528 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 529 } else if (media == IFM_100_TX) 530 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 531 DBG_MSE16DB_UP); 532 } 533 } else { 534 alc_miiext_readreg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, &val); 535 val &= ~ANEG_AFEE_10BT_100M_TH; 536 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, val); 537 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 538 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 539 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 540 DBG_MSE16DB_DOWN); 541 alc_miidbg_readreg(sc, MII_DBG_MSE20DB, &val); 542 val &= ~DBG_MSE20DB_TH_MASK; 543 val |= (DBG_MSE20DB_TH_DEFAULT << DBG_MSE20DB_TH_SHIFT); 544 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 545 } 546 } 547 } 548 549 static void 550 alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 551 { 552 struct alc_softc *sc = ifp->if_softc; 553 struct mii_data *mii = &sc->sc_miibus; 554 555 if ((ifp->if_flags & IFF_UP) == 0) 556 return; 557 558 mii_pollstat(mii); 559 ifmr->ifm_status = mii->mii_media_status; 560 ifmr->ifm_active = mii->mii_media_active; 561 } 562 563 static int 564 alc_mediachange(struct ifnet *ifp) 565 { 566 struct alc_softc *sc = ifp->if_softc; 567 struct mii_data *mii = &sc->sc_miibus; 568 int error; 569 570 if (mii->mii_instance != 0) { 571 struct mii_softc *miisc; 572 573 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 574 mii_phy_reset(miisc); 575 } 576 error = mii_mediachg(mii); 577 578 return (error); 579 } 580 581 static const struct alc_ident * 582 alc_find_ident(struct pci_attach_args *pa) 583 { 584 const struct alc_ident *ident; 585 uint16_t vendor, devid; 586 587 vendor = PCI_VENDOR(pa->pa_id); 588 devid = PCI_PRODUCT(pa->pa_id); 589 for (ident = alc_ident_table; ident->name != NULL; ident++) { 590 if (vendor == ident->vendorid && devid == ident->deviceid) 591 return (ident); 592 } 593 594 return (NULL); 595 } 596 597 static int 598 alc_match(device_t dev, cfdata_t match, void *aux) 599 { 600 struct pci_attach_args *pa = aux; 601 602 return alc_find_ident(pa) != NULL; 603 } 604 605 static void 606 alc_get_macaddr(struct alc_softc *sc) 607 { 608 609 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 610 alc_get_macaddr_816x(sc); 611 else 612 alc_get_macaddr_813x(sc); 613 } 614 615 static void 616 alc_get_macaddr_813x(struct alc_softc *sc) 617 { 618 uint32_t opt; 619 uint16_t val; 620 int eeprom, i; 621 622 eeprom = 0; 623 opt = CSR_READ_4(sc, ALC_OPT_CFG); 624 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && 625 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 626 /* 627 * EEPROM found, let TWSI reload EEPROM configuration. 628 * This will set ethernet address of controller. 629 */ 630 eeprom++; 631 switch (sc->alc_ident->deviceid) { 632 case PCI_PRODUCT_ATTANSIC_AR8131: 633 case PCI_PRODUCT_ATTANSIC_AR8132: 634 if ((opt & OPT_CFG_CLK_ENB) == 0) { 635 opt |= OPT_CFG_CLK_ENB; 636 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 637 CSR_READ_4(sc, ALC_OPT_CFG); 638 DELAY(1000); 639 } 640 break; 641 case PCI_PRODUCT_ATTANSIC_AR8151: 642 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 643 case PCI_PRODUCT_ATTANSIC_AR8152_B: 644 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 645 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 646 ALC_MII_DBG_ADDR, 0x00); 647 alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 648 ALC_MII_DBG_DATA, &val); 649 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 650 ALC_MII_DBG_DATA, val & 0xFF7F); 651 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 652 ALC_MII_DBG_ADDR, 0x3B); 653 alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 654 ALC_MII_DBG_DATA, &val); 655 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 656 ALC_MII_DBG_DATA, val | 0x0008); 657 DELAY(20); 658 break; 659 } 660 661 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 662 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 663 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 664 CSR_READ_4(sc, ALC_WOL_CFG); 665 666 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 667 TWSI_CFG_SW_LD_START); 668 for (i = 100; i > 0; i--) { 669 DELAY(1000); 670 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 671 TWSI_CFG_SW_LD_START) == 0) 672 break; 673 } 674 if (i == 0) 675 printf("%s: reloading EEPROM timeout!\n", 676 device_xname(sc->sc_dev)); 677 } else { 678 if (alcdebug) 679 printf("%s: EEPROM not found!\n", device_xname(sc->sc_dev)); 680 } 681 if (eeprom != 0) { 682 switch (sc->alc_ident->deviceid) { 683 case PCI_PRODUCT_ATTANSIC_AR8131: 684 case PCI_PRODUCT_ATTANSIC_AR8132: 685 if ((opt & OPT_CFG_CLK_ENB) != 0) { 686 opt &= ~OPT_CFG_CLK_ENB; 687 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 688 CSR_READ_4(sc, ALC_OPT_CFG); 689 DELAY(1000); 690 } 691 break; 692 case PCI_PRODUCT_ATTANSIC_AR8151: 693 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 694 case PCI_PRODUCT_ATTANSIC_AR8152_B: 695 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 696 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 697 ALC_MII_DBG_ADDR, 0x00); 698 alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 699 ALC_MII_DBG_DATA, &val); 700 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 701 ALC_MII_DBG_DATA, val | 0x0080); 702 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 703 ALC_MII_DBG_ADDR, 0x3B); 704 alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 705 ALC_MII_DBG_DATA, &val); 706 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 707 ALC_MII_DBG_DATA, val & 0xFFF7); 708 DELAY(20); 709 break; 710 } 711 } 712 713 alc_get_macaddr_par(sc); 714 } 715 716 static void 717 alc_get_macaddr_816x(struct alc_softc *sc) 718 { 719 uint32_t reg; 720 int i, reloaded; 721 722 reloaded = 0; 723 /* Try to reload station address via TWSI. */ 724 for (i = 100; i > 0; i--) { 725 reg = CSR_READ_4(sc, ALC_SLD); 726 if ((reg & (SLD_PROGRESS | SLD_START)) == 0) 727 break; 728 DELAY(1000); 729 } 730 if (i != 0) { 731 CSR_WRITE_4(sc, ALC_SLD, reg | SLD_START); 732 for (i = 100; i > 0; i--) { 733 DELAY(1000); 734 reg = CSR_READ_4(sc, ALC_SLD); 735 if ((reg & SLD_START) == 0) 736 break; 737 } 738 if (i != 0) 739 reloaded++; 740 else if (alcdebug) 741 printf("%s: reloading station address via TWSI timed out!\n", 742 device_xname(sc->sc_dev)); 743 } 744 745 /* Try to reload station address from EEPROM or FLASH. */ 746 if (reloaded == 0) { 747 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 748 if ((reg & (EEPROM_LD_EEPROM_EXIST | 749 EEPROM_LD_FLASH_EXIST)) != 0) { 750 for (i = 100; i > 0; i--) { 751 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 752 if ((reg & (EEPROM_LD_PROGRESS | 753 EEPROM_LD_START)) == 0) 754 break; 755 DELAY(1000); 756 } 757 if (i != 0) { 758 CSR_WRITE_4(sc, ALC_EEPROM_LD, reg | 759 EEPROM_LD_START); 760 for (i = 100; i > 0; i--) { 761 DELAY(1000); 762 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 763 if ((reg & EEPROM_LD_START) == 0) 764 break; 765 } 766 } else if (alcdebug) 767 printf("%s: reloading EEPROM/FLASH timed out!\n", 768 device_xname(sc->sc_dev)); 769 } 770 } 771 772 alc_get_macaddr_par(sc); 773 } 774 775 static void 776 alc_get_macaddr_par(struct alc_softc *sc) 777 { 778 uint32_t ea[2]; 779 780 ea[0] = CSR_READ_4(sc, ALC_PAR0); 781 ea[1] = CSR_READ_4(sc, ALC_PAR1); 782 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 783 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 784 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 785 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 786 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 787 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 788 } 789 790 static void 791 alc_disable_l0s_l1(struct alc_softc *sc) 792 { 793 uint32_t pmcfg; 794 795 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 796 /* Another magic from vendor. */ 797 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 798 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 799 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 800 PM_CFG_MAC_ASPM_CHK | PM_CFG_SERDES_PD_EX_L1); 801 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | 802 PM_CFG_SERDES_PLL_L1_ENB | PM_CFG_SERDES_L1_ENB; 803 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 804 } 805 } 806 807 static void 808 alc_phy_reset(struct alc_softc *sc) 809 { 810 811 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 812 alc_phy_reset_816x(sc); 813 else 814 alc_phy_reset_813x(sc); 815 } 816 817 static void 818 alc_phy_reset_813x(struct alc_softc *sc) 819 { 820 uint16_t data; 821 822 /* Reset magic from Linux. */ 823 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_SEL_ANA_RESET); 824 CSR_READ_2(sc, ALC_GPHY_CFG); 825 DELAY(10 * 1000); 826 827 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 828 GPHY_CFG_SEL_ANA_RESET); 829 CSR_READ_2(sc, ALC_GPHY_CFG); 830 DELAY(10 * 1000); 831 832 /* DSP fixup, Vendor magic. */ 833 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B) { 834 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 835 ALC_MII_DBG_ADDR, 0x000A); 836 alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 837 ALC_MII_DBG_DATA, &data); 838 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 839 ALC_MII_DBG_DATA, data & 0xDFFF); 840 } 841 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151 || 842 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 || 843 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B || 844 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) { 845 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 846 ALC_MII_DBG_ADDR, 0x003B); 847 alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 848 ALC_MII_DBG_DATA, &data); 849 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 850 ALC_MII_DBG_DATA, data & 0xFFF7); 851 DELAY(20 * 1000); 852 } 853 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151) { 854 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 855 ALC_MII_DBG_ADDR, 0x0029); 856 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 857 ALC_MII_DBG_DATA, 0x929D); 858 } 859 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8131 || 860 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8132 || 861 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 || 862 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) { 863 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 864 ALC_MII_DBG_ADDR, 0x0029); 865 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 866 ALC_MII_DBG_DATA, 0xB6DD); 867 } 868 869 /* Load DSP codes, vendor magic. */ 870 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 871 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 872 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 873 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 874 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 875 ALC_MII_DBG_DATA, data); 876 877 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 878 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 879 ANA_SERDES_EN_LCKDT; 880 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 881 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 882 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 883 ALC_MII_DBG_DATA, data); 884 885 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 886 ANA_LONG_CABLE_TH_100_MASK) | 887 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 888 ANA_SHORT_CABLE_TH_100_SHIFT) | 889 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 890 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 891 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 892 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 893 ALC_MII_DBG_DATA, data); 894 895 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 896 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 897 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 898 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 899 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 900 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 901 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 902 ALC_MII_DBG_DATA, data); 903 904 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 905 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 906 ANA_OEN_125M; 907 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 908 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 909 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 910 ALC_MII_DBG_DATA, data); 911 DELAY(1000); 912 913 /* Disable hibernation. */ 914 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 915 0x0029); 916 alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 917 ALC_MII_DBG_DATA, &data); 918 data &= ~0x8000; 919 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 920 data); 921 922 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 923 0x000B); 924 alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 925 ALC_MII_DBG_DATA, &data); 926 data &= ~0x8000; 927 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 928 data); 929 } 930 931 static void 932 alc_phy_reset_816x(struct alc_softc *sc) 933 { 934 uint32_t val; 935 uint16_t phyval; 936 937 val = CSR_READ_4(sc, ALC_GPHY_CFG); 938 val &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 939 GPHY_CFG_GATE_25M_ENB | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PHY_PLL_ON | 940 GPHY_CFG_PWDOWN_HW | GPHY_CFG_100AB_ENB); 941 val |= GPHY_CFG_SEL_ANA_RESET; 942 #ifdef notyet 943 val |= GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN | GPHY_CFG_SEL_ANA_RESET; 944 #else 945 /* Disable PHY hibernation. */ 946 val &= ~(GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN); 947 #endif 948 CSR_WRITE_4(sc, ALC_GPHY_CFG, val); 949 DELAY(10); 950 CSR_WRITE_4(sc, ALC_GPHY_CFG, val | GPHY_CFG_EXT_RESET); 951 DELAY(800); 952 953 /* Vendor PHY magic. */ 954 #ifdef notyet 955 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, DBG_LEGCYPS_DEFAULT); 956 alc_miidbg_writereg(sc, MII_DBG_SYSMODCTL, DBG_SYSMODCTL_DEFAULT); 957 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_VDRVBIAS, 958 EXT_VDRVBIAS_DEFAULT); 959 #else 960 /* Disable PHY hibernation. */ 961 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, 962 DBG_LEGCYPS_DEFAULT & ~DBG_LEGCYPS_ENB); 963 alc_miidbg_writereg(sc, MII_DBG_HIBNEG, 964 DBG_HIBNEG_DEFAULT & ~(DBG_HIBNEG_PSHIB_EN | DBG_HIBNEG_HIB_PULSE)); 965 alc_miidbg_writereg(sc, MII_DBG_GREENCFG, DBG_GREENCFG_DEFAULT); 966 #endif 967 968 /* XXX Disable EEE. */ 969 val = CSR_READ_4(sc, ALC_LPI_CTL); 970 val &= ~LPI_CTL_ENB; 971 CSR_WRITE_4(sc, ALC_LPI_CTL, val); 972 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_LOCAL_EEEADV, 0); 973 974 /* PHY power saving. */ 975 alc_miidbg_writereg(sc, MII_DBG_TST10BTCFG, DBG_TST10BTCFG_DEFAULT); 976 alc_miidbg_writereg(sc, MII_DBG_SRDSYSMOD, DBG_SRDSYSMOD_DEFAULT); 977 alc_miidbg_writereg(sc, MII_DBG_TST100BTCFG, DBG_TST100BTCFG_DEFAULT); 978 alc_miidbg_writereg(sc, MII_DBG_ANACTL, DBG_ANACTL_DEFAULT); 979 alc_miidbg_readreg(sc, MII_DBG_GREENCFG2, &phyval); 980 phyval &= ~DBG_GREENCFG2_GATE_DFSE_EN; 981 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, phyval); 982 983 /* RTL8139C, 120m issue. */ 984 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_NLP78, 985 ANEG_NLP78_120M_DEFAULT); 986 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, 987 ANEG_S3DIG10_DEFAULT); 988 989 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0) { 990 /* Turn off half amplitude. */ 991 alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3, &phyval); 992 phyval |= EXT_CLDCTL3_BP_CABLE1TH_DET_GT; 993 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3, phyval); 994 /* Turn off Green feature. */ 995 alc_miidbg_readreg(sc, MII_DBG_GREENCFG2, &phyval); 996 phyval |= DBG_GREENCFG2_BP_GREEN; 997 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, phyval); 998 /* Turn off half bias. */ 999 alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5, &phyval); 1000 val |= EXT_CLDCTL5_BP_VD_HLFBIAS; 1001 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5, phyval); 1002 } 1003 } 1004 1005 static void 1006 alc_phy_down(struct alc_softc *sc) 1007 { 1008 uint32_t gphy; 1009 1010 switch (sc->alc_ident->deviceid) { 1011 case PCI_PRODUCT_ATTANSIC_AR8161: 1012 case PCI_PRODUCT_ATTANSIC_E2200: 1013 case PCI_PRODUCT_ATTANSIC_E2400: 1014 case PCI_PRODUCT_ATTANSIC_E2500: 1015 case PCI_PRODUCT_ATTANSIC_AR8162: 1016 case PCI_PRODUCT_ATTANSIC_AR8171: 1017 case PCI_PRODUCT_ATTANSIC_AR8172: 1018 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); 1019 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 1020 GPHY_CFG_100AB_ENB | GPHY_CFG_PHY_PLL_ON); 1021 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 1022 GPHY_CFG_SEL_ANA_RESET; 1023 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; 1024 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); 1025 break; 1026 case PCI_PRODUCT_ATTANSIC_AR8151: 1027 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 1028 case PCI_PRODUCT_ATTANSIC_AR8152_B: 1029 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 1030 /* 1031 * GPHY power down caused more problems on AR8151 v2.0. 1032 * When driver is reloaded after GPHY power down, 1033 * accesses to PHY/MAC registers hung the system. Only 1034 * cold boot recovered from it. I'm not sure whether 1035 * AR8151 v1.0 also requires this one though. I don't 1036 * have AR8151 v1.0 controller in hand. 1037 * The only option left is to isolate the PHY and 1038 * initiates power down the PHY which in turn saves 1039 * more power when driver is unloaded. 1040 */ 1041 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 1042 MII_BMCR, BMCR_ISO | BMCR_PDOWN); 1043 break; 1044 default: 1045 /* Force PHY down. */ 1046 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 1047 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | 1048 GPHY_CFG_PWDOWN_HW); 1049 DELAY(1000); 1050 break; 1051 } 1052 } 1053 1054 static void 1055 alc_aspm(struct alc_softc *sc, int init, int media) 1056 { 1057 1058 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 1059 alc_aspm_816x(sc, init); 1060 else 1061 alc_aspm_813x(sc, media); 1062 } 1063 1064 static void 1065 alc_aspm_813x(struct alc_softc *sc, int media) 1066 { 1067 uint32_t pmcfg; 1068 uint16_t linkcfg; 1069 1070 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1071 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == 1072 (ALC_FLAG_APS | ALC_FLAG_PCIE)) 1073 linkcfg = CSR_READ_2(sc, sc->alc_expcap + 1074 PCIE_LCSR); 1075 else 1076 linkcfg = 0; 1077 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 1078 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK); 1079 pmcfg |= PM_CFG_MAC_ASPM_CHK; 1080 pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT); 1081 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1082 1083 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1084 /* Disable extended sync except AR8152 B v1.0 */ 1085 linkcfg &= ~0x80; 1086 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B && 1087 sc->alc_rev == ATHEROS_AR8152_B_V10) 1088 linkcfg |= 0x80; 1089 CSR_WRITE_2(sc, sc->alc_expcap + PCIE_LCSR, 1090 linkcfg); 1091 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | 1092 PM_CFG_HOTRST); 1093 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT << 1094 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1095 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1096 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT << 1097 PM_CFG_PM_REQ_TIMER_SHIFT); 1098 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV; 1099 } 1100 1101 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1102 if ((sc->alc_flags & ALC_FLAG_L0S) != 0) 1103 pmcfg |= PM_CFG_ASPM_L0S_ENB; 1104 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1105 pmcfg |= PM_CFG_ASPM_L1_ENB; 1106 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1107 if (sc->alc_ident->deviceid == 1108 PCI_PRODUCT_ATTANSIC_AR8152_B) 1109 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 1110 pmcfg &= ~(PM_CFG_SERDES_L1_ENB | 1111 PM_CFG_SERDES_PLL_L1_ENB | 1112 PM_CFG_SERDES_BUDS_RX_L1_ENB); 1113 pmcfg |= PM_CFG_CLK_SWH_L1; 1114 if (media == IFM_100_TX || media == IFM_1000_T) { 1115 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 1116 switch (sc->alc_ident->deviceid) { 1117 case PCI_PRODUCT_ATTANSIC_AR8152_B: 1118 pmcfg |= (7 << 1119 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1120 break; 1121 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 1122 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 1123 pmcfg |= (4 << 1124 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1125 break; 1126 default: 1127 pmcfg |= (15 << 1128 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1129 break; 1130 } 1131 } 1132 } else { 1133 pmcfg |= PM_CFG_SERDES_L1_ENB | 1134 PM_CFG_SERDES_PLL_L1_ENB | 1135 PM_CFG_SERDES_BUDS_RX_L1_ENB; 1136 pmcfg &= ~(PM_CFG_CLK_SWH_L1 | 1137 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1138 } 1139 } else { 1140 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB | 1141 PM_CFG_SERDES_PLL_L1_ENB); 1142 pmcfg |= PM_CFG_CLK_SWH_L1; 1143 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1144 pmcfg |= PM_CFG_ASPM_L1_ENB; 1145 } 1146 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1147 } 1148 1149 static void 1150 alc_aspm_816x(struct alc_softc *sc, int init) 1151 { 1152 uint32_t pmcfg; 1153 1154 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1155 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_816X_MASK; 1156 pmcfg |= PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT; 1157 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1158 pmcfg |= PM_CFG_PM_REQ_TIMER_816X_DEFAULT; 1159 pmcfg &= ~PM_CFG_LCKDET_TIMER_MASK; 1160 pmcfg |= PM_CFG_LCKDET_TIMER_DEFAULT; 1161 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_CLK_SWH_L1 | PM_CFG_PCIE_RECV; 1162 pmcfg &= ~(PM_CFG_RX_L1_AFTER_L0S | PM_CFG_TX_L1_AFTER_L0S | 1163 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB | 1164 PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 1165 PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SA_DLY_ENB | 1166 PM_CFG_MAC_ASPM_CHK | PM_CFG_HOTRST); 1167 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1168 (sc->alc_rev & 0x01) != 0) 1169 pmcfg |= PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB; 1170 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1171 /* Link up, enable both L0s, L1s. */ 1172 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1173 PM_CFG_MAC_ASPM_CHK; 1174 } else { 1175 if (init != 0) 1176 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1177 PM_CFG_MAC_ASPM_CHK; 1178 else if ((sc->sc_ec.ec_if.if_flags & IFF_RUNNING) != 0) 1179 pmcfg |= PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK; 1180 } 1181 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1182 } 1183 1184 static void 1185 alc_init_pcie(struct alc_softc *sc) 1186 { 1187 const char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; 1188 uint32_t cap, ctl, val; 1189 int state; 1190 1191 /* Clear data link and flow-control protocol error. */ 1192 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 1193 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 1194 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 1195 1196 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1197 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 1198 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 1199 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, 1200 CSR_READ_4(sc, ALC_PCIE_PHYMISC) | 1201 PCIE_PHYMISC_FORCE_RCV_DET); 1202 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B && 1203 sc->alc_rev == ATHEROS_AR8152_B_V10) { 1204 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); 1205 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | 1206 PCIE_PHYMISC2_SERDES_TH_MASK); 1207 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; 1208 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; 1209 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); 1210 } 1211 /* Disable ASPM L0S and L1. */ 1212 cap = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 1213 sc->alc_expcap + PCIE_LCAP) >> 16; 1214 if ((cap & PCIE_LCAP_ASPM) != 0) { 1215 ctl = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 1216 sc->alc_expcap + PCIE_LCSR) >> 16; 1217 if ((ctl & 0x08) != 0) 1218 sc->alc_rcb = DMA_CFG_RCB_128; 1219 if (alcdebug) 1220 printf("%s: RCB %u bytes\n", 1221 device_xname(sc->sc_dev), 1222 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 1223 state = ctl & 0x03; 1224 if (state & 0x01) 1225 sc->alc_flags |= ALC_FLAG_L0S; 1226 if (state & 0x02) 1227 sc->alc_flags |= ALC_FLAG_L1S; 1228 if (alcdebug) 1229 printf("%s: ASPM %s %s\n", 1230 device_xname(sc->sc_dev), 1231 aspm_state[state], 1232 state == 0 ? "disabled" : "enabled"); 1233 alc_disable_l0s_l1(sc); 1234 } else { 1235 aprint_debug_dev(sc->sc_dev, "no ASPM support\n"); 1236 } 1237 } else { 1238 val = CSR_READ_4(sc, ALC_PDLL_TRNS1); 1239 val &= ~PDLL_TRNS1_D3PLLOFF_ENB; 1240 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, val); 1241 val = CSR_READ_4(sc, ALC_MASTER_CFG); 1242 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1243 (sc->alc_rev & 0x01) != 0) { 1244 if ((val & MASTER_WAKEN_25M) == 0 || 1245 (val & MASTER_CLK_SEL_DIS) == 0) { 1246 val |= MASTER_WAKEN_25M | MASTER_CLK_SEL_DIS; 1247 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1248 } 1249 } else { 1250 if ((val & MASTER_WAKEN_25M) == 0 || 1251 (val & MASTER_CLK_SEL_DIS) != 0) { 1252 val |= MASTER_WAKEN_25M; 1253 val &= ~MASTER_CLK_SEL_DIS; 1254 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1255 } 1256 } 1257 } 1258 alc_aspm(sc, 1, IFM_UNKNOWN); 1259 } 1260 1261 static void 1262 alc_attach(device_t parent, device_t self, void *aux) 1263 { 1264 1265 struct alc_softc *sc = device_private(self); 1266 struct pci_attach_args *pa = aux; 1267 pci_chipset_tag_t pc = pa->pa_pc; 1268 pci_intr_handle_t ih; 1269 const char *intrstr; 1270 struct ifnet *ifp; 1271 struct mii_data * const mii = &sc->sc_miibus; 1272 pcireg_t memtype; 1273 uint16_t burst; 1274 int base, mii_flags, error = 0; 1275 char intrbuf[PCI_INTRSTR_LEN]; 1276 1277 sc->alc_ident = alc_find_ident(pa); 1278 sc->alc_rev = PCI_REVISION(pa->pa_class); 1279 1280 aprint_naive("\n"); 1281 aprint_normal(": %s\n", sc->alc_ident->name); 1282 1283 sc->sc_dev = self; 1284 sc->sc_pct = pa->pa_pc; 1285 sc->sc_pcitag = pa->pa_tag; 1286 1287 if (pci_dma64_available(pa)) 1288 sc->sc_dmat = pa->pa_dmat64; 1289 else 1290 sc->sc_dmat = pa->pa_dmat; 1291 1292 /* 1293 * Allocate IO memory 1294 */ 1295 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, ALC_PCIR_BAR); 1296 switch (memtype) { 1297 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1298 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M: 1299 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1300 break; 1301 default: 1302 aprint_error_dev(self, "invalid base address register\n"); 1303 break; 1304 } 1305 1306 if (pci_mapreg_map(pa, ALC_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 1307 &sc->sc_mem_bh, NULL, &sc->sc_mem_size)) { 1308 aprint_error_dev(self, "could not map mem space\n"); 1309 return; 1310 } 1311 1312 if (pci_intr_map(pa, &ih) != 0) { 1313 printf(": can't map interrupt\n"); 1314 goto fail; 1315 } 1316 1317 /* 1318 * Allocate IRQ 1319 */ 1320 intrstr = pci_intr_string(sc->sc_pct, ih, intrbuf, sizeof(intrbuf)); 1321 sc->sc_irq_handle = pci_intr_establish_xname(pc, ih, IPL_NET, alc_intr, 1322 sc, device_xname(self)); 1323 if (sc->sc_irq_handle == NULL) { 1324 printf(": could not establish interrupt"); 1325 if (intrstr != NULL) 1326 printf(" at %s", intrstr); 1327 printf("\n"); 1328 goto fail; 1329 } 1330 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 1331 1332 /* Set PHY address. */ 1333 sc->alc_phyaddr = ALC_PHY_ADDR; 1334 1335 /* Initialize DMA parameters. */ 1336 sc->alc_dma_rd_burst = 0; 1337 sc->alc_dma_wr_burst = 0; 1338 sc->alc_rcb = DMA_CFG_RCB_64; 1339 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, 1340 &base, NULL)) { 1341 sc->alc_flags |= ALC_FLAG_PCIE; 1342 sc->alc_expcap = base; 1343 burst = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 1344 base + PCIE_DCSR) >> 16; 1345 sc->alc_dma_rd_burst = (burst & 0x7000) >> 12; 1346 sc->alc_dma_wr_burst = (burst & 0x00e0) >> 5; 1347 if (alcdebug) { 1348 printf("%s: Read request size : %u bytes.\n", 1349 device_xname(sc->sc_dev), 1350 alc_dma_burst[sc->alc_dma_rd_burst]); 1351 printf("%s: TLP payload size : %u bytes.\n", 1352 device_xname(sc->sc_dev), 1353 alc_dma_burst[sc->alc_dma_wr_burst]); 1354 } 1355 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024) 1356 sc->alc_dma_rd_burst = 3; 1357 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024) 1358 sc->alc_dma_wr_burst = 3; 1359 /* 1360 * Force maximum payload size to 128 bytes for 1361 * E2200/E2400/E2500. 1362 * Otherwise it triggers DMA write error. 1363 */ 1364 if ((sc->alc_flags & ALC_FLAG_E2X00) != 0) 1365 sc->alc_dma_wr_burst = 0; 1366 alc_init_pcie(sc); 1367 } 1368 1369 /* Reset PHY. */ 1370 alc_phy_reset(sc); 1371 1372 /* Reset the ethernet controller. */ 1373 alc_stop_mac(sc); 1374 alc_reset(sc); 1375 1376 /* 1377 * One odd thing is AR8132 uses the same PHY hardware(F1 1378 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 1379 * the PHY supports 1000Mbps but that's not true. The PHY 1380 * used in AR8132 can't establish gigabit link even if it 1381 * shows the same PHY model/revision number of AR8131. 1382 */ 1383 switch (sc->alc_ident->deviceid) { 1384 case PCI_PRODUCT_ATTANSIC_E2200: 1385 case PCI_PRODUCT_ATTANSIC_E2400: 1386 case PCI_PRODUCT_ATTANSIC_E2500: 1387 sc->alc_flags |= ALC_FLAG_E2X00; 1388 /* FALLTHROUGH */ 1389 case PCI_PRODUCT_ATTANSIC_AR8161: 1390 if (PCI_SUBSYS_ID(pci_conf_read( 1391 sc->sc_pct, sc->sc_pcitag, PCI_SUBSYS_ID_REG)) == 0x0091 && 1392 sc->alc_rev == 0) 1393 sc->alc_flags |= ALC_FLAG_LINK_WAR; 1394 /* FALLTHROUGH */ 1395 case PCI_PRODUCT_ATTANSIC_AR8171: 1396 sc->alc_flags |= ALC_FLAG_AR816X_FAMILY; 1397 break; 1398 case PCI_PRODUCT_ATTANSIC_AR8162: 1399 case PCI_PRODUCT_ATTANSIC_AR8172: 1400 sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_AR816X_FAMILY; 1401 break; 1402 case PCI_PRODUCT_ATTANSIC_AR8152_B: 1403 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 1404 sc->alc_flags |= ALC_FLAG_APS; 1405 /* FALLTHROUGH */ 1406 case PCI_PRODUCT_ATTANSIC_AR8132: 1407 sc->alc_flags |= ALC_FLAG_FASTETHER; 1408 break; 1409 case PCI_PRODUCT_ATTANSIC_AR8151: 1410 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 1411 sc->alc_flags |= ALC_FLAG_APS; 1412 /* FALLTHROUGH */ 1413 default: 1414 break; 1415 } 1416 sc->alc_flags |= ALC_FLAG_JUMBO; 1417 1418 /* 1419 * It seems that AR813x/AR815x has silicon bug for SMB. In 1420 * addition, Atheros said that enabling SMB wouldn't improve 1421 * performance. However I think it's bad to access lots of 1422 * registers to extract MAC statistics. 1423 */ 1424 sc->alc_flags |= ALC_FLAG_SMB_BUG; 1425 /* 1426 * Don't use Tx CMB. It is known to have silicon bug. 1427 */ 1428 sc->alc_flags |= ALC_FLAG_CMB_BUG; 1429 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 1430 MASTER_CHIP_REV_SHIFT; 1431 if (alcdebug) { 1432 printf("%s: PCI device revision : 0x%04x\n", 1433 device_xname(sc->sc_dev), sc->alc_rev); 1434 printf("%s: Chip id/revision : 0x%04x\n", 1435 device_xname(sc->sc_dev), sc->alc_chip_rev); 1436 printf("%s: %u Tx FIFO, %u Rx FIFO\n", device_xname(sc->sc_dev), 1437 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 1438 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 1439 } 1440 1441 error = alc_dma_alloc(sc); 1442 if (error) 1443 goto fail; 1444 1445 callout_init(&sc->sc_tick_ch, 0); 1446 callout_setfunc(&sc->sc_tick_ch, alc_tick, sc); 1447 1448 /* Load station address. */ 1449 alc_get_macaddr(sc); 1450 1451 aprint_normal_dev(self, "Ethernet address %s\n", 1452 ether_sprintf(sc->alc_eaddr)); 1453 1454 ifp = &sc->sc_ec.ec_if; 1455 ifp->if_softc = sc; 1456 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1457 ifp->if_init = alc_init; 1458 ifp->if_ioctl = alc_ioctl; 1459 ifp->if_start = alc_start; 1460 ifp->if_stop = alc_stop; 1461 ifp->if_watchdog = alc_watchdog; 1462 IFQ_SET_MAXLEN(&ifp->if_snd, ALC_TX_RING_CNT - 1); 1463 IFQ_SET_READY(&ifp->if_snd); 1464 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 1465 1466 sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 1467 1468 #ifdef ALC_CHECKSUM 1469 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1470 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1471 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1472 #endif 1473 1474 #if NVLAN > 0 1475 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 1476 sc->sc_ec.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 1477 #endif 1478 1479 /* 1480 * XXX 1481 * It seems enabling Tx checksum offloading makes more trouble. 1482 * Sometimes the controller does not receive any frames when 1483 * Tx checksum offloading is enabled. I'm not sure whether this 1484 * is a bug in Tx checksum offloading logic or I got broken 1485 * sample boards. To safety, don't enable Tx checksum offloading 1486 * by default but give chance to users to toggle it if they know 1487 * their controllers work without problems. 1488 * Fortunately, Tx checksum offloading for AR816x family 1489 * seems to work. 1490 */ 1491 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1492 ifp->if_capenable &= ~IFCAP_CSUM_IPv4_Tx; 1493 ifp->if_capabilities &= ~ALC_CSUM_FEATURES; 1494 } 1495 1496 /* Set up MII bus. */ 1497 mii->mii_ifp = ifp; 1498 mii->mii_readreg = alc_miibus_readreg; 1499 mii->mii_writereg = alc_miibus_writereg; 1500 mii->mii_statchg = alc_miibus_statchg; 1501 1502 sc->sc_ec.ec_mii = mii; 1503 ifmedia_init(&mii->mii_media, 0, alc_mediachange, alc_mediastatus); 1504 mii_flags = 0; 1505 if ((sc->alc_flags & ALC_FLAG_JUMBO) != 0) 1506 mii_flags |= MIIF_DOPAUSE; 1507 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, 1508 MII_OFFSET_ANY, mii_flags); 1509 1510 if (LIST_FIRST(&mii->mii_phys) == NULL) { 1511 printf("%s: no PHY found!\n", device_xname(sc->sc_dev)); 1512 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 1513 0, NULL); 1514 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 1515 } else 1516 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 1517 1518 if_attach(ifp); 1519 if_deferred_start_init(ifp, NULL); 1520 ether_ifattach(ifp, sc->alc_eaddr); 1521 1522 if (!pmf_device_register(self, NULL, NULL)) 1523 aprint_error_dev(self, "couldn't establish power handler\n"); 1524 else 1525 pmf_class_network_register(self, ifp); 1526 1527 return; 1528 fail: 1529 alc_dma_free(sc); 1530 if (sc->sc_irq_handle != NULL) { 1531 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 1532 sc->sc_irq_handle = NULL; 1533 } 1534 if (sc->sc_mem_size) { 1535 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 1536 sc->sc_mem_size = 0; 1537 } 1538 } 1539 1540 static int 1541 alc_detach(device_t self, int flags) 1542 { 1543 struct alc_softc *sc = device_private(self); 1544 struct ifnet *ifp = &sc->sc_ec.ec_if; 1545 int s; 1546 1547 s = splnet(); 1548 alc_stop(ifp, 0); 1549 splx(s); 1550 1551 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 1552 1553 ether_ifdetach(ifp); 1554 if_detach(ifp); 1555 alc_dma_free(sc); 1556 1557 /* Delete all remaining media. */ 1558 ifmedia_fini(&sc->sc_miibus.mii_media); 1559 1560 alc_phy_down(sc); 1561 if (sc->sc_irq_handle != NULL) { 1562 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 1563 sc->sc_irq_handle = NULL; 1564 } 1565 if (sc->sc_mem_size) { 1566 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 1567 sc->sc_mem_size = 0; 1568 } 1569 1570 return (0); 1571 } 1572 1573 static int 1574 alc_dma_alloc(struct alc_softc *sc) 1575 { 1576 struct alc_txdesc *txd; 1577 struct alc_rxdesc *rxd; 1578 int nsegs, error, i; 1579 1580 /* 1581 * Create DMA stuffs for TX ring 1582 */ 1583 error = bus_dmamap_create(sc->sc_dmat, ALC_TX_RING_SZ, 1, 1584 ALC_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_tx_ring_map); 1585 if (error) { 1586 sc->alc_cdata.alc_tx_ring_map = NULL; 1587 return (ENOBUFS); 1588 } 1589 1590 /* Allocate DMA'able memory for TX ring */ 1591 error = bus_dmamem_alloc(sc->sc_dmat, ALC_TX_RING_SZ, 1592 PAGE_SIZE, 0, &sc->alc_rdata.alc_tx_ring_seg, 1, 1593 &nsegs, BUS_DMA_NOWAIT); 1594 if (error) { 1595 printf("%s: could not allocate DMA'able memory for Tx ring.\n", 1596 device_xname(sc->sc_dev)); 1597 return error; 1598 } 1599 1600 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_tx_ring_seg, 1601 nsegs, ALC_TX_RING_SZ, (void **)&sc->alc_rdata.alc_tx_ring, 1602 BUS_DMA_NOWAIT); 1603 if (error) 1604 return (ENOBUFS); 1605 1606 /* Load the DMA map for Tx ring. */ 1607 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 1608 sc->alc_rdata.alc_tx_ring, ALC_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 1609 if (error) { 1610 printf("%s: could not load DMA'able memory for Tx ring.\n", 1611 device_xname(sc->sc_dev)); 1612 bus_dmamem_free(sc->sc_dmat, 1613 &sc->alc_rdata.alc_tx_ring_seg, 1); 1614 return error; 1615 } 1616 1617 sc->alc_rdata.alc_tx_ring_paddr = 1618 sc->alc_cdata.alc_tx_ring_map->dm_segs[0].ds_addr; 1619 1620 /* 1621 * Create DMA stuffs for RX ring 1622 */ 1623 error = bus_dmamap_create(sc->sc_dmat, ALC_RX_RING_SZ, 1, 1624 ALC_RX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rx_ring_map); 1625 if (error) 1626 return (ENOBUFS); 1627 1628 /* Allocate DMA'able memory for RX ring */ 1629 error = bus_dmamem_alloc(sc->sc_dmat, ALC_RX_RING_SZ, 1630 PAGE_SIZE, 0, &sc->alc_rdata.alc_rx_ring_seg, 1, 1631 &nsegs, BUS_DMA_NOWAIT); 1632 if (error) { 1633 printf("%s: could not allocate DMA'able memory for Rx ring.\n", 1634 device_xname(sc->sc_dev)); 1635 return error; 1636 } 1637 1638 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_rx_ring_seg, 1639 nsegs, ALC_RX_RING_SZ, (void **)&sc->alc_rdata.alc_rx_ring, 1640 BUS_DMA_NOWAIT); 1641 if (error) 1642 return (ENOBUFS); 1643 1644 /* Load the DMA map for Rx ring. */ 1645 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 1646 sc->alc_rdata.alc_rx_ring, ALC_RX_RING_SZ, NULL, BUS_DMA_WAITOK); 1647 if (error) { 1648 printf("%s: could not load DMA'able memory for Rx ring.\n", 1649 device_xname(sc->sc_dev)); 1650 bus_dmamem_free(sc->sc_dmat, 1651 &sc->alc_rdata.alc_rx_ring_seg, 1); 1652 return error; 1653 } 1654 1655 sc->alc_rdata.alc_rx_ring_paddr = 1656 sc->alc_cdata.alc_rx_ring_map->dm_segs[0].ds_addr; 1657 1658 /* 1659 * Create DMA stuffs for RX return ring 1660 */ 1661 error = bus_dmamap_create(sc->sc_dmat, ALC_RR_RING_SZ, 1, 1662 ALC_RR_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rr_ring_map); 1663 if (error) 1664 return (ENOBUFS); 1665 1666 /* Allocate DMA'able memory for RX return ring */ 1667 error = bus_dmamem_alloc(sc->sc_dmat, ALC_RR_RING_SZ, 1668 PAGE_SIZE, 0, &sc->alc_rdata.alc_rr_ring_seg, 1, 1669 &nsegs, BUS_DMA_NOWAIT); 1670 if (error) { 1671 printf("%s: could not allocate DMA'able memory for Rx " 1672 "return ring.\n", device_xname(sc->sc_dev)); 1673 return error; 1674 } 1675 1676 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_rr_ring_seg, 1677 nsegs, ALC_RR_RING_SZ, (void **)&sc->alc_rdata.alc_rr_ring, 1678 BUS_DMA_NOWAIT); 1679 if (error) 1680 return (ENOBUFS); 1681 1682 /* Load the DMA map for Rx return ring. */ 1683 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 1684 sc->alc_rdata.alc_rr_ring, ALC_RR_RING_SZ, NULL, BUS_DMA_WAITOK); 1685 if (error) { 1686 printf("%s: could not load DMA'able memory for Rx return ring." 1687 "\n", device_xname(sc->sc_dev)); 1688 bus_dmamem_free(sc->sc_dmat, 1689 &sc->alc_rdata.alc_rr_ring_seg, 1); 1690 return error; 1691 } 1692 1693 sc->alc_rdata.alc_rr_ring_paddr = 1694 sc->alc_cdata.alc_rr_ring_map->dm_segs[0].ds_addr; 1695 1696 /* 1697 * All of the memory we allocated for the Rx ring / Rx Return 1698 * ring need to be in the same 4GB segment. Make sure this is 1699 * so. 1700 * 1701 * XXX We don't care WHAT 4GB segment they're in, just that 1702 * XXX they're all in the same one. Need some bus_dma API 1703 * XXX help to make this easier to enforce when we actually 1704 * XXX perform the allocation. 1705 */ 1706 if (ALC_ADDR_HI(sc->alc_rdata.alc_rx_ring_paddr) != 1707 ALC_ADDR_HI(sc->alc_rdata.alc_rr_ring_paddr)) { 1708 aprint_error_dev(sc->sc_dev, 1709 "Rx control data allocation constraints failed\n"); 1710 return ENOBUFS; 1711 } 1712 1713 /* 1714 * Create DMA stuffs for CMB block 1715 */ 1716 error = bus_dmamap_create(sc->sc_dmat, ALC_CMB_SZ, 1, 1717 ALC_CMB_SZ, 0, BUS_DMA_NOWAIT, 1718 &sc->alc_cdata.alc_cmb_map); 1719 if (error) 1720 return (ENOBUFS); 1721 1722 /* Allocate DMA'able memory for CMB block */ 1723 error = bus_dmamem_alloc(sc->sc_dmat, ALC_CMB_SZ, 1724 PAGE_SIZE, 0, &sc->alc_rdata.alc_cmb_seg, 1, 1725 &nsegs, BUS_DMA_NOWAIT); 1726 if (error) { 1727 printf("%s: could not allocate DMA'able memory for " 1728 "CMB block\n", device_xname(sc->sc_dev)); 1729 return error; 1730 } 1731 1732 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_cmb_seg, 1733 nsegs, ALC_CMB_SZ, (void **)&sc->alc_rdata.alc_cmb, 1734 BUS_DMA_NOWAIT); 1735 if (error) 1736 return (ENOBUFS); 1737 1738 /* Load the DMA map for CMB block. */ 1739 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 1740 sc->alc_rdata.alc_cmb, ALC_CMB_SZ, NULL, 1741 BUS_DMA_WAITOK); 1742 if (error) { 1743 printf("%s: could not load DMA'able memory for CMB block\n", 1744 device_xname(sc->sc_dev)); 1745 bus_dmamem_free(sc->sc_dmat, 1746 &sc->alc_rdata.alc_cmb_seg, 1); 1747 return error; 1748 } 1749 1750 sc->alc_rdata.alc_cmb_paddr = 1751 sc->alc_cdata.alc_cmb_map->dm_segs[0].ds_addr; 1752 1753 /* 1754 * Create DMA stuffs for SMB block 1755 */ 1756 error = bus_dmamap_create(sc->sc_dmat, ALC_SMB_SZ, 1, 1757 ALC_SMB_SZ, 0, BUS_DMA_NOWAIT, 1758 &sc->alc_cdata.alc_smb_map); 1759 if (error) 1760 return (ENOBUFS); 1761 1762 /* Allocate DMA'able memory for SMB block */ 1763 error = bus_dmamem_alloc(sc->sc_dmat, ALC_SMB_SZ, 1764 PAGE_SIZE, 0, &sc->alc_rdata.alc_smb_seg, 1, 1765 &nsegs, BUS_DMA_NOWAIT); 1766 if (error) { 1767 printf("%s: could not allocate DMA'able memory for " 1768 "SMB block\n", device_xname(sc->sc_dev)); 1769 return error; 1770 } 1771 1772 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_smb_seg, 1773 nsegs, ALC_SMB_SZ, (void **)&sc->alc_rdata.alc_smb, 1774 BUS_DMA_NOWAIT); 1775 if (error) 1776 return (ENOBUFS); 1777 1778 /* Load the DMA map for SMB block */ 1779 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 1780 sc->alc_rdata.alc_smb, ALC_SMB_SZ, NULL, 1781 BUS_DMA_WAITOK); 1782 if (error) { 1783 printf("%s: could not load DMA'able memory for SMB block\n", 1784 device_xname(sc->sc_dev)); 1785 bus_dmamem_free(sc->sc_dmat, 1786 &sc->alc_rdata.alc_smb_seg, 1); 1787 return error; 1788 } 1789 1790 sc->alc_rdata.alc_smb_paddr = 1791 sc->alc_cdata.alc_smb_map->dm_segs[0].ds_addr; 1792 1793 1794 /* Create DMA maps for Tx buffers. */ 1795 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1796 txd = &sc->alc_cdata.alc_txdesc[i]; 1797 txd->tx_m = NULL; 1798 txd->tx_dmamap = NULL; 1799 error = bus_dmamap_create(sc->sc_dmat, ALC_TSO_MAXSIZE, 1800 ALC_MAXTXSEGS, ALC_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 1801 &txd->tx_dmamap); 1802 if (error) { 1803 printf("%s: could not create Tx dmamap.\n", 1804 device_xname(sc->sc_dev)); 1805 return error; 1806 } 1807 } 1808 1809 /* Create DMA maps for Rx buffers. */ 1810 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 1811 BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rx_sparemap); 1812 if (error) { 1813 printf("%s: could not create spare Rx dmamap.\n", 1814 device_xname(sc->sc_dev)); 1815 return error; 1816 } 1817 1818 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1819 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1820 rxd->rx_m = NULL; 1821 rxd->rx_dmamap = NULL; 1822 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1823 MCLBYTES, 0, BUS_DMA_NOWAIT, &rxd->rx_dmamap); 1824 if (error) { 1825 printf("%s: could not create Rx dmamap.\n", 1826 device_xname(sc->sc_dev)); 1827 return error; 1828 } 1829 } 1830 1831 return (0); 1832 } 1833 1834 static void 1835 alc_dma_free(struct alc_softc *sc) 1836 { 1837 struct alc_txdesc *txd; 1838 struct alc_rxdesc *rxd; 1839 int i; 1840 1841 /* Tx buffers */ 1842 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1843 txd = &sc->alc_cdata.alc_txdesc[i]; 1844 if (txd->tx_dmamap != NULL) { 1845 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 1846 txd->tx_dmamap = NULL; 1847 } 1848 } 1849 /* Rx buffers */ 1850 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1851 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1852 if (rxd->rx_dmamap != NULL) { 1853 bus_dmamap_destroy(sc->sc_dmat, rxd->rx_dmamap); 1854 rxd->rx_dmamap = NULL; 1855 } 1856 } 1857 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 1858 bus_dmamap_destroy(sc->sc_dmat, sc->alc_cdata.alc_rx_sparemap); 1859 sc->alc_cdata.alc_rx_sparemap = NULL; 1860 } 1861 1862 /* Tx ring. */ 1863 if (sc->alc_cdata.alc_tx_ring_map != NULL) 1864 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map); 1865 if (sc->alc_cdata.alc_tx_ring_map != NULL && 1866 sc->alc_rdata.alc_tx_ring != NULL) 1867 bus_dmamem_free(sc->sc_dmat, 1868 &sc->alc_rdata.alc_tx_ring_seg, 1); 1869 sc->alc_rdata.alc_tx_ring = NULL; 1870 sc->alc_cdata.alc_tx_ring_map = NULL; 1871 1872 /* Rx ring. */ 1873 if (sc->alc_cdata.alc_rx_ring_map != NULL) 1874 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map); 1875 if (sc->alc_cdata.alc_rx_ring_map != NULL && 1876 sc->alc_rdata.alc_rx_ring != NULL) 1877 bus_dmamem_free(sc->sc_dmat, 1878 &sc->alc_rdata.alc_rx_ring_seg, 1); 1879 sc->alc_rdata.alc_rx_ring = NULL; 1880 sc->alc_cdata.alc_rx_ring_map = NULL; 1881 1882 /* Rx return ring. */ 1883 if (sc->alc_cdata.alc_rr_ring_map != NULL) 1884 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map); 1885 if (sc->alc_cdata.alc_rr_ring_map != NULL && 1886 sc->alc_rdata.alc_rr_ring != NULL) 1887 bus_dmamem_free(sc->sc_dmat, 1888 &sc->alc_rdata.alc_rr_ring_seg, 1); 1889 sc->alc_rdata.alc_rr_ring = NULL; 1890 sc->alc_cdata.alc_rr_ring_map = NULL; 1891 1892 /* CMB block */ 1893 if (sc->alc_cdata.alc_cmb_map != NULL) 1894 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_cmb_map); 1895 if (sc->alc_cdata.alc_cmb_map != NULL && 1896 sc->alc_rdata.alc_cmb != NULL) 1897 bus_dmamem_free(sc->sc_dmat, 1898 &sc->alc_rdata.alc_cmb_seg, 1); 1899 sc->alc_rdata.alc_cmb = NULL; 1900 sc->alc_cdata.alc_cmb_map = NULL; 1901 1902 /* SMB block */ 1903 if (sc->alc_cdata.alc_smb_map != NULL) 1904 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_smb_map); 1905 if (sc->alc_cdata.alc_smb_map != NULL && 1906 sc->alc_rdata.alc_smb != NULL) 1907 bus_dmamem_free(sc->sc_dmat, 1908 &sc->alc_rdata.alc_smb_seg, 1); 1909 sc->alc_rdata.alc_smb = NULL; 1910 sc->alc_cdata.alc_smb_map = NULL; 1911 } 1912 1913 static int 1914 alc_encap(struct alc_softc *sc, struct mbuf **m_head) 1915 { 1916 struct alc_txdesc *txd, *txd_last; 1917 struct tx_desc *desc; 1918 struct mbuf *m; 1919 bus_dmamap_t map; 1920 uint32_t cflags, poff, vtag; 1921 int error, idx, nsegs, prod; 1922 1923 m = *m_head; 1924 cflags = vtag = 0; 1925 poff = 0; 1926 1927 prod = sc->alc_cdata.alc_tx_prod; 1928 txd = &sc->alc_cdata.alc_txdesc[prod]; 1929 txd_last = txd; 1930 map = txd->tx_dmamap; 1931 1932 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); 1933 1934 if (error == EFBIG) { 1935 error = 0; 1936 1937 *m_head = m_pullup(*m_head, MHLEN); 1938 if (*m_head == NULL) { 1939 printf("%s: can't defrag TX mbuf\n", 1940 device_xname(sc->sc_dev)); 1941 return ENOBUFS; 1942 } 1943 1944 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, 1945 BUS_DMA_NOWAIT); 1946 1947 if (error != 0) { 1948 printf("%s: could not load defragged TX mbuf\n", 1949 device_xname(sc->sc_dev)); 1950 m_freem(*m_head); 1951 *m_head = NULL; 1952 return error; 1953 } 1954 } else if (error) { 1955 printf("%s: could not load TX mbuf\n", device_xname(sc->sc_dev)); 1956 return (error); 1957 } 1958 1959 nsegs = map->dm_nsegs; 1960 1961 if (nsegs == 0) { 1962 m_freem(*m_head); 1963 *m_head = NULL; 1964 return (EIO); 1965 } 1966 1967 /* Check descriptor overrun. */ 1968 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) { 1969 bus_dmamap_unload(sc->sc_dmat, map); 1970 return (ENOBUFS); 1971 } 1972 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1973 BUS_DMASYNC_PREWRITE); 1974 1975 m = *m_head; 1976 desc = NULL; 1977 idx = 0; 1978 #if NVLAN > 0 1979 /* Configure VLAN hardware tag insertion. */ 1980 if (vlan_has_tag(m)) { 1981 vtag = htons(vlan_get_tag(m)); 1982 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 1983 cflags |= TD_INS_VLAN_TAG; 1984 } 1985 #endif 1986 /* Configure Tx checksum offload. */ 1987 if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 1988 cflags |= TD_CUSTOM_CSUM; 1989 /* Set checksum start offset. */ 1990 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 1991 TD_PLOAD_OFFSET_MASK; 1992 } 1993 for (; idx < nsegs; idx++) { 1994 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1995 desc->len = 1996 htole32(TX_BYTES(map->dm_segs[idx].ds_len) | vtag); 1997 desc->flags = htole32(cflags); 1998 desc->addr = htole64(map->dm_segs[idx].ds_addr); 1999 sc->alc_cdata.alc_tx_cnt++; 2000 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2001 } 2002 /* Update producer index. */ 2003 sc->alc_cdata.alc_tx_prod = prod; 2004 2005 /* Finally set EOP on the last descriptor. */ 2006 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 2007 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2008 desc->flags |= htole32(TD_EOP); 2009 2010 /* Swap dmamap of the first and the last. */ 2011 txd = &sc->alc_cdata.alc_txdesc[prod]; 2012 map = txd_last->tx_dmamap; 2013 txd_last->tx_dmamap = txd->tx_dmamap; 2014 txd->tx_dmamap = map; 2015 txd->tx_m = m; 2016 2017 return (0); 2018 } 2019 2020 static void 2021 alc_start(struct ifnet *ifp) 2022 { 2023 struct alc_softc *sc = ifp->if_softc; 2024 struct mbuf *m_head; 2025 int enq; 2026 2027 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2028 return; 2029 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) 2030 return; 2031 2032 /* Reclaim transmitted frames. */ 2033 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 2034 alc_txeof(sc); 2035 2036 enq = 0; 2037 for (;;) { 2038 IFQ_DEQUEUE(&ifp->if_snd, m_head); 2039 if (m_head == NULL) 2040 break; 2041 2042 /* 2043 * Pack the data into the transmit ring. If we 2044 * don't have room, set the OACTIVE flag and wait 2045 * for the NIC to drain the ring. 2046 */ 2047 if (alc_encap(sc, &m_head)) { 2048 if (m_head == NULL) 2049 break; 2050 ifp->if_flags |= IFF_OACTIVE; 2051 break; 2052 } 2053 enq = 1; 2054 2055 /* 2056 * If there's a BPF listener, bounce a copy of this frame 2057 * to him. 2058 */ 2059 bpf_mtap(ifp, m_head, BPF_D_OUT); 2060 } 2061 2062 if (enq) { 2063 /* Sync descriptors. */ 2064 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 2065 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, 2066 BUS_DMASYNC_PREWRITE); 2067 /* Kick. Assume we're using normal Tx priority queue. */ 2068 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 2069 (sc->alc_cdata.alc_tx_prod << 2070 MBOX_TD_PROD_LO_IDX_SHIFT) & 2071 MBOX_TD_PROD_LO_IDX_MASK); 2072 /* Set a timeout in case the chip goes out to lunch. */ 2073 ifp->if_timer = ALC_TX_TIMEOUT; 2074 } 2075 } 2076 2077 static void 2078 alc_watchdog(struct ifnet *ifp) 2079 { 2080 struct alc_softc *sc = ifp->if_softc; 2081 2082 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 2083 printf("%s: watchdog timeout (missed link)\n", 2084 device_xname(sc->sc_dev)); 2085 if_statinc(ifp, if_oerrors); 2086 alc_init_backend(ifp, false); 2087 return; 2088 } 2089 2090 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 2091 if_statinc(ifp, if_oerrors); 2092 alc_init_backend(ifp, false); 2093 alc_start(ifp); 2094 } 2095 2096 static int 2097 alc_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2098 { 2099 struct alc_softc *sc = ifp->if_softc; 2100 int s, error = 0; 2101 2102 s = splnet(); 2103 2104 switch (cmd) { 2105 case SIOCSIFADDR: 2106 error = ether_ioctl(ifp, cmd, data); 2107 ifp->if_flags |= IFF_UP; 2108 if (!(ifp->if_flags & IFF_RUNNING)) 2109 alc_init(ifp); 2110 break; 2111 2112 case SIOCSIFFLAGS: 2113 error = ether_ioctl(ifp, cmd, data); 2114 if (ifp->if_flags & IFF_UP) { 2115 if (ifp->if_flags & IFF_RUNNING) 2116 error = ENETRESET; 2117 else 2118 alc_init(ifp); 2119 } else { 2120 if (ifp->if_flags & IFF_RUNNING) 2121 alc_stop(ifp, 0); 2122 } 2123 break; 2124 2125 default: 2126 error = ether_ioctl(ifp, cmd, data); 2127 break; 2128 } 2129 2130 if (error == ENETRESET) { 2131 if (ifp->if_flags & IFF_RUNNING) 2132 alc_iff(sc); 2133 error = 0; 2134 } 2135 2136 splx(s); 2137 return (error); 2138 } 2139 2140 static void 2141 alc_mac_config(struct alc_softc *sc) 2142 { 2143 struct mii_data *mii; 2144 uint32_t reg; 2145 2146 mii = &sc->sc_miibus; 2147 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2148 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 2149 MAC_CFG_SPEED_MASK); 2150 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151 || 2151 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 || 2152 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) 2153 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 2154 /* Reprogram MAC with resolved speed/duplex. */ 2155 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2156 case IFM_10_T: 2157 case IFM_100_TX: 2158 reg |= MAC_CFG_SPEED_10_100; 2159 break; 2160 case IFM_1000_T: 2161 reg |= MAC_CFG_SPEED_1000; 2162 break; 2163 } 2164 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2165 reg |= MAC_CFG_FULL_DUPLEX; 2166 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2167 reg |= MAC_CFG_TX_FC; 2168 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2169 reg |= MAC_CFG_RX_FC; 2170 } 2171 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2172 } 2173 2174 static void 2175 alc_stats_clear(struct alc_softc *sc) 2176 { 2177 struct smb sb, *smb; 2178 uint32_t *reg; 2179 int i; 2180 2181 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2182 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2183 sc->alc_cdata.alc_smb_map->dm_mapsize, 2184 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2185 smb = sc->alc_rdata.alc_smb; 2186 /* Update done, clear. */ 2187 smb->updated = 0; 2188 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2189 sc->alc_cdata.alc_smb_map->dm_mapsize, 2190 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2191 } else { 2192 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2193 reg++) { 2194 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2195 i += sizeof(uint32_t); 2196 } 2197 /* Read Tx statistics. */ 2198 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2199 reg++) { 2200 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2201 i += sizeof(uint32_t); 2202 } 2203 } 2204 } 2205 2206 static void 2207 alc_stats_update(struct alc_softc *sc) 2208 { 2209 struct ifnet *ifp = &sc->sc_ec.ec_if; 2210 struct alc_hw_stats *stat; 2211 struct smb sb, *smb; 2212 uint32_t *reg; 2213 int i; 2214 2215 stat = &sc->alc_stats; 2216 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2217 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2218 sc->alc_cdata.alc_smb_map->dm_mapsize, 2219 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2220 smb = sc->alc_rdata.alc_smb; 2221 if (smb->updated == 0) 2222 return; 2223 } else { 2224 smb = &sb; 2225 /* Read Rx statistics. */ 2226 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2227 reg++) { 2228 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2229 i += sizeof(uint32_t); 2230 } 2231 /* Read Tx statistics. */ 2232 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2233 reg++) { 2234 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2235 i += sizeof(uint32_t); 2236 } 2237 } 2238 2239 /* Rx stats. */ 2240 stat->rx_frames += smb->rx_frames; 2241 stat->rx_bcast_frames += smb->rx_bcast_frames; 2242 stat->rx_mcast_frames += smb->rx_mcast_frames; 2243 stat->rx_pause_frames += smb->rx_pause_frames; 2244 stat->rx_control_frames += smb->rx_control_frames; 2245 stat->rx_crcerrs += smb->rx_crcerrs; 2246 stat->rx_lenerrs += smb->rx_lenerrs; 2247 stat->rx_bytes += smb->rx_bytes; 2248 stat->rx_runts += smb->rx_runts; 2249 stat->rx_fragments += smb->rx_fragments; 2250 stat->rx_pkts_64 += smb->rx_pkts_64; 2251 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2252 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2253 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2254 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2255 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2256 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2257 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2258 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2259 stat->rx_rrs_errs += smb->rx_rrs_errs; 2260 stat->rx_alignerrs += smb->rx_alignerrs; 2261 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2262 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2263 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2264 2265 /* Tx stats. */ 2266 stat->tx_frames += smb->tx_frames; 2267 stat->tx_bcast_frames += smb->tx_bcast_frames; 2268 stat->tx_mcast_frames += smb->tx_mcast_frames; 2269 stat->tx_pause_frames += smb->tx_pause_frames; 2270 stat->tx_excess_defer += smb->tx_excess_defer; 2271 stat->tx_control_frames += smb->tx_control_frames; 2272 stat->tx_deferred += smb->tx_deferred; 2273 stat->tx_bytes += smb->tx_bytes; 2274 stat->tx_pkts_64 += smb->tx_pkts_64; 2275 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2276 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2277 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2278 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2279 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2280 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2281 stat->tx_single_colls += smb->tx_single_colls; 2282 stat->tx_multi_colls += smb->tx_multi_colls; 2283 stat->tx_late_colls += smb->tx_late_colls; 2284 stat->tx_excess_colls += smb->tx_excess_colls; 2285 stat->tx_underrun += smb->tx_underrun; 2286 stat->tx_desc_underrun += smb->tx_desc_underrun; 2287 stat->tx_lenerrs += smb->tx_lenerrs; 2288 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2289 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2290 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2291 2292 /* Update counters in ifnet. */ 2293 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 2294 2295 if_statadd_ref(ifp, nsr, if_opackets, smb->tx_frames); 2296 2297 if_statadd_ref(ifp, nsr, if_collisions, 2298 smb->tx_single_colls + 2299 smb->tx_multi_colls * 2 + smb->tx_late_colls + 2300 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT); 2301 2302 if_statadd_ref(ifp, nsr, if_oerrors, 2303 smb->tx_late_colls + smb->tx_excess_colls + 2304 smb->tx_underrun + smb->tx_pkts_truncated); 2305 2306 if_statadd_ref(ifp, nsr, if_ierrors, 2307 smb->rx_crcerrs + smb->rx_lenerrs + 2308 smb->rx_runts + smb->rx_pkts_truncated + 2309 smb->rx_fifo_oflows + smb->rx_rrs_errs + 2310 smb->rx_alignerrs); 2311 2312 IF_STAT_PUTREF(ifp); 2313 2314 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2315 /* Update done, clear. */ 2316 smb->updated = 0; 2317 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2318 sc->alc_cdata.alc_smb_map->dm_mapsize, 2319 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2320 } 2321 } 2322 2323 static int 2324 alc_intr(void *arg) 2325 { 2326 struct alc_softc *sc = arg; 2327 struct ifnet *ifp = &sc->sc_ec.ec_if; 2328 uint32_t status; 2329 2330 status = CSR_READ_4(sc, ALC_INTR_STATUS); 2331 if ((status & ALC_INTRS) == 0) 2332 return (0); 2333 2334 /* Acknowledge and disable interrupts. */ 2335 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 2336 2337 if (ifp->if_flags & IFF_RUNNING) { 2338 if (status & INTR_RX_PKT) { 2339 int error; 2340 2341 error = alc_rxintr(sc); 2342 if (error) { 2343 alc_init_backend(ifp, false); 2344 return (0); 2345 } 2346 } 2347 2348 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 2349 INTR_TXQ_TO_RST)) { 2350 if (status & INTR_DMA_RD_TO_RST) 2351 printf("%s: DMA read error! -- resetting\n", 2352 device_xname(sc->sc_dev)); 2353 if (status & INTR_DMA_WR_TO_RST) 2354 printf("%s: DMA write error! -- resetting\n", 2355 device_xname(sc->sc_dev)); 2356 if (status & INTR_TXQ_TO_RST) 2357 printf("%s: TxQ reset! -- resetting\n", 2358 device_xname(sc->sc_dev)); 2359 alc_init_backend(ifp, false); 2360 return (0); 2361 } 2362 2363 alc_txeof(sc); 2364 if_schedule_deferred_start(ifp); 2365 } 2366 2367 /* Re-enable interrupts. */ 2368 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 2369 return (1); 2370 } 2371 2372 static void 2373 alc_txeof(struct alc_softc *sc) 2374 { 2375 struct ifnet *ifp = &sc->sc_ec.ec_if; 2376 struct alc_txdesc *txd; 2377 uint32_t cons, prod; 2378 int prog; 2379 2380 if (sc->alc_cdata.alc_tx_cnt == 0) 2381 return; 2382 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 2383 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, 2384 BUS_DMASYNC_POSTREAD); 2385 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 2386 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 2387 sc->alc_cdata.alc_cmb_map->dm_mapsize, 2388 BUS_DMASYNC_POSTREAD); 2389 prod = sc->alc_rdata.alc_cmb->cons; 2390 } else 2391 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 2392 /* Assume we're using normal Tx priority queue. */ 2393 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 2394 MBOX_TD_CONS_LO_IDX_SHIFT; 2395 cons = sc->alc_cdata.alc_tx_cons; 2396 /* 2397 * Go through our Tx list and free mbufs for those 2398 * frames which have been transmitted. 2399 */ 2400 for (prog = 0; cons != prod; prog++, 2401 ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 2402 if (sc->alc_cdata.alc_tx_cnt <= 0) 2403 break; 2404 prog++; 2405 ifp->if_flags &= ~IFF_OACTIVE; 2406 sc->alc_cdata.alc_tx_cnt--; 2407 txd = &sc->alc_cdata.alc_txdesc[cons]; 2408 if (txd->tx_m != NULL) { 2409 /* Reclaim transmitted mbufs. */ 2410 bus_dmamap_sync(sc->sc_dmat, txd->tx_dmamap, 0, 2411 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2412 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 2413 m_freem(txd->tx_m); 2414 txd->tx_m = NULL; 2415 } 2416 } 2417 2418 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 2419 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 2420 sc->alc_cdata.alc_cmb_map->dm_mapsize, BUS_DMASYNC_PREREAD); 2421 sc->alc_cdata.alc_tx_cons = cons; 2422 /* 2423 * Unarm watchdog timer only when there is no pending 2424 * frames in Tx queue. 2425 */ 2426 if (sc->alc_cdata.alc_tx_cnt == 0) 2427 ifp->if_timer = 0; 2428 } 2429 2430 static int 2431 alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd, bool init) 2432 { 2433 struct mbuf *m; 2434 bus_dmamap_t map; 2435 int error; 2436 2437 MGETHDR(m, init ? M_WAITOK : M_DONTWAIT, MT_DATA); 2438 if (m == NULL) 2439 return (ENOBUFS); 2440 MCLAIM(m, &sc->sc_ec.ec_rx_mowner); 2441 MCLGET(m, init ? M_WAITOK : M_DONTWAIT); 2442 if (!(m->m_flags & M_EXT)) { 2443 m_freem(m); 2444 return (ENOBUFS); 2445 } 2446 2447 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 2448 2449 error = bus_dmamap_load_mbuf(sc->sc_dmat, 2450 sc->alc_cdata.alc_rx_sparemap, m, BUS_DMA_NOWAIT); 2451 2452 if (error != 0) { 2453 m_freem(m); 2454 2455 if (init) 2456 printf("%s: can't load RX mbuf\n", device_xname(sc->sc_dev)); 2457 2458 return (error); 2459 } 2460 2461 if (rxd->rx_m != NULL) { 2462 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 2463 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2464 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 2465 } 2466 map = rxd->rx_dmamap; 2467 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 2468 sc->alc_cdata.alc_rx_sparemap = map; 2469 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, rxd->rx_dmamap->dm_mapsize, 2470 BUS_DMASYNC_PREREAD); 2471 rxd->rx_m = m; 2472 rxd->rx_desc->addr = htole64(rxd->rx_dmamap->dm_segs[0].ds_addr); 2473 return (0); 2474 } 2475 2476 static int 2477 alc_rxintr(struct alc_softc *sc) 2478 { 2479 struct ifnet *ifp = &sc->sc_ec.ec_if; 2480 struct rx_rdesc *rrd; 2481 uint32_t nsegs, status; 2482 int rr_cons, prog; 2483 2484 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 2485 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, 2486 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2487 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 2488 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, 2489 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2490 rr_cons = sc->alc_cdata.alc_rr_cons; 2491 for (prog = 0; (ifp->if_flags & IFF_RUNNING) != 0;) { 2492 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 2493 status = le32toh(rrd->status); 2494 if ((status & RRD_VALID) == 0) 2495 break; 2496 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo)); 2497 if (nsegs == 0) { 2498 /* This should not happen! */ 2499 if (alcdebug) 2500 printf("%s: unexpected segment count -- " 2501 "resetting\n", device_xname(sc->sc_dev)); 2502 return (EIO); 2503 } 2504 alc_rxeof(sc, rrd); 2505 /* Clear Rx return status. */ 2506 rrd->status = 0; 2507 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 2508 sc->alc_cdata.alc_rx_cons += nsegs; 2509 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 2510 prog += nsegs; 2511 } 2512 2513 if (prog > 0) { 2514 /* Update the consumer index. */ 2515 sc->alc_cdata.alc_rr_cons = rr_cons; 2516 /* Sync Rx return descriptors. */ 2517 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 2518 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, 2519 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2520 /* 2521 * Sync updated Rx descriptors such that controller see 2522 * modified buffer addresses. 2523 */ 2524 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 2525 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, 2526 BUS_DMASYNC_PREWRITE); 2527 /* 2528 * Let controller know availability of new Rx buffers. 2529 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 2530 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 2531 * only when Rx buffer pre-fetching is required. In 2532 * addition we already set ALC_RX_RD_FREE_THRESH to 2533 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 2534 * it still seems that pre-fetching needs more 2535 * experimentation. 2536 */ 2537 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 2538 sc->alc_cdata.alc_rx_cons); 2539 } 2540 2541 return (0); 2542 } 2543 2544 /* Receive a frame. */ 2545 static void 2546 alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 2547 { 2548 struct ifnet *ifp = &sc->sc_ec.ec_if; 2549 struct alc_rxdesc *rxd; 2550 struct mbuf *mp, *m; 2551 uint32_t rdinfo, status; 2552 int count, nsegs, rx_cons; 2553 2554 status = le32toh(rrd->status); 2555 rdinfo = le32toh(rrd->rdinfo); 2556 rx_cons = RRD_RD_IDX(rdinfo); 2557 nsegs = RRD_RD_CNT(rdinfo); 2558 2559 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 2560 if (status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) { 2561 /* 2562 * We want to pass the following frames to upper 2563 * layer regardless of error status of Rx return 2564 * ring. 2565 * 2566 * o IP/TCP/UDP checksum is bad. 2567 * o frame length and protocol specific length 2568 * does not match. 2569 * 2570 * Force network stack compute checksum for 2571 * errored frames. 2572 */ 2573 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK; 2574 if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN | 2575 RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0) 2576 return; 2577 } 2578 2579 for (count = 0; count < nsegs; count++, 2580 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 2581 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 2582 mp = rxd->rx_m; 2583 /* Add a new receive buffer to the ring. */ 2584 if (alc_newbuf(sc, rxd, false) != 0) { 2585 if_statinc(ifp, if_iqdrops); 2586 /* Reuse Rx buffers. */ 2587 m_freem(sc->alc_cdata.alc_rxhead); 2588 break; 2589 } 2590 2591 /* 2592 * Assume we've received a full sized frame. 2593 * Actual size is fixed when we encounter the end of 2594 * multi-segmented frame. 2595 */ 2596 mp->m_len = sc->alc_buf_size; 2597 2598 /* Chain received mbufs. */ 2599 if (sc->alc_cdata.alc_rxhead == NULL) { 2600 sc->alc_cdata.alc_rxhead = mp; 2601 sc->alc_cdata.alc_rxtail = mp; 2602 } else { 2603 m_remove_pkthdr(mp); 2604 sc->alc_cdata.alc_rxprev_tail = 2605 sc->alc_cdata.alc_rxtail; 2606 sc->alc_cdata.alc_rxtail->m_next = mp; 2607 sc->alc_cdata.alc_rxtail = mp; 2608 } 2609 2610 if (count == nsegs - 1) { 2611 /* Last desc. for this frame. */ 2612 m = sc->alc_cdata.alc_rxhead; 2613 KASSERT(m->m_flags & M_PKTHDR); 2614 /* 2615 * It seems that L1C/L2C controller has no way 2616 * to tell hardware to strip CRC bytes. 2617 */ 2618 m->m_pkthdr.len = 2619 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 2620 if (nsegs > 1) { 2621 /* Set last mbuf size. */ 2622 mp->m_len = sc->alc_cdata.alc_rxlen - 2623 (nsegs - 1) * sc->alc_buf_size; 2624 /* Remove the CRC bytes in chained mbufs. */ 2625 if (mp->m_len <= ETHER_CRC_LEN) { 2626 sc->alc_cdata.alc_rxtail = 2627 sc->alc_cdata.alc_rxprev_tail; 2628 sc->alc_cdata.alc_rxtail->m_len -= 2629 (ETHER_CRC_LEN - mp->m_len); 2630 sc->alc_cdata.alc_rxtail->m_next = NULL; 2631 m_freem(mp); 2632 } else { 2633 mp->m_len -= ETHER_CRC_LEN; 2634 } 2635 } else 2636 m->m_len = m->m_pkthdr.len; 2637 m_set_rcvif(m, ifp); 2638 #if NVLAN > 0 2639 /* 2640 * Due to hardware bugs, Rx checksum offloading 2641 * was intentionally disabled. 2642 */ 2643 if (status & RRD_VLAN_TAG) { 2644 uint32_t vtag = RRD_VLAN(le32toh(rrd->vtag)); 2645 vlan_set_tag(m, ntohs(vtag)); 2646 } 2647 #endif 2648 2649 /* Pass it on. */ 2650 if_percpuq_enqueue(ifp->if_percpuq, m); 2651 } 2652 } 2653 /* Reset mbuf chains. */ 2654 ALC_RXCHAIN_RESET(sc); 2655 } 2656 2657 static void 2658 alc_tick(void *xsc) 2659 { 2660 struct alc_softc *sc = xsc; 2661 struct mii_data *mii = &sc->sc_miibus; 2662 int s; 2663 2664 s = splnet(); 2665 mii_tick(mii); 2666 alc_stats_update(sc); 2667 splx(s); 2668 2669 callout_schedule(&sc->sc_tick_ch, hz); 2670 } 2671 2672 static void 2673 alc_osc_reset(struct alc_softc *sc) 2674 { 2675 uint32_t reg; 2676 2677 reg = CSR_READ_4(sc, ALC_MISC3); 2678 reg &= ~MISC3_25M_BY_SW; 2679 reg |= MISC3_25M_NOTO_INTNL; 2680 CSR_WRITE_4(sc, ALC_MISC3, reg); 2681 2682 reg = CSR_READ_4(sc, ALC_MISC); 2683 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) { 2684 /* 2685 * Restore over-current protection default value. 2686 * This value could be reset by MAC reset. 2687 */ 2688 reg &= ~MISC_PSW_OCP_MASK; 2689 reg |= (MISC_PSW_OCP_DEFAULT << MISC_PSW_OCP_SHIFT); 2690 reg &= ~MISC_INTNLOSC_OPEN; 2691 CSR_WRITE_4(sc, ALC_MISC, reg); 2692 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 2693 reg = CSR_READ_4(sc, ALC_MISC2); 2694 reg &= ~MISC2_CALB_START; 2695 CSR_WRITE_4(sc, ALC_MISC2, reg); 2696 CSR_WRITE_4(sc, ALC_MISC2, reg | MISC2_CALB_START); 2697 2698 } else { 2699 reg &= ~MISC_INTNLOSC_OPEN; 2700 /* Disable isolate for revision A devices. */ 2701 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 2702 reg &= ~MISC_ISO_ENB; 2703 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 2704 CSR_WRITE_4(sc, ALC_MISC, reg); 2705 } 2706 2707 DELAY(20); 2708 } 2709 2710 static void 2711 alc_reset(struct alc_softc *sc) 2712 { 2713 uint32_t pmcfg, reg; 2714 int i; 2715 2716 pmcfg = 0; 2717 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2718 /* Reset workaround. */ 2719 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 1); 2720 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 2721 (sc->alc_rev & 0x01) != 0) { 2722 /* Disable L0s/L1s before reset. */ 2723 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 2724 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 2725 != 0) { 2726 pmcfg &= ~(PM_CFG_ASPM_L0S_ENB | 2727 PM_CFG_ASPM_L1_ENB); 2728 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 2729 } 2730 } 2731 } 2732 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 2733 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; 2734 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2735 2736 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2737 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2738 DELAY(10); 2739 if (CSR_READ_4(sc, ALC_MBOX_RD0_PROD_IDX) == 0) 2740 break; 2741 } 2742 if (i == 0) 2743 printf("%s: MAC reset timeout!\n", device_xname(sc->sc_dev)); 2744 } 2745 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2746 DELAY(10); 2747 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 2748 break; 2749 } 2750 if (i == 0) 2751 printf("%s: master reset timeout!\n", device_xname(sc->sc_dev)); 2752 2753 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2754 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 2755 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC | 2756 IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 2757 break; 2758 DELAY(10); 2759 } 2760 if (i == 0) 2761 printf("%s: reset timeout(0x%08x)!\n", 2762 device_xname(sc->sc_dev), reg); 2763 2764 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2765 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 2766 (sc->alc_rev & 0x01) != 0) { 2767 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 2768 reg |= MASTER_CLK_SEL_DIS; 2769 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2770 /* Restore L0s/L1s config. */ 2771 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 2772 != 0) 2773 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 2774 } 2775 2776 alc_osc_reset(sc); 2777 reg = CSR_READ_4(sc, ALC_MISC3); 2778 reg &= ~MISC3_25M_BY_SW; 2779 reg |= MISC3_25M_NOTO_INTNL; 2780 CSR_WRITE_4(sc, ALC_MISC3, reg); 2781 reg = CSR_READ_4(sc, ALC_MISC); 2782 reg &= ~MISC_INTNLOSC_OPEN; 2783 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 2784 reg &= ~MISC_ISO_ENB; 2785 CSR_WRITE_4(sc, ALC_MISC, reg); 2786 DELAY(20); 2787 } 2788 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 2789 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B || 2790 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2) 2791 CSR_WRITE_4(sc, ALC_SERDES_LOCK, 2792 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | 2793 SERDES_PHY_CLK_SLOWDOWN); 2794 } 2795 2796 static int 2797 alc_init(struct ifnet *ifp) 2798 { 2799 2800 return alc_init_backend(ifp, true); 2801 } 2802 2803 static int 2804 alc_init_backend(struct ifnet *ifp, bool init) 2805 { 2806 struct alc_softc *sc = ifp->if_softc; 2807 struct mii_data *mii; 2808 uint8_t eaddr[ETHER_ADDR_LEN]; 2809 bus_addr_t paddr; 2810 uint32_t reg, rxf_hi, rxf_lo; 2811 int error; 2812 2813 /* 2814 * Cancel any pending I/O. 2815 */ 2816 alc_stop(ifp, 0); 2817 /* 2818 * Reset the chip to a known state. 2819 */ 2820 alc_reset(sc); 2821 2822 /* Initialize Rx descriptors. */ 2823 error = alc_init_rx_ring(sc, init); 2824 if (error != 0) { 2825 printf("%s: no memory for Rx buffers.\n", device_xname(sc->sc_dev)); 2826 alc_stop(ifp, 0); 2827 return (error); 2828 } 2829 alc_init_rr_ring(sc); 2830 alc_init_tx_ring(sc); 2831 alc_init_cmb(sc); 2832 alc_init_smb(sc); 2833 2834 /* Enable all clocks. */ 2835 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2836 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, CLK_GATING_DMAW_ENB | 2837 CLK_GATING_DMAR_ENB | CLK_GATING_TXQ_ENB | 2838 CLK_GATING_RXQ_ENB | CLK_GATING_TXMAC_ENB | 2839 CLK_GATING_RXMAC_ENB); 2840 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) 2841 CSR_WRITE_4(sc, ALC_IDLE_DECISN_TIMER, 2842 IDLE_DECISN_TIMER_DEFAULT_1MS); 2843 } else 2844 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0); 2845 2846 /* Reprogram the station address. */ 2847 memcpy(eaddr, CLLADDR(ifp->if_sadl), sizeof(eaddr)); 2848 CSR_WRITE_4(sc, ALC_PAR0, (uint32_t)eaddr[2] << 24 2849 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2850 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 2851 /* 2852 * Clear WOL status and disable all WOL feature as WOL 2853 * would interfere Rx operation under normal environments. 2854 */ 2855 CSR_READ_4(sc, ALC_WOL_CFG); 2856 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2857 /* Set Tx descriptor base addresses. */ 2858 paddr = sc->alc_rdata.alc_tx_ring_paddr; 2859 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2860 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2861 /* We don't use high priority ring. */ 2862 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 2863 /* Set Tx descriptor counter. */ 2864 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 2865 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 2866 /* Set Rx descriptor base addresses. */ 2867 paddr = sc->alc_rdata.alc_rx_ring_paddr; 2868 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2869 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2870 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 2871 /* We use one Rx ring. */ 2872 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 2873 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 2874 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 2875 } 2876 /* Set Rx descriptor counter. */ 2877 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 2878 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 2879 2880 /* 2881 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 2882 * if it do not fit the buffer size. Rx return descriptor holds 2883 * a counter that indicates how many fragments were made by the 2884 * hardware. The buffer size should be multiple of 8 bytes. 2885 * Since hardware has limit on the size of buffer size, always 2886 * use the maximum value. 2887 * For strict-alignment architectures make sure to reduce buffer 2888 * size by 8 bytes to make room for alignment fixup. 2889 */ 2890 sc->alc_buf_size = RX_BUF_SIZE_MAX; 2891 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 2892 2893 paddr = sc->alc_rdata.alc_rr_ring_paddr; 2894 /* Set Rx return descriptor base addresses. */ 2895 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2896 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 2897 /* We use one Rx return ring. */ 2898 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 2899 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 2900 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 2901 } 2902 /* Set Rx return descriptor counter. */ 2903 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 2904 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 2905 paddr = sc->alc_rdata.alc_cmb_paddr; 2906 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 2907 paddr = sc->alc_rdata.alc_smb_paddr; 2908 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2909 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 2910 2911 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B) { 2912 /* Reconfigure SRAM - Vendor magic. */ 2913 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); 2914 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); 2915 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); 2916 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); 2917 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); 2918 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); 2919 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); 2920 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); 2921 } 2922 2923 /* Tell hardware that we're ready to load DMA blocks. */ 2924 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 2925 2926 /* Configure interrupt moderation timer. */ 2927 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 2928 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 2929 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 2930 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) 2931 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 2932 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 2933 /* 2934 * We don't want to automatic interrupt clear as task queue 2935 * for the interrupt should know interrupt status. 2936 */ 2937 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 2938 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 2939 reg |= MASTER_SA_TIMER_ENB; 2940 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 2941 reg |= MASTER_IM_RX_TIMER_ENB; 2942 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0 && 2943 ALC_USECS(sc->alc_int_tx_mod) != 0) 2944 reg |= MASTER_IM_TX_TIMER_ENB; 2945 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2946 /* 2947 * Disable interrupt re-trigger timer. We don't want automatic 2948 * re-triggering of un-ACKed interrupts. 2949 */ 2950 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 2951 /* Configure CMB. */ 2952 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2953 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, ALC_TX_RING_CNT / 3); 2954 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, 2955 ALC_USECS(sc->alc_int_tx_mod)); 2956 } else { 2957 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 2958 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 2959 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 2960 } else 2961 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 2962 } 2963 /* 2964 * Hardware can be configured to issue SMB interrupt based 2965 * on programmed interval. Since there is a callout that is 2966 * invoked for every hz in driver we use that instead of 2967 * relying on periodic SMB interrupt. 2968 */ 2969 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 2970 /* Clear MAC statistics. */ 2971 alc_stats_clear(sc); 2972 2973 /* 2974 * Always use maximum frame size that controller can support. 2975 * Otherwise received frames that has larger frame length 2976 * than alc(4) MTU would be silently dropped in hardware. This 2977 * would make path-MTU discovery hard as sender wouldn't get 2978 * any responses from receiver. alc(4) supports 2979 * multi-fragmented frames on Rx path so it has no issue on 2980 * assembling fragmented frames. Using maximum frame size also 2981 * removes the need to reinitialize hardware when interface 2982 * MTU configuration was changed. 2983 * 2984 * Be conservative in what you do, be liberal in what you 2985 * accept from others - RFC 793. 2986 */ 2987 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen); 2988 2989 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 2990 /* Disable header split(?) */ 2991 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 2992 2993 /* Configure IPG/IFG parameters. */ 2994 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 2995 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & 2996 IPG_IFG_IPGT_MASK) | 2997 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & 2998 IPG_IFG_MIFG_MASK) | 2999 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & 3000 IPG_IFG_IPG1_MASK) | 3001 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & 3002 IPG_IFG_IPG2_MASK)); 3003 /* Set parameters for half-duplex media. */ 3004 CSR_WRITE_4(sc, ALC_HDPX_CFG, 3005 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 3006 HDPX_CFG_LCOL_MASK) | 3007 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 3008 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 3009 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 3010 HDPX_CFG_ABEBT_MASK) | 3011 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 3012 HDPX_CFG_JAMIPG_MASK)); 3013 } 3014 3015 /* 3016 * Set TSO/checksum offload threshold. For frames that is 3017 * larger than this threshold, hardware wouldn't do 3018 * TSO/checksum offloading. 3019 */ 3020 reg = (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 3021 TSO_OFFLOAD_THRESH_MASK; 3022 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3023 reg |= TSO_OFFLOAD_ERRLGPKT_DROP_ENB; 3024 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, reg); 3025 /* Configure TxQ. */ 3026 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 3027 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 3028 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B || 3029 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) 3030 reg >>= 1; 3031 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 3032 TXQ_CFG_TD_BURST_MASK; 3033 reg |= TXQ_CFG_IP_OPTION_ENB | TXQ_CFG_8023_ENB; 3034 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 3035 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3036 reg = (TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q1_BURST_SHIFT | 3037 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q2_BURST_SHIFT | 3038 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q3_BURST_SHIFT | 3039 HQTD_CFG_BURST_ENB); 3040 CSR_WRITE_4(sc, ALC_HQTD_CFG, reg); 3041 reg = WRR_PRI_RESTRICT_NONE; 3042 reg |= (WRR_PRI_DEFAULT << WRR_PRI0_SHIFT | 3043 WRR_PRI_DEFAULT << WRR_PRI1_SHIFT | 3044 WRR_PRI_DEFAULT << WRR_PRI2_SHIFT | 3045 WRR_PRI_DEFAULT << WRR_PRI3_SHIFT); 3046 CSR_WRITE_4(sc, ALC_WRR, reg); 3047 } else { 3048 /* Configure Rx free descriptor pre-fetching. */ 3049 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 3050 ((RX_RD_FREE_THRESH_HI_DEFAULT << 3051 RX_RD_FREE_THRESH_HI_SHIFT) & RX_RD_FREE_THRESH_HI_MASK) | 3052 ((RX_RD_FREE_THRESH_LO_DEFAULT << 3053 RX_RD_FREE_THRESH_LO_SHIFT) & RX_RD_FREE_THRESH_LO_MASK)); 3054 } 3055 3056 /* 3057 * Configure flow control parameters. 3058 * XON : 80% of Rx FIFO 3059 * XOFF : 30% of Rx FIFO 3060 */ 3061 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3062 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 3063 reg &= SRAM_RX_FIFO_LEN_MASK; 3064 reg *= 8; 3065 if (reg > 8 * 1024) 3066 reg -= RX_FIFO_PAUSE_816X_RSVD; 3067 else 3068 reg -= RX_BUF_SIZE_MAX; 3069 reg /= 8; 3070 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 3071 ((reg << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 3072 RX_FIFO_PAUSE_THRESH_LO_MASK) | 3073 (((RX_FIFO_PAUSE_816X_RSVD / 8) << 3074 RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 3075 RX_FIFO_PAUSE_THRESH_HI_MASK)); 3076 } else if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8131 || 3077 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8132) { 3078 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 3079 rxf_hi = (reg * 8) / 10; 3080 rxf_lo = (reg * 3) / 10; 3081 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 3082 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 3083 RX_FIFO_PAUSE_THRESH_LO_MASK) | 3084 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 3085 RX_FIFO_PAUSE_THRESH_HI_MASK)); 3086 } 3087 3088 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3089 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 3090 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 3091 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 3092 } 3093 3094 /* Configure RxQ. */ 3095 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 3096 RXQ_CFG_RD_BURST_MASK; 3097 reg |= RXQ_CFG_RSS_MODE_DIS; 3098 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3099 reg |= (RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT << 3100 RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT) & 3101 RXQ_CFG_816X_IDT_TBL_SIZE_MASK; 3102 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 3103 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M; 3104 } else { 3105 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0 && 3106 sc->alc_ident->deviceid != PCI_PRODUCT_ATTANSIC_AR8151_V2) 3107 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M; 3108 } 3109 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3110 3111 /* Configure DMA parameters. */ 3112 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 3113 reg |= sc->alc_rcb; 3114 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 3115 reg |= DMA_CFG_CMB_ENB; 3116 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 3117 reg |= DMA_CFG_SMB_ENB; 3118 else 3119 reg |= DMA_CFG_SMB_DIS; 3120 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 3121 DMA_CFG_RD_BURST_SHIFT; 3122 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 3123 DMA_CFG_WR_BURST_SHIFT; 3124 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 3125 DMA_CFG_RD_DELAY_CNT_MASK; 3126 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 3127 DMA_CFG_WR_DELAY_CNT_MASK; 3128 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3129 switch (AR816X_REV(sc->alc_rev)) { 3130 case AR816X_REV_A0: 3131 case AR816X_REV_A1: 3132 reg |= DMA_CFG_RD_CHNL_SEL_2; 3133 break; 3134 case AR816X_REV_B0: 3135 /* FALLTHROUGH */ 3136 default: 3137 reg |= DMA_CFG_RD_CHNL_SEL_4; 3138 break; 3139 } 3140 } 3141 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3142 3143 /* 3144 * Configure Tx/Rx MACs. 3145 * - Auto-padding for short frames. 3146 * - Enable CRC generation. 3147 * Actual reconfiguration of MAC for resolved speed/duplex 3148 * is followed after detection of link establishment. 3149 * AR813x/AR815x always does checksum computation regardless 3150 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 3151 * have bug in protocol field in Rx return structure so 3152 * these controllers can't handle fragmented frames. Disable 3153 * Rx checksum offloading until there is a newer controller 3154 * that has sane implementation. 3155 */ 3156 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 3157 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 3158 MAC_CFG_PREAMBLE_MASK); 3159 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 3160 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151 || 3161 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 || 3162 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) 3163 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 3164 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 3165 reg |= MAC_CFG_SPEED_10_100; 3166 else 3167 reg |= MAC_CFG_SPEED_1000; 3168 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3169 3170 /* Set up the receive filter. */ 3171 alc_iff(sc); 3172 alc_rxvlan(sc); 3173 3174 /* Acknowledge all pending interrupts and clear it. */ 3175 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 3176 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3177 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 3178 3179 sc->alc_flags &= ~ALC_FLAG_LINK; 3180 /* Switch to the current media. */ 3181 mii = &sc->sc_miibus; 3182 mii_mediachg(mii); 3183 3184 callout_schedule(&sc->sc_tick_ch, hz); 3185 3186 ifp->if_flags |= IFF_RUNNING; 3187 ifp->if_flags &= ~IFF_OACTIVE; 3188 3189 return (0); 3190 } 3191 3192 static void 3193 alc_stop(struct ifnet *ifp, int disable) 3194 { 3195 struct alc_softc *sc = ifp->if_softc; 3196 struct alc_txdesc *txd; 3197 struct alc_rxdesc *rxd; 3198 uint32_t reg; 3199 int i; 3200 3201 callout_stop(&sc->sc_tick_ch); 3202 3203 /* 3204 * Mark the interface down and cancel the watchdog timer. 3205 */ 3206 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3207 ifp->if_timer = 0; 3208 3209 sc->alc_flags &= ~ALC_FLAG_LINK; 3210 3211 alc_stats_update(sc); 3212 3213 mii_down(&sc->sc_miibus); 3214 3215 /* Disable interrupts. */ 3216 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 3217 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3218 3219 /* Disable DMA. */ 3220 reg = CSR_READ_4(sc, ALC_DMA_CFG); 3221 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 3222 reg |= DMA_CFG_SMB_DIS; 3223 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3224 DELAY(1000); 3225 3226 /* Stop Rx/Tx MACs. */ 3227 alc_stop_mac(sc); 3228 3229 /* Disable interrupts which might be touched in taskq handler. */ 3230 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3231 3232 /* Disable L0s/L1s */ 3233 alc_aspm(sc, 0, IFM_UNKNOWN); 3234 3235 /* Reclaim Rx buffers that have been processed. */ 3236 m_freem(sc->alc_cdata.alc_rxhead); 3237 ALC_RXCHAIN_RESET(sc); 3238 /* 3239 * Free Tx/Rx mbufs still in the queues. 3240 */ 3241 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3242 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3243 if (rxd->rx_m != NULL) { 3244 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 3245 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3246 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 3247 m_freem(rxd->rx_m); 3248 rxd->rx_m = NULL; 3249 } 3250 } 3251 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3252 txd = &sc->alc_cdata.alc_txdesc[i]; 3253 if (txd->tx_m != NULL) { 3254 bus_dmamap_sync(sc->sc_dmat, txd->tx_dmamap, 0, 3255 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 3256 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 3257 m_freem(txd->tx_m); 3258 txd->tx_m = NULL; 3259 } 3260 } 3261 } 3262 3263 static void 3264 alc_stop_mac(struct alc_softc *sc) 3265 { 3266 uint32_t reg; 3267 int i; 3268 3269 alc_stop_queue(sc); 3270 /* Disable Rx/Tx MAC. */ 3271 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3272 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 3273 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 3274 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3275 } 3276 for (i = ALC_TIMEOUT; i > 0; i--) { 3277 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3278 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC)) == 0) 3279 break; 3280 DELAY(10); 3281 } 3282 if (i == 0) 3283 printf("%s: could not disable Rx/Tx MAC(0x%08x)!\n", 3284 device_xname(sc->sc_dev), reg); 3285 } 3286 3287 static void 3288 alc_start_queue(struct alc_softc *sc) 3289 { 3290 uint32_t qcfg[] = { 3291 0, 3292 RXQ_CFG_QUEUE0_ENB, 3293 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 3294 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 3295 RXQ_CFG_ENB 3296 }; 3297 uint32_t cfg; 3298 3299 /* Enable RxQ. */ 3300 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 3301 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3302 cfg &= ~RXQ_CFG_ENB; 3303 cfg |= qcfg[1]; 3304 } else 3305 cfg |= RXQ_CFG_QUEUE0_ENB; 3306 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 3307 /* Enable TxQ. */ 3308 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 3309 cfg |= TXQ_CFG_ENB; 3310 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 3311 } 3312 3313 static void 3314 alc_stop_queue(struct alc_softc *sc) 3315 { 3316 uint32_t reg; 3317 int i; 3318 3319 /* Disable RxQ. */ 3320 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 3321 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3322 if ((reg & RXQ_CFG_ENB) != 0) { 3323 reg &= ~RXQ_CFG_ENB; 3324 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3325 } 3326 } else { 3327 if ((reg & RXQ_CFG_QUEUE0_ENB) != 0) { 3328 reg &= ~RXQ_CFG_QUEUE0_ENB; 3329 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3330 } 3331 } 3332 /* Disable TxQ. */ 3333 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 3334 if ((reg & TXQ_CFG_ENB) != 0) { 3335 reg &= ~TXQ_CFG_ENB; 3336 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 3337 } 3338 DELAY(40); 3339 for (i = ALC_TIMEOUT; i > 0; i--) { 3340 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3341 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 3342 break; 3343 DELAY(10); 3344 } 3345 if (i == 0) 3346 printf("%s: could not disable RxQ/TxQ (0x%08x)!\n", 3347 device_xname(sc->sc_dev), reg); 3348 } 3349 3350 static void 3351 alc_init_tx_ring(struct alc_softc *sc) 3352 { 3353 struct alc_ring_data *rd; 3354 struct alc_txdesc *txd; 3355 int i; 3356 3357 sc->alc_cdata.alc_tx_prod = 0; 3358 sc->alc_cdata.alc_tx_cons = 0; 3359 sc->alc_cdata.alc_tx_cnt = 0; 3360 3361 rd = &sc->alc_rdata; 3362 memset(rd->alc_tx_ring, 0, ALC_TX_RING_SZ); 3363 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3364 txd = &sc->alc_cdata.alc_txdesc[i]; 3365 txd->tx_m = NULL; 3366 } 3367 3368 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 3369 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 3370 } 3371 3372 static int 3373 alc_init_rx_ring(struct alc_softc *sc, bool init) 3374 { 3375 struct alc_ring_data *rd; 3376 struct alc_rxdesc *rxd; 3377 int i; 3378 3379 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 3380 rd = &sc->alc_rdata; 3381 memset(rd->alc_rx_ring, 0, ALC_RX_RING_SZ); 3382 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3383 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3384 rxd->rx_m = NULL; 3385 rxd->rx_desc = &rd->alc_rx_ring[i]; 3386 if (alc_newbuf(sc, rxd, init) != 0) 3387 return (ENOBUFS); 3388 } 3389 3390 /* 3391 * Since controller does not update Rx descriptors, driver 3392 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 3393 * is enough to ensure coherence. 3394 */ 3395 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 3396 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 3397 /* Let controller know availability of new Rx buffers. */ 3398 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 3399 3400 return (0); 3401 } 3402 3403 static void 3404 alc_init_rr_ring(struct alc_softc *sc) 3405 { 3406 struct alc_ring_data *rd; 3407 3408 sc->alc_cdata.alc_rr_cons = 0; 3409 ALC_RXCHAIN_RESET(sc); 3410 3411 rd = &sc->alc_rdata; 3412 memset(rd->alc_rr_ring, 0, ALC_RR_RING_SZ); 3413 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 3414 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, 3415 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3416 } 3417 3418 static void 3419 alc_init_cmb(struct alc_softc *sc) 3420 { 3421 struct alc_ring_data *rd; 3422 3423 rd = &sc->alc_rdata; 3424 memset(rd->alc_cmb, 0, ALC_CMB_SZ); 3425 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 3426 sc->alc_cdata.alc_cmb_map->dm_mapsize, 3427 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3428 } 3429 3430 static void 3431 alc_init_smb(struct alc_softc *sc) 3432 { 3433 struct alc_ring_data *rd; 3434 3435 rd = &sc->alc_rdata; 3436 memset(rd->alc_smb, 0, ALC_SMB_SZ); 3437 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 3438 sc->alc_cdata.alc_smb_map->dm_mapsize, 3439 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3440 } 3441 3442 static void 3443 alc_rxvlan(struct alc_softc *sc) 3444 { 3445 uint32_t reg; 3446 3447 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3448 if (sc->sc_ec.ec_capenable & ETHERCAP_VLAN_HWTAGGING) 3449 reg |= MAC_CFG_VLAN_TAG_STRIP; 3450 else 3451 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3452 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3453 } 3454 3455 static void 3456 alc_iff(struct alc_softc *sc) 3457 { 3458 struct ethercom *ec = &sc->sc_ec; 3459 struct ifnet *ifp = &ec->ec_if; 3460 struct ether_multi *enm; 3461 struct ether_multistep step; 3462 uint32_t crc; 3463 uint32_t mchash[2]; 3464 uint32_t rxcfg; 3465 3466 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 3467 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3468 ifp->if_flags &= ~IFF_ALLMULTI; 3469 3470 /* 3471 * Always accept broadcast frames. 3472 */ 3473 rxcfg |= MAC_CFG_BCAST; 3474 3475 /* Program new filter. */ 3476 if ((ifp->if_flags & IFF_PROMISC) != 0) 3477 goto update; 3478 3479 memset(mchash, 0, sizeof(mchash)); 3480 3481 ETHER_LOCK(ec); 3482 ETHER_FIRST_MULTI(step, ec, enm); 3483 while (enm != NULL) { 3484 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3485 /* XXX Use ETHER_F_ALLMULTI in future. */ 3486 ifp->if_flags |= IFF_ALLMULTI; 3487 ETHER_UNLOCK(ec); 3488 goto update; 3489 } 3490 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3491 mchash[crc >> 31] |= 1U << ((crc >> 26) & 0x1f); 3492 ETHER_NEXT_MULTI(step, enm); 3493 } 3494 ETHER_UNLOCK(ec); 3495 3496 update: 3497 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3498 if (ifp->if_flags & IFF_PROMISC) { 3499 rxcfg |= MAC_CFG_PROMISC; 3500 /* XXX Use ETHER_F_ALLMULTI in future. */ 3501 ifp->if_flags |= IFF_ALLMULTI; 3502 } else 3503 rxcfg |= MAC_CFG_ALLMULTI; 3504 mchash[0] = mchash[1] = 0xFFFFFFFF; 3505 } 3506 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 3507 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 3508 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 3509 } 3510 3511 MODULE(MODULE_CLASS_DRIVER, if_alc, "pci"); 3512 3513 #ifdef _MODULE 3514 #include "ioconf.c" 3515 #endif 3516 3517 static int 3518 if_alc_modcmd(modcmd_t cmd, void *opaque) 3519 { 3520 int error = 0; 3521 3522 switch (cmd) { 3523 case MODULE_CMD_INIT: 3524 #ifdef _MODULE 3525 error = config_init_component(cfdriver_ioconf_if_alc, 3526 cfattach_ioconf_if_alc, cfdata_ioconf_if_alc); 3527 #endif 3528 return error; 3529 case MODULE_CMD_FINI: 3530 #ifdef _MODULE 3531 error = config_fini_component(cfdriver_ioconf_if_alc, 3532 cfattach_ioconf_if_alc, cfdata_ioconf_if_alc); 3533 #endif 3534 return error; 3535 default: 3536 return ENOTTY; 3537 } 3538 } 3539
Indexes created Sun Oct 25 00:26:45 UTC 2026