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      1 /* $NetBSD: tegra_timerreg.h,v 1.2 2015/12/22 22:10:36 jmcneill Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca>
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  * SUCH DAMAGE.
     27  */
     28 
     29 #ifndef _ARM_TEGRA_TIMERREG_H
     30 #define _ARM_TEGRA_TIMERREG_H
     31 
     32 #define TMR1_PTV_REG		0x00
     33 #define TMR1_PCR_REG		0x04
     34 #define TMR2_PTV_REG		0x08
     35 #define TMR2_PCR_REG		0x0c
     36 #define TMRUS_CNTR_1US_REG	0x10
     37 #define TMRUS_USEC_CFG_REG	0x14
     38 #define TMRUS_CNTR_FREEZE_REG	0x18
     39 #define TMR3_PTV_REG		0x50
     40 #define TMR3_PCR_REG		0x54
     41 #define TMR4_PTV_REG		0x58
     42 #define TMR4_PCR_REG		0x5c
     43 #define TMR5_PTV_REG		0x60
     44 #define TMR5_PCR_REG		0x64
     45 #define TMR6_PTV_REG		0x68
     46 #define TMR6_PCR_REG		0x6c
     47 #define TMR7_PTV_REG		0x70
     48 #define TMR7_PCR_REG		0x74
     49 #define TMR8_PTV_REG		0x78
     50 #define TMR8_PCR_REG		0x7c
     51 #define TMR9_PTV_REG		0x80
     52 #define TMR9_PCR_REG		0x84
     53 #define TMR0_PTV_REG		0x88
     54 #define TMR0_PCR_REG		0x8c
     55 
     56 #define TMR_PTV_EN		__BIT(31)
     57 #define TMR_PTV_PER		__BIT(30)
     58 #define TMR_PTV_VAL		__BITS(28,0)
     59 
     60 #define TMR_PCR_INTR_CLR	__BIT(30)
     61 #define TMR_PCR_VAL		__BITS(28,0)
     62 
     63 #define WDT0_CONFIG_REG		0x100
     64 #define WDT0_STATUS_REG		0x104
     65 #define WDT0_COMMAND_REG	0x108
     66 #define WDT0_UNLOCK_PATTERN_REG	0x10c
     67 #define WDT1_CONFIG_REG		0x100
     68 #define WDT1_STATUS_REG		0x104
     69 #define WDT1_COMMAND_REG	0x108
     70 #define WDT1_UNLOCK_PATTERN_REG	0x10c
     71 #define WDT2_CONFIG_REG		0x100
     72 #define WDT2_STATUS_REG		0x104
     73 #define WDT2_COMMAND_REG	0x108
     74 #define WDT2_UNLOCK_PATTERN_REG	0x10c
     75 #define WDT3_CONFIG_REG		0x100
     76 #define WDT3_STATUS_REG		0x104
     77 #define WDT3_COMMAND_REG	0x108
     78 #define WDT3_UNLOCK_PATTERN_REG	0x10c
     79 #define WDT4_CONFIG_REG		0x100
     80 #define WDT4_STATUS_REG		0x104
     81 #define WDT4_COMMAND_REG	0x108
     82 #define WDT4_UNLOCK_PATTERN_REG	0x10c
     83 
     84 #endif /* _ARM_TEGRA_TIMERREG_H */
     85