| /src/sys/arch/i386/i386/ |
| i386_trap.S | 73 * Trap and fault vector routines
83 #define TRAP(a) pushl $(a) ; jmp _C_LABEL(alltraps)
84 #define ZTRAP(a) pushl $0 ; TRAP(a)
152 call _C_LABEL(trap)
184 /* If so, just handle it as a normal trap. */
228 TRAP(T_DOUBLEFLT)
236 TRAP(T_TSSFLT)
240 TRAP(T_SEGNPFLT)
244 TRAP(T_STKFLT)
248 TRAP(T_PROTFLT
[all...] |
| /src/sys/arch/amd64/amd64/ |
| amd64_trap.S | 76 #include <machine/trap.h>
82 * Trap and fault vector routines
104 #define TRAP(a) TRAP_NJ(a) ; TRAPENTRY
363 TRAP(T_DOUBLEFLT)
407 TRAP(T_TSSFLT)
435 TRAP(T_PAGEFLT)
453 * interrupted just before the CLI in the trap macro.
468 TRAP(T_ALIGNFLT)
527 * It is possible that we received a trap in kernel mode, but with the user
562 * everything behaves as if we had received a trap from the outer frame
[all...] |
| /src/sys/arch/x86/include/ |
| db_machdep.h | 9 #define TRAP 1
|
| /src/external/gpl3/binutils/dist/opcodes/ |
| mips16-opc.c | 187 #define TRAP INSN_NO_DELAY_SLOT
260 {"break", "", 0xe805, 0xffff, TRAP, SH, I1, 0, 0 },
261 {"break", "6", 0xe805, 0xf81f, TRAP, SH, I1, 0, 0 },
316 {"exit", "L", 0xed09, 0xff1f, TRAP, SH, I1, 0, 0 },
317 {"exit", "L", 0xee09, 0xff1f, TRAP, SH, I1, 0, 0 },
318 {"exit", "", 0xef09, 0xffff, TRAP, SH, I1, 0, 0 },
319 {"exit", "L", 0xef09, 0xff1f, TRAP, SH, I1, 0, 0 },
320 {"entry", "", 0xe809, 0xffff, TRAP, SH, I1, 0, 0 },
321 {"entry", "l", 0xe809, 0xf81f, TRAP, SH, I1, 0, 0 },
449 {"sdbbp", "", 0xe801, 0xffff, TRAP, SH, I32, 0, 0 }
[all...] |
| micromips-opc.c | 211 #define TRAP INSN_NO_DELAY_SLOT
456 {"break", "", 0x4680, 0xffff, TRAP, 0, I1, 0, 0 },
457 {"break", "", 0x00000007, 0xffffffff, TRAP, 0, I1, 0, 0 },
458 {"break", "mF", 0x4680, 0xfff0, TRAP, 0, I1, 0, 0 },
459 {"break", "c", 0x00000007, 0xfc00ffff, TRAP, 0, I1, 0, 0 },
460 {"break", "c,q", 0x00000007, 0xfc00003f, TRAP, 0, I1, 0, 0 },
566 {"cftc1", "s,y", 0x0000043e, 0xfc00ffff, WR_1|RD_C1|TRAP|LC, AL, 0, MT32, 0 },
567 {"cftc1", "s,T", 0x0000043e, 0xfc00ffff, WR_1|RD_C1|TRAP|LC, AL, 0, MT32, 0 },
568 {"cftc2", "s,y", 0x0000045e, 0xfc00ffff, WR_1|RD_C2|TRAP|LC, AL, 0, MT32, 0 },
575 {"cttc1", "t,g", 0x00000436, 0xfc00ffff, RD_1|WR_CC|TRAP|CM, AL, 0, MT32, 0 }
[all...] |
| mips-opc.c | 229 #define TRAP INSN_NO_DELAY_SLOT
798 {"break", "", 0x0000000d, 0xffffffff, TRAP, 0, I1, 0, 0 },
799 {"break", "c", 0x0000000d, 0xfc00ffff, TRAP, 0, I1, 0, 0 },
800 {"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, 0, I1, 0, 0 },
989 {"cftc1", "d,y", 0x41000023, 0xffe007ff, WR_1|RD_C1|TRAP|LC, AL, 0, MT32, 0 },
990 {"cftc1", "d,T", 0x41000023, 0xffe007ff, WR_1|RD_C1|TRAP|LC, AL, 0, MT32, 0 },
991 {"cftc2", "d,y", 0x41000025, 0xffe007ff, WR_1|RD_C2|TRAP|LC, AL, 0, MT32, IOCT|IOCTP|IOCT2 },
1006 {"cttc1", "t,g", 0x41800023, 0xffe007ff, RD_1|WR_CC|TRAP|CM, AL, 0, MT32, 0 },
1007 {"cttc1", "t,S", 0x41800023, 0xffe007ff, RD_1|WR_CC|TRAP|CM, AL, 0, MT32, 0 },
1008 {"cttc2", "t,g", 0x41800025, 0xffe007ff, RD_1|WR_CC|TRAP|CM, AL, 0, MT32, IOCT|IOCTP|IOCT2 }
[all...] |
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| mips16-opc.c | 187 #define TRAP INSN_NO_DELAY_SLOT
260 {"break", "", 0xe805, 0xffff, TRAP, SH, I1, 0, 0 },
261 {"break", "6", 0xe805, 0xf81f, TRAP, SH, I1, 0, 0 },
316 {"exit", "L", 0xed09, 0xff1f, TRAP, SH, I1, 0, 0 },
317 {"exit", "L", 0xee09, 0xff1f, TRAP, SH, I1, 0, 0 },
318 {"exit", "", 0xef09, 0xffff, TRAP, SH, I1, 0, 0 },
319 {"exit", "L", 0xef09, 0xff1f, TRAP, SH, I1, 0, 0 },
320 {"entry", "", 0xe809, 0xffff, TRAP, SH, I1, 0, 0 },
321 {"entry", "l", 0xe809, 0xf81f, TRAP, SH, I1, 0, 0 },
449 {"sdbbp", "", 0xe801, 0xffff, TRAP, SH, I32, 0, 0 }
[all...] |
| micromips-opc.c | 211 #define TRAP INSN_NO_DELAY_SLOT
456 {"break", "", 0x4680, 0xffff, TRAP, 0, I1, 0, 0 },
457 {"break", "", 0x00000007, 0xffffffff, TRAP, 0, I1, 0, 0 },
458 {"break", "mF", 0x4680, 0xfff0, TRAP, 0, I1, 0, 0 },
459 {"break", "c", 0x00000007, 0xfc00ffff, TRAP, 0, I1, 0, 0 },
460 {"break", "c,q", 0x00000007, 0xfc00003f, TRAP, 0, I1, 0, 0 },
566 {"cftc1", "s,y", 0x0000043e, 0xfc00ffff, WR_1|RD_C1|TRAP|LC, AL, 0, MT32, 0 },
567 {"cftc1", "s,T", 0x0000043e, 0xfc00ffff, WR_1|RD_C1|TRAP|LC, AL, 0, MT32, 0 },
568 {"cftc2", "s,y", 0x0000045e, 0xfc00ffff, WR_1|RD_C2|TRAP|LC, AL, 0, MT32, 0 },
575 {"cttc1", "t,g", 0x00000436, 0xfc00ffff, RD_1|WR_CC|TRAP|CM, AL, 0, MT32, 0 }
[all...] |
| mips-opc.c | 229 #define TRAP INSN_NO_DELAY_SLOT
798 {"break", "", 0x0000000d, 0xffffffff, TRAP, 0, I1, 0, 0 },
799 {"break", "c", 0x0000000d, 0xfc00ffff, TRAP, 0, I1, 0, 0 },
800 {"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, 0, I1, 0, 0 },
989 {"cftc1", "d,y", 0x41000023, 0xffe007ff, WR_1|RD_C1|TRAP|LC, AL, 0, MT32, 0 },
990 {"cftc1", "d,T", 0x41000023, 0xffe007ff, WR_1|RD_C1|TRAP|LC, AL, 0, MT32, 0 },
991 {"cftc2", "d,y", 0x41000025, 0xffe007ff, WR_1|RD_C2|TRAP|LC, AL, 0, MT32, IOCT|IOCTP|IOCT2 },
1006 {"cttc1", "t,g", 0x41800023, 0xffe007ff, RD_1|WR_CC|TRAP|CM, AL, 0, MT32, 0 },
1007 {"cttc1", "t,S", 0x41800023, 0xffe007ff, RD_1|WR_CC|TRAP|CM, AL, 0, MT32, 0 },
1008 {"cttc2", "t,g", 0x41800025, 0xffe007ff, RD_1|WR_CC|TRAP|CM, AL, 0, MT32, IOCT|IOCTP|IOCT2 }
[all...] |
| /src/external/gpl3/gdb/dist/opcodes/ |
| mips16-opc.c | 187 #define TRAP INSN_NO_DELAY_SLOT
260 {"break", "", 0xe805, 0xffff, TRAP, SH, I1, 0, 0 },
261 {"break", "6", 0xe805, 0xf81f, TRAP, SH, I1, 0, 0 },
316 {"exit", "L", 0xed09, 0xff1f, TRAP, SH, I1, 0, 0 },
317 {"exit", "L", 0xee09, 0xff1f, TRAP, SH, I1, 0, 0 },
318 {"exit", "", 0xef09, 0xffff, TRAP, SH, I1, 0, 0 },
319 {"exit", "L", 0xef09, 0xff1f, TRAP, SH, I1, 0, 0 },
320 {"entry", "", 0xe809, 0xffff, TRAP, SH, I1, 0, 0 },
321 {"entry", "l", 0xe809, 0xf81f, TRAP, SH, I1, 0, 0 },
449 {"sdbbp", "", 0xe801, 0xffff, TRAP, SH, I32, 0, 0 }
[all...] |
| micromips-opc.c | 211 #define TRAP INSN_NO_DELAY_SLOT
456 {"break", "", 0x4680, 0xffff, TRAP, 0, I1, 0, 0 },
457 {"break", "", 0x00000007, 0xffffffff, TRAP, 0, I1, 0, 0 },
458 {"break", "mF", 0x4680, 0xfff0, TRAP, 0, I1, 0, 0 },
459 {"break", "c", 0x00000007, 0xfc00ffff, TRAP, 0, I1, 0, 0 },
460 {"break", "c,q", 0x00000007, 0xfc00003f, TRAP, 0, I1, 0, 0 },
566 {"cftc1", "s,y", 0x0000043e, 0xfc00ffff, WR_1|RD_C1|TRAP|LC, AL, 0, MT32, 0 },
567 {"cftc1", "s,T", 0x0000043e, 0xfc00ffff, WR_1|RD_C1|TRAP|LC, AL, 0, MT32, 0 },
568 {"cftc2", "s,y", 0x0000045e, 0xfc00ffff, WR_1|RD_C2|TRAP|LC, AL, 0, MT32, 0 },
575 {"cttc1", "t,g", 0x00000436, 0xfc00ffff, RD_1|WR_CC|TRAP|CM, AL, 0, MT32, 0 }
[all...] |
| mips-opc.c | 229 #define TRAP INSN_NO_DELAY_SLOT
798 {"break", "", 0x0000000d, 0xffffffff, TRAP, 0, I1, 0, 0 },
799 {"break", "c", 0x0000000d, 0xfc00ffff, TRAP, 0, I1, 0, 0 },
800 {"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, 0, I1, 0, 0 },
989 {"cftc1", "d,y", 0x41000023, 0xffe007ff, WR_1|RD_C1|TRAP|LC, AL, 0, MT32, 0 },
990 {"cftc1", "d,T", 0x41000023, 0xffe007ff, WR_1|RD_C1|TRAP|LC, AL, 0, MT32, 0 },
991 {"cftc2", "d,y", 0x41000025, 0xffe007ff, WR_1|RD_C2|TRAP|LC, AL, 0, MT32, IOCT|IOCTP|IOCT2 },
1006 {"cttc1", "t,g", 0x41800023, 0xffe007ff, RD_1|WR_CC|TRAP|CM, AL, 0, MT32, 0 },
1007 {"cttc1", "t,S", 0x41800023, 0xffe007ff, RD_1|WR_CC|TRAP|CM, AL, 0, MT32, 0 },
1008 {"cttc2", "t,g", 0x41800025, 0xffe007ff, RD_1|WR_CC|TRAP|CM, AL, 0, MT32, IOCT|IOCTP|IOCT2 }
[all...] |
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| mips16-opc.c | 187 #define TRAP INSN_NO_DELAY_SLOT
260 {"break", "", 0xe805, 0xffff, TRAP, SH, I1, 0, 0 },
261 {"break", "6", 0xe805, 0xf81f, TRAP, SH, I1, 0, 0 },
316 {"exit", "L", 0xed09, 0xff1f, TRAP, SH, I1, 0, 0 },
317 {"exit", "L", 0xee09, 0xff1f, TRAP, SH, I1, 0, 0 },
318 {"exit", "", 0xef09, 0xffff, TRAP, SH, I1, 0, 0 },
319 {"exit", "L", 0xef09, 0xff1f, TRAP, SH, I1, 0, 0 },
320 {"entry", "", 0xe809, 0xffff, TRAP, SH, I1, 0, 0 },
321 {"entry", "l", 0xe809, 0xf81f, TRAP, SH, I1, 0, 0 },
449 {"sdbbp", "", 0xe801, 0xffff, TRAP, SH, I32, 0, 0 }
[all...] |
| micromips-opc.c | 203 #define TRAP INSN_NO_DELAY_SLOT
445 {"break", "", 0x4680, 0xffff, TRAP, 0, I1, 0, 0 },
446 {"break", "", 0x00000007, 0xffffffff, TRAP, 0, I1, 0, 0 },
447 {"break", "mF", 0x4680, 0xfff0, TRAP, 0, I1, 0, 0 },
448 {"break", "c", 0x00000007, 0xfc00ffff, TRAP, 0, I1, 0, 0 },
449 {"break", "c,q", 0x00000007, 0xfc00003f, TRAP, 0, I1, 0, 0 },
702 {"hypcall", "", 0x0000c37c, 0xffffffff, TRAP, 0, 0, IVIRT, 0 },
703 {"hypcall", "+J", 0x0000c37c, 0xfc00ffff, TRAP, 0, 0, IVIRT, 0 },
985 {"sdbbp", "", 0x46c0, 0xffff, TRAP, 0, I1, 0, 0 },
986 {"sdbbp", "", 0x0000db7c, 0xffffffff, TRAP, 0, I1, 0, 0 }
[all...] |
| mips-opc.c | 228 #define TRAP INSN_NO_DELAY_SLOT
797 {"break", "", 0x0000000d, 0xffffffff, TRAP, 0, I1, 0, 0 },
798 {"break", "c", 0x0000000d, 0xfc00ffff, TRAP, 0, I1, 0, 0 },
799 {"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, 0, I1, 0, 0 },
988 {"cftc1", "d,y", 0x41000023, 0xffe007ff, WR_1|RD_C1|TRAP|LC, 0, 0, MT32, 0 },
989 {"cftc1", "d,T", 0x41000023, 0xffe007ff, WR_1|RD_C1|TRAP|LC, 0, 0, MT32, 0 },
990 {"cftc2", "d,y", 0x41000025, 0xffe007ff, WR_1|RD_C2|TRAP|LC, 0, 0, MT32, IOCT|IOCTP|IOCT2 },
1005 {"cttc1", "t,g", 0x41800023, 0xffe007ff, RD_1|WR_CC|TRAP|CM, 0, 0, MT32, 0 },
1006 {"cttc1", "t,S", 0x41800023, 0xffe007ff, RD_1|WR_CC|TRAP|CM, 0, 0, MT32, 0 },
1007 {"cttc2", "t,g", 0x41800025, 0xffe007ff, RD_1|WR_CC|TRAP|CM, 0, 0, MT32, IOCT|IOCTP|IOCT2 }
[all...] |
| /src/sys/arch/hppa/hppa/ |
| trap.S | 1 /* $NetBSD: trap.S,v 1.75 2023/07/23 10:09:36 skrll Exp $ */
105 * #include <hppa/hppa/trap.S>
234 * our callee(s). However, see the longer comment in the trap handling
427 * See the comment in the trap handling code below about why we need to
547 #define TRAP(name,num) \
558 TRAP(all,num) ! \
565 TRAP(name,num) ! \
648 ATRAP(recnt,T_RECOVERY) /* 3. recovery counter trap */
652 ATRAP(iprot,T_IPROT) /* 7. instruction protection trap */
653 ATRAP(ill,T_ILLEGAL) /* 8. Illegal instruction trap */
[all...] |
| /src/sys/arch/sparc/sparc/ |
| locore.s | 73 #include <machine/trap.h>
119 * To return from trap we need the two-instruction sequence
130 * trap-frame setup code, since we may need to switch from the kernel
250 * The first thing in the real text segment is the trap vector table,
265 * Each trap has room for four instructions, of which one perforce must
268 * put the trap type value into %l3 (with a few exceptions below).
269 * We could read the trap type field of %tbr later in the code instead,
276 * trap numbers are given as arguments to the trap macros. This means
277 * there is one line per trap. Sigh
[all...] |
| /src/sys/arch/sparc64/sparc64/ |
| locore.s | 63 #define HWREF /* Track ref/mod bits in trap handlers */
84 #include <machine/trap.h>
288 * romtba is the prom trap table base address
302 * The v9 trap frame is stored in the special trap registers. The
315 * trap numbers are given as arguments to the trap macros. This means
316 * there is one line per trap. Sigh.
328 * TA8 -- trap align for 8 instruction traps
329 * TA32 -- trap align for 32 instruction trap
[all...] |
| /src/external/bsd/tcpdump/dist/ |
| print-snmp.c | 141 "Trap",
142 #define TRAP 4
153 #define NOTIFY_CLASS(x) (x == TRAP || x == V2TRAP || x == INFORMREQ)
209 * generic-trap values in the SNMP Trap-PDU
1191 * PDUs for all but Trap: (see rfc1157 from page 15 on)
1202 * PDU for Trap:
1206 * generic-trap INTEGER,
1207 * specific-trap INTEGER,
1391 * Decode SNMP Trap PD
[all...] |
| /src/games/rogue/ |
| rogue.h | 59 #define TRAP ((unsigned short) 0400)
337 typedef struct tr trap; typedef in typeref:struct:tr
341 extern trap traps[];
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 1077 /// TRAP - Trapping instruction
1078 TRAP,
1080 /// DEBUGTRAP - Trap intended to get the attention of a debugger.
1083 /// UBSANTRAP - Trap with an immediate describing the kind of sanitizer
|
