| /src/usr.bin/banner/ |
| banner.c | 104 #define TRC(q) (((q)-' ')&0177)
112 case TRC('_'):
113 case TRC(';'):
114 case TRC(','):
115 case TRC('g'):
116 case TRC('j'):
117 case TRC('p'):
118 case TRC('q'):
119 case TRC('y'):
144 d = dropit(c = TRC(cc))
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/m32c/ |
| reg.c | 601 #define TRC(f,n, id) \
616 TRC (r[0].r_r0, "r0", r0);
617 TRC (r[0].r_r1, "r1", r1);
618 TRC (r[0].r_r2, "r2", r2);
619 TRC (r[0].r_r3, "r3", r3);
620 TRC (r[0].r_a0, "a0", a0);
621 TRC (r[0].r_a1, "a1", a1);
622 TRC (r[0].r_sb, "sb", sb);
623 TRC (r[0].r_fb, "fb", fb);
624 TRC (r[1].r_r0, "r0'", r0)
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/rx/ |
| reg.c | 510 #define TRC(f,n) \
529 TRC (r[i], reg_names[i]);
530 TRC (r_intb, "intb");
531 TRC (r_usp, "usp");
532 TRC (r_isp, "isp");
|
| /src/external/gpl3/gdb/dist/sim/m32c/ |
| reg.c | 601 #define TRC(f,n, id) \
616 TRC (r[0].r_r0, "r0", r0);
617 TRC (r[0].r_r1, "r1", r1);
618 TRC (r[0].r_r2, "r2", r2);
619 TRC (r[0].r_r3, "r3", r3);
620 TRC (r[0].r_a0, "a0", a0);
621 TRC (r[0].r_a1, "a1", a1);
622 TRC (r[0].r_sb, "sb", sb);
623 TRC (r[0].r_fb, "fb", fb);
624 TRC (r[1].r_r0, "r0'", r0)
[all...] |
| /src/external/gpl3/gdb/dist/sim/rx/ |
| reg.c | 510 #define TRC(f,n) \
529 TRC (r[i], reg_names[i]);
530 TRC (r_intb, "intb");
531 TRC (r_usp, "usp");
532 TRC (r_isp, "isp");
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| MachineRegisterInfo.cpp | 496 const TargetRegisterClass &TRC = *getRegClass(Reg);
497 return TRC.getLaneMask();
|
| RegAllocPBQP.cpp | 617 const TargetRegisterClass *TRC = MRI.getRegClass(VReg);
625 ArrayRef<MCPhysReg> RawPRegOrder = TRC->getRawAllocationOrder(MF);
|
| LiveDebugVariables.cpp | 1437 const TargetRegisterClass *TRC = MRI.getRegClass(VirtReg);
1438 bool Success = TII.getStackSlotRange(TRC, Loc.getSubReg(), SpillSize,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| A15SDOptimizer.cpp | 74 unsigned Lane, const TargetRegisterClass *TRC);
97 bool usesRegClass(MachineOperand &MO, const TargetRegisterClass *TRC);
133 const TargetRegisterClass *TRC) {
139 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC);
141 return TRC->contains(Reg);
270 const TargetRegisterClass *TRC =
272 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) {
434 const TargetRegisterClass *TRC) {
435 Register Out = MRI->createVirtualRegister(TRC);
|
| ARMBaseInstrInfo.cpp | 3397 const TargetRegisterClass *TRC = MRI->getRegClass(Reg);
3398 Register NewReg = MRI->createVirtualRegister(TRC);
3420 MRI->constrainRegClass(UseMI.getOperand(0).getReg(), TRC);
|
| ARMISelLowering.cpp | 10073 const TargetRegisterClass *TRC = isThumb ? &ARM::tGPRRegClass
10092 Register NewVReg1 = MRI->createVirtualRegister(TRC);
10098 Register NewVReg2 = MRI->createVirtualRegister(TRC);
10104 Register NewVReg3 = MRI->createVirtualRegister(TRC);
10122 Register NewVReg1 = MRI->createVirtualRegister(TRC);
10127 Register NewVReg2 = MRI->createVirtualRegister(TRC);
10132 Register NewVReg3 = MRI->createVirtualRegister(TRC);
10137 Register NewVReg4 = MRI->createVirtualRegister(TRC);
10143 Register NewVReg5 = MRI->createVirtualRegister(TRC);
10158 Register NewVReg1 = MRI->createVirtualRegister(TRC);
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblyAsmPrinter.cpp | 62 const TargetRegisterClass *TRC = MRI->getRegClass(RegNo);
65 if (TRI->isTypeLegalForClass(*TRC, T))
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86AvoidStoreForwardingBlocks.cpp | 563 const auto *TRC = TII->getRegClass(TII->get(LoadInst->getOpcode()), 0, TRI,
565 return TRI->getRegSizeInBits(*TRC) / 8;
|
| /src/usr.sbin/lpr/lpd/ |
| printjob.c | 1063 #define TRC(q) (((q)-' ')&0177)
1078 d = dropit(c = TRC(cc = *sp++));
1104 case TRC('_'):
1105 case TRC(';'):
1106 case TRC(','):
1107 case TRC('g'):
1108 case TRC('j'):
1109 case TRC('p'):
1110 case TRC('q'):
1111 case TRC('y')
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 380 const TargetRegisterClass *TRC = TRI->getPointerRegClass(*MF, /*Kind=*/1);
382 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i32);
|
| PPCMIPeephole.cpp | 943 const TargetRegisterClass *TRC = MI.getOpcode() == PPC::ADD8
946 MRI->setRegClass(DominatorReg, TRC);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZISelDAGToDAG.cpp | 1714 const TargetRegisterClass *TRC =
1717 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), DL, MVT::i32);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | 379 const TargetRegisterClass *TRC = TRI->getPointerRegClass(*MF);
381 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i64);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.cpp | 2015 const TargetRegisterClass *TRC;
2017 TRC = &Hexagon::PredRegsRegClass;
2019 TRC = &Hexagon::IntRegsRegClass;
2021 TRC = &Hexagon::DoubleRegsRegClass;
2026 Register NewReg = MRI.createVirtualRegister(TRC);
|
