1 /* $NetBSD: if_urereg.h,v 1.2 2019/04/12 03:32:06 msaitoh Exp $ */ 2 /* $OpenBSD: if_urereg.h,v 1.5 2018/11/02 21:32:30 jcs Exp $ */ 3 /*- 4 * Copyright (c) 2015-2016 Kevin Lo <kevlo (at) FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #define URE_CONFIG_IDX 0 /* config number 1 */ 32 #define URE_IFACE_IDX 0 33 34 #define URE_CTL_READ 0x01 35 #define URE_CTL_WRITE 0x02 36 37 #define URE_TIMEOUT 1000 38 #define URE_PHY_TIMEOUT 2000 39 40 #define URE_BYTE_EN_DWORD 0xff 41 #define URE_BYTE_EN_WORD 0x33 42 #define URE_BYTE_EN_BYTE 0x11 43 #define URE_BYTE_EN_SIX_BYTES 0x3f 44 45 #define URE_MAX_FRAMELEN (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) 46 47 #define URE_PLA_IDR 0xc000 48 #define URE_PLA_RCR 0xc010 49 #define URE_PLA_RMS 0xc016 50 #define URE_PLA_RXFIFO_CTRL0 0xc0a0 51 #define URE_PLA_RXFIFO_CTRL1 0xc0a4 52 #define URE_PLA_RXFIFO_CTRL2 0xc0a8 53 #define URE_PLA_DMY_REG0 0xc0b0 54 #define URE_PLA_FMC 0xc0b4 55 #define URE_PLA_CFG_WOL 0xc0b6 56 #define URE_PLA_TEREDO_CFG 0xc0bc 57 #define URE_PLA_MAR0 0xcd00 58 #define URE_PLA_MAR4 0xcd04 59 #define URE_PLA_BACKUP 0xd000 60 #define URE_PLA_BDC_CR 0xd1a0 61 #define URE_PLA_TEREDO_TIMER 0xd2cc 62 #define URE_PLA_REALWOW_TIMER 0xd2e8 63 #define URE_PLA_LEDSEL 0xdd90 64 #define URE_PLA_LED_FEATURE 0xdd92 65 #define URE_PLA_PHYAR 0xde00 66 #define URE_PLA_BOOT_CTRL 0xe004 67 #define URE_PLA_GPHY_INTR_IMR 0xe022 68 #define URE_PLA_EEE_CR 0xe040 69 #define URE_PLA_EEEP_CR 0xe080 70 #define URE_PLA_MAC_PWR_CTRL 0xe0c0 71 #define URE_PLA_MAC_PWR_CTRL2 0xe0ca 72 #define URE_PLA_MAC_PWR_CTRL3 0xe0cc 73 #define URE_PLA_MAC_PWR_CTRL4 0xe0ce 74 #define URE_PLA_WDT6_CTRL 0xe428 75 #define URE_PLA_TCR0 0xe610 76 #define URE_PLA_TCR1 0xe612 77 #define URE_PLA_MTPS 0xe615 78 #define URE_PLA_TXFIFO_CTRL 0xe618 79 #define URE_PLA_RSTTELLY 0xe800 80 #define URE_PLA_CR 0xe813 81 #define URE_PLA_CRWECR 0xe81c 82 #define URE_PLA_CONFIG5 0xe822 83 #define URE_PLA_PHY_PWR 0xe84c 84 #define URE_PLA_OOB_CTRL 0xe84f 85 #define URE_PLA_CPCR 0xe854 86 #define URE_PLA_MISC_0 0xe858 87 #define URE_PLA_MISC_1 0xe85a 88 #define URE_PLA_OCP_GPHY_BASE 0xe86c 89 #define URE_PLA_TELLYCNT 0xe890 90 #define URE_PLA_SFF_STS_7 0xe8de 91 #define URE_PLA_PHYSTATUS 0xe908 92 93 #define URE_USB_USB2PHY 0xb41e 94 #define URE_USB_SSPHYLINK2 0xb428 95 #define URE_USB_U2P3_CTRL 0xb460 96 #define URE_USB_CSR_DUMMY1 0xb464 97 #define URE_USB_CSR_DUMMY2 0xb466 98 #define URE_USB_DEV_STAT 0xb808 99 #define URE_USB_CONNECT_TIMER 0xcbf8 100 #define URE_USB_BURST_SIZE 0xcfc0 101 #define URE_USB_USB_CTRL 0xd406 102 #define URE_USB_PHY_CTRL 0xd408 103 #define URE_USB_TX_AGG 0xd40a 104 #define URE_USB_RX_BUF_TH 0xd40c 105 #define URE_USB_USB_TIMER 0xd428 106 #define URE_USB_RX_EARLY_AGG 0xd42c 107 #define URE_USB_PM_CTRL_STATUS 0xd432 108 #define URE_USB_TX_DMA 0xd434 109 #define URE_USB_TOLERANCE 0xd490 110 #define URE_USB_LPM_CTRL 0xd41a 111 #define URE_USB_UPS_CTRL 0xd800 112 #define URE_USB_MISC_0 0xd81a 113 #define URE_USB_POWER_CUT 0xd80a 114 #define URE_USB_AFE_CTRL2 0xd824 115 #define URE_USB_WDT11_CTRL 0xe43c 116 117 /* OCP Registers. */ 118 #define URE_OCP_ALDPS_CONFIG 0x2010 119 #define URE_OCP_EEE_CONFIG1 0x2080 120 #define URE_OCP_EEE_CONFIG2 0x2092 121 #define URE_OCP_EEE_CONFIG3 0x2094 122 #define URE_OCP_BASE_MII 0xa400 123 #define URE_OCP_EEE_AR 0xa41a 124 #define URE_OCP_EEE_DATA 0xa41c 125 #define URE_OCP_PHY_STATUS 0xa420 126 #define URE_OCP_POWER_CFG 0xa430 127 #define URE_OCP_EEE_CFG 0xa432 128 #define URE_OCP_SRAM_ADDR 0xa436 129 #define URE_OCP_SRAM_DATA 0xa438 130 #define URE_OCP_DOWN_SPEED 0xa442 131 #define URE_OCP_EEE_ABLE 0xa5c4 132 #define URE_OCP_EEE_ADV 0xa5d0 133 #define URE_OCP_EEE_LPABLE 0xa5d2 134 #define URE_OCP_PHY_STATE 0xa708 135 #define URE_OCP_ADC_CFG 0xbc06 136 137 /* SRAM Register. */ 138 #define URE_SRAM_LPF_CFG 0x8012 139 #define URE_SRAM_10M_AMP1 0x8080 140 #define URE_SRAM_10M_AMP2 0x8082 141 #define URE_SRAM_IMPEDANCE 0x8084 142 143 /* PLA_RCR */ 144 #define URE_RCR_AAP 0x00000001 145 #define URE_RCR_APM 0x00000002 146 #define URE_RCR_AM 0x00000004 147 #define URE_RCR_AB 0x00000008 148 #define URE_RCR_ACPT_ALL \ 149 (URE_RCR_AAP | URE_RCR_APM | URE_RCR_AM | URE_RCR_AB) 150 151 /* PLA_RXFIFO_CTRL0 */ 152 #define URE_RXFIFO_THR1_NORMAL 0x00080002 153 #define URE_RXFIFO_THR1_OOB 0x01800003 154 155 /* PLA_RXFIFO_CTRL1 */ 156 #define URE_RXFIFO_THR2_FULL 0x00000060 157 #define URE_RXFIFO_THR2_HIGH 0x00000038 158 #define URE_RXFIFO_THR2_OOB 0x0000004a 159 #define URE_RXFIFO_THR2_NORMAL 0x00a0 160 161 /* PLA_RXFIFO_CTRL2 */ 162 #define URE_RXFIFO_THR3_FULL 0x00000078 163 #define URE_RXFIFO_THR3_HIGH 0x00000048 164 #define URE_RXFIFO_THR3_OOB 0x0000005a 165 #define URE_RXFIFO_THR3_NORMAL 0x0110 166 167 /* PLA_TXFIFO_CTRL */ 168 #define URE_TXFIFO_THR_NORMAL 0x00400008 169 #define URE_TXFIFO_THR_NORMAL2 0x01000008 170 171 /* PLA_DMY_REG0 */ 172 #define URE_ECM_ALDPS 0x0002 173 174 /* PLA_FMC */ 175 #define URE_FMC_FCR_MCU_EN 0x0001 176 177 /* PLA_EEEP_CR */ 178 #define URE_EEEP_CR_EEEP_TX 0x0002 179 180 /* PLA_WDT6_CTRL */ 181 #define URE_WDT6_SET_MODE 0x0010 182 183 /* PLA_TCR0 */ 184 #define URE_TCR0_TX_EMPTY 0x0800 185 #define URE_TCR0_AUTO_FIFO 0x0080 186 187 /* PLA_TCR1 */ 188 #define URE_VERSION_MASK 0x7cf0 189 190 /* PLA_CR */ 191 #define URE_CR_RST 0x10 192 #define URE_CR_RE 0x08 193 #define URE_CR_TE 0x04 194 195 /* PLA_CRWECR */ 196 #define URE_CRWECR_NORAML 0x00 197 #define URE_CRWECR_CONFIG 0xc0 198 199 /* PLA_OOB_CTRL */ 200 #define URE_NOW_IS_OOB 0x80 201 #define URE_TXFIFO_EMPTY 0x20 202 #define URE_RXFIFO_EMPTY 0x10 203 #define URE_LINK_LIST_READY 0x02 204 #define URE_DIS_MCU_CLROOB 0x01 205 #define URE_FIFO_EMPTY (URE_TXFIFO_EMPTY | URE_RXFIFO_EMPTY) 206 207 /* PLA_MISC_1 */ 208 #define URE_RXDY_GATED_EN 0x0008 209 210 /* PLA_SFF_STS_7 */ 211 #define URE_RE_INIT_LL 0x8000 212 #define URE_MCU_BORW_EN 0x4000 213 214 /* PLA_CPCR */ 215 #define URE_CPCR_RX_VLAN 0x0040 216 217 /* PLA_TEREDO_CFG */ 218 #define URE_TEREDO_SEL 0x8000 219 #define URE_TEREDO_WAKE_MASK 0x7f00 220 #define URE_TEREDO_RS_EVENT_MASK 0x00fe 221 #define URE_OOB_TEREDO_EN 0x0001 222 223 /* PAL_BDC_CR */ 224 #define URE_ALDPS_PROXY_MODE 0x0001 225 226 /* PLA_CONFIG5 */ 227 #define URE_LAN_WAKE_EN 0x0002 228 229 /* PLA_LED_FEATURE */ 230 #define URE_LED_MODE_MASK 0x0700 231 232 /* PLA_PHY_PWR */ 233 #define URE_TX_10M_IDLE_EN 0x0080 234 #define URE_PFM_PWM_SWITCH 0x0040 235 236 /* PLA_MAC_PWR_CTRL */ 237 #define URE_D3_CLK_GATED_EN 0x00004000 238 #define URE_MCU_CLK_RATIO 0x07010f07 239 #define URE_MCU_CLK_RATIO_MASK 0x0f0f0f0f 240 #define URE_ALDPS_SPDWN_RATIO 0x0f87 241 242 /* PLA_MAC_PWR_CTRL2 */ 243 #define URE_EEE_SPDWN_RATIO 0x8007 244 245 /* PLA_MAC_PWR_CTRL3 */ 246 #define URE_PKT_AVAIL_SPDWN_EN 0x0100 247 #define URE_SUSPEND_SPDWN_EN 0x0004 248 #define URE_U1U2_SPDWN_EN 0x0002 249 #define URE_L1_SPDWN_EN 0x0001 250 251 /* PLA_MAC_PWR_CTRL4 */ 252 #define URE_PWRSAVE_SPDWN_EN 0x1000 253 #define URE_RXDV_SPDWN_EN 0x0800 254 #define URE_TX10MIDLE_EN 0x0100 255 #define URE_TP100_SPDWN_EN 0x0020 256 #define URE_TP500_SPDWN_EN 0x0010 257 #define URE_TP1000_SPDWN_EN 0x0008 258 #define URE_EEE_SPDWN_EN 0x0001 259 260 /* PLA_GPHY_INTR_IMR */ 261 #define URE_GPHY_STS_MSK 0x0001 262 #define URE_SPEED_DOWN_MSK 0x0002 263 #define URE_SPDWN_RXDV_MSK 0x0004 264 #define URE_SPDWN_LINKCHG_MSK 0x0008 265 266 /* PLA_PHYAR */ 267 #define URE_PHYAR_PHYDATA 0x0000ffff 268 #define URE_PHYAR_BUSY 0x80000000 269 270 /* PLA_EEE_CR */ 271 #define URE_EEE_RX_EN 0x0001 272 #define URE_EEE_TX_EN 0x0002 273 274 /* PLA_BOOT_CTRL */ 275 #define URE_AUTOLOAD_DONE 0x0002 276 277 /* USB_USB2PHY */ 278 #define URE_USB2PHY_SUSPEND 0x0001 279 #define URE_USB2PHY_L1 0x0002 280 281 /* USB_SSPHYLINK2 */ 282 #define URE_PWD_DN_SCALE_MASK 0x3ffe 283 #define URE_PWD_DN_SCALE(x) ((x) << 1) 284 285 /* USB_CSR_DUMMY1 */ 286 #define URE_DYNAMIC_BURST 0x0001 287 288 /* USB_CSR_DUMMY2 */ 289 #define URE_EP4_FULL_FC 0x0001 290 291 /* USB_DEV_STAT */ 292 #define URE_STAT_SPEED_MASK 0x0006 293 #define URE_STAT_SPEED_HIGH 0x0000 294 #define URE_STAT_SPEED_FULL 0x0001 295 296 /* USB_TX_AGG */ 297 #define URE_TX_AGG_MAX_THRESHOLD 0x03 298 299 /* USB_RX_BUF_TH */ 300 #define URE_RX_THR_SUPER 0x0c350180 301 #define URE_RX_THR_HIGH 0x7a120180 302 #define URE_RX_THR_SLOW 0xffff0180 303 304 /* USB_TX_DMA */ 305 #define URE_TEST_MODE_DISABLE 0x00000001 306 #define URE_TX_SIZE_ADJUST1 0x00000100 307 308 /* USB_UPS_CTRL */ 309 #define URE_POWER_CUT 0x0100 310 311 /* USB_PM_CTRL_STATUS */ 312 #define URE_RESUME_INDICATE 0x0001 313 314 /* USB_USB_CTRL */ 315 #define URE_RX_AGG_DISABLE 0x0010 316 #define URE_RX_ZERO_EN 0x0080 317 318 /* USB_U2P3_CTRL */ 319 #define URE_U2P3_ENABLE 0x0001 320 321 /* USB_POWER_CUT */ 322 #define URE_PWR_EN 0x0001 323 #define URE_PHASE2_EN 0x0008 324 325 /* USB_MISC_0 */ 326 #define URE_PCUT_STATUS 0x0001 327 328 /* USB_RX_EARLY_TIMEOUT */ 329 #define URE_COALESCE_SUPER 85000U 330 #define URE_COALESCE_HIGH 250000U 331 #define URE_COALESCE_SLOW 524280U 332 333 /* USB_WDT11_CTRL */ 334 #define URE_TIMER11_EN 0x0001 335 336 /* USB_LPM_CTRL */ 337 #define URE_FIFO_EMPTY_1FB 0x30 338 #define URE_LPM_TIMER_MASK 0x0c 339 #define URE_LPM_TIMER_500MS 0x04 340 #define URE_LPM_TIMER_500US 0x0c 341 #define URE_ROK_EXIT_LPM 0x02 342 343 /* USB_AFE_CTRL2 */ 344 #define URE_SEN_VAL_MASK 0xf800 345 #define URE_SEN_VAL_NORMAL 0xa000 346 #define URE_SEL_RXIDLE 0x0100 347 348 /* OCP_ALDPS_CONFIG */ 349 #define URE_ENPWRSAVE 0x8000 350 #define URE_ENPDNPS 0x0200 351 #define URE_LINKENA 0x0100 352 #define URE_DIS_SDSAVE 0x0010 353 354 /* OCP_PHY_STATUS */ 355 #define URE_PHY_STAT_MASK 0x0007 356 #define URE_PHY_STAT_LAN_ON 3 357 #define URE_PHY_STAT_PWRDN 5 358 359 /* OCP_POWER_CFG */ 360 #define URE_EEE_CLKDIV_EN 0x8000 361 #define URE_EN_ALDPS 0x0004 362 #define URE_EN_10M_PLLOFF 0x0001 363 364 /* OCP_EEE_CFG */ 365 #define URE_CTAP_SHORT_EN 0x0040 366 #define URE_EEE10_EN 0x0010 367 368 /* OCP_DOWN_SPEED */ 369 #define URE_EN_10M_BGOFF 0x0080 370 371 /* OCP_PHY_STATE */ 372 #define URE_TXDIS_STATE 0x01 373 #define URE_ABD_STATE 0x02 374 375 /* OCP_ADC_CFG */ 376 #define URE_CKADSEL_L 0x0100 377 #define URE_ADC_EN 0x0080 378 #define URE_EN_EMI_L 0x0040 379 380 #define URE_MCU_TYPE_PLA 0x0100 381 #define URE_MCU_TYPE_USB 0x0000 382
Indexes created Mon Sep 29 21:09:56 GMT 2025