1 /* $NetBSD: qcom,gcc-ipq806x.h,v 1.1.1.2 2020/01/03 14:33:05 skrll Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0-only */ 4 /* 5 * Copyright (c) 2014, The Linux Foundation. All rights reserved. 6 */ 7 8 #ifndef _DT_BINDINGS_CLK_GCC_IPQ806X_H 9 #define _DT_BINDINGS_CLK_GCC_IPQ806X_H 10 11 #define AFAB_CLK_SRC 0 12 #define QDSS_STM_CLK 1 13 #define SCSS_A_CLK 2 14 #define SCSS_H_CLK 3 15 #define AFAB_CORE_CLK 4 16 #define SCSS_XO_SRC_CLK 5 17 #define AFAB_EBI1_CH0_A_CLK 6 18 #define AFAB_EBI1_CH1_A_CLK 7 19 #define AFAB_AXI_S0_FCLK 8 20 #define AFAB_AXI_S1_FCLK 9 21 #define AFAB_AXI_S2_FCLK 10 22 #define AFAB_AXI_S3_FCLK 11 23 #define AFAB_AXI_S4_FCLK 12 24 #define SFAB_CORE_CLK 13 25 #define SFAB_AXI_S0_FCLK 14 26 #define SFAB_AXI_S1_FCLK 15 27 #define SFAB_AXI_S2_FCLK 16 28 #define SFAB_AXI_S3_FCLK 17 29 #define SFAB_AXI_S4_FCLK 18 30 #define SFAB_AXI_S5_FCLK 19 31 #define SFAB_AHB_S0_FCLK 20 32 #define SFAB_AHB_S1_FCLK 21 33 #define SFAB_AHB_S2_FCLK 22 34 #define SFAB_AHB_S3_FCLK 23 35 #define SFAB_AHB_S4_FCLK 24 36 #define SFAB_AHB_S5_FCLK 25 37 #define SFAB_AHB_S6_FCLK 26 38 #define SFAB_AHB_S7_FCLK 27 39 #define QDSS_AT_CLK_SRC 28 40 #define QDSS_AT_CLK 29 41 #define QDSS_TRACECLKIN_CLK_SRC 30 42 #define QDSS_TRACECLKIN_CLK 31 43 #define QDSS_TSCTR_CLK_SRC 32 44 #define QDSS_TSCTR_CLK 33 45 #define SFAB_ADM0_M0_A_CLK 34 46 #define SFAB_ADM0_M1_A_CLK 35 47 #define SFAB_ADM0_M2_H_CLK 36 48 #define ADM0_CLK 37 49 #define ADM0_PBUS_CLK 38 50 #define IMEM0_A_CLK 39 51 #define QDSS_H_CLK 40 52 #define PCIE_A_CLK 41 53 #define PCIE_AUX_CLK 42 54 #define PCIE_H_CLK 43 55 #define PCIE_PHY_CLK 44 56 #define SFAB_CLK_SRC 45 57 #define SFAB_LPASS_Q6_A_CLK 46 58 #define SFAB_AFAB_M_A_CLK 47 59 #define AFAB_SFAB_M0_A_CLK 48 60 #define AFAB_SFAB_M1_A_CLK 49 61 #define SFAB_SATA_S_H_CLK 50 62 #define DFAB_CLK_SRC 51 63 #define DFAB_CLK 52 64 #define SFAB_DFAB_M_A_CLK 53 65 #define DFAB_SFAB_M_A_CLK 54 66 #define DFAB_SWAY0_H_CLK 55 67 #define DFAB_SWAY1_H_CLK 56 68 #define DFAB_ARB0_H_CLK 57 69 #define DFAB_ARB1_H_CLK 58 70 #define PPSS_H_CLK 59 71 #define PPSS_PROC_CLK 60 72 #define PPSS_TIMER0_CLK 61 73 #define PPSS_TIMER1_CLK 62 74 #define PMEM_A_CLK 63 75 #define DMA_BAM_H_CLK 64 76 #define SIC_H_CLK 65 77 #define SPS_TIC_H_CLK 66 78 #define CFPB_2X_CLK_SRC 67 79 #define CFPB_CLK 68 80 #define CFPB0_H_CLK 69 81 #define CFPB1_H_CLK 70 82 #define CFPB2_H_CLK 71 83 #define SFAB_CFPB_M_H_CLK 72 84 #define CFPB_MASTER_H_CLK 73 85 #define SFAB_CFPB_S_H_CLK 74 86 #define CFPB_SPLITTER_H_CLK 75 87 #define TSIF_H_CLK 76 88 #define TSIF_INACTIVITY_TIMERS_CLK 77 89 #define TSIF_REF_SRC 78 90 #define TSIF_REF_CLK 79 91 #define CE1_H_CLK 80 92 #define CE1_CORE_CLK 81 93 #define CE1_SLEEP_CLK 82 94 #define CE2_H_CLK 83 95 #define CE2_CORE_CLK 84 96 #define SFPB_H_CLK_SRC 85 97 #define SFPB_H_CLK 86 98 #define SFAB_SFPB_M_H_CLK 87 99 #define SFAB_SFPB_S_H_CLK 88 100 #define RPM_PROC_CLK 89 101 #define RPM_BUS_H_CLK 90 102 #define RPM_SLEEP_CLK 91 103 #define RPM_TIMER_CLK 92 104 #define RPM_MSG_RAM_H_CLK 93 105 #define PMIC_ARB0_H_CLK 94 106 #define PMIC_ARB1_H_CLK 95 107 #define PMIC_SSBI2_SRC 96 108 #define PMIC_SSBI2_CLK 97 109 #define SDC1_H_CLK 98 110 #define SDC2_H_CLK 99 111 #define SDC3_H_CLK 100 112 #define SDC4_H_CLK 101 113 #define SDC1_SRC 102 114 #define SDC1_CLK 103 115 #define SDC2_SRC 104 116 #define SDC2_CLK 105 117 #define SDC3_SRC 106 118 #define SDC3_CLK 107 119 #define SDC4_SRC 108 120 #define SDC4_CLK 109 121 #define USB_HS1_H_CLK 110 122 #define USB_HS1_XCVR_SRC 111 123 #define USB_HS1_XCVR_CLK 112 124 #define USB_HSIC_H_CLK 113 125 #define USB_HSIC_XCVR_SRC 114 126 #define USB_HSIC_XCVR_CLK 115 127 #define USB_HSIC_SYSTEM_CLK_SRC 116 128 #define USB_HSIC_SYSTEM_CLK 117 129 #define CFPB0_C0_H_CLK 118 130 #define CFPB0_D0_H_CLK 119 131 #define CFPB0_C1_H_CLK 120 132 #define CFPB0_D1_H_CLK 121 133 #define USB_FS1_H_CLK 122 134 #define USB_FS1_XCVR_SRC 123 135 #define USB_FS1_XCVR_CLK 124 136 #define USB_FS1_SYSTEM_CLK 125 137 #define GSBI_COMMON_SIM_SRC 126 138 #define GSBI1_H_CLK 127 139 #define GSBI2_H_CLK 128 140 #define GSBI3_H_CLK 129 141 #define GSBI4_H_CLK 130 142 #define GSBI5_H_CLK 131 143 #define GSBI6_H_CLK 132 144 #define GSBI7_H_CLK 133 145 #define GSBI1_QUP_SRC 134 146 #define GSBI1_QUP_CLK 135 147 #define GSBI2_QUP_SRC 136 148 #define GSBI2_QUP_CLK 137 149 #define GSBI3_QUP_SRC 138 150 #define GSBI3_QUP_CLK 139 151 #define GSBI4_QUP_SRC 140 152 #define GSBI4_QUP_CLK 141 153 #define GSBI5_QUP_SRC 142 154 #define GSBI5_QUP_CLK 143 155 #define GSBI6_QUP_SRC 144 156 #define GSBI6_QUP_CLK 145 157 #define GSBI7_QUP_SRC 146 158 #define GSBI7_QUP_CLK 147 159 #define GSBI1_UART_SRC 148 160 #define GSBI1_UART_CLK 149 161 #define GSBI2_UART_SRC 150 162 #define GSBI2_UART_CLK 151 163 #define GSBI3_UART_SRC 152 164 #define GSBI3_UART_CLK 153 165 #define GSBI4_UART_SRC 154 166 #define GSBI4_UART_CLK 155 167 #define GSBI5_UART_SRC 156 168 #define GSBI5_UART_CLK 157 169 #define GSBI6_UART_SRC 158 170 #define GSBI6_UART_CLK 159 171 #define GSBI7_UART_SRC 160 172 #define GSBI7_UART_CLK 161 173 #define GSBI1_SIM_CLK 162 174 #define GSBI2_SIM_CLK 163 175 #define GSBI3_SIM_CLK 164 176 #define GSBI4_SIM_CLK 165 177 #define GSBI5_SIM_CLK 166 178 #define GSBI6_SIM_CLK 167 179 #define GSBI7_SIM_CLK 168 180 #define USB_HSIC_HSIC_CLK_SRC 169 181 #define USB_HSIC_HSIC_CLK 170 182 #define USB_HSIC_HSIO_CAL_CLK 171 183 #define SPDM_CFG_H_CLK 172 184 #define SPDM_MSTR_H_CLK 173 185 #define SPDM_FF_CLK_SRC 174 186 #define SPDM_FF_CLK 175 187 #define SEC_CTRL_CLK 176 188 #define SEC_CTRL_ACC_CLK_SRC 177 189 #define SEC_CTRL_ACC_CLK 178 190 #define TLMM_H_CLK 179 191 #define TLMM_CLK 180 192 #define SATA_H_CLK 181 193 #define SATA_CLK_SRC 182 194 #define SATA_RXOOB_CLK 183 195 #define SATA_PMALIVE_CLK 184 196 #define SATA_PHY_REF_CLK 185 197 #define SATA_A_CLK 186 198 #define SATA_PHY_CFG_CLK 187 199 #define TSSC_CLK_SRC 188 200 #define TSSC_CLK 189 201 #define PDM_SRC 190 202 #define PDM_CLK 191 203 #define GP0_SRC 192 204 #define GP0_CLK 193 205 #define GP1_SRC 194 206 #define GP1_CLK 195 207 #define GP2_SRC 196 208 #define GP2_CLK 197 209 #define MPM_CLK 198 210 #define EBI1_CLK_SRC 199 211 #define EBI1_CH0_CLK 200 212 #define EBI1_CH1_CLK 201 213 #define EBI1_2X_CLK 202 214 #define EBI1_CH0_DQ_CLK 203 215 #define EBI1_CH1_DQ_CLK 204 216 #define EBI1_CH0_CA_CLK 205 217 #define EBI1_CH1_CA_CLK 206 218 #define EBI1_XO_CLK 207 219 #define SFAB_SMPSS_S_H_CLK 208 220 #define PRNG_SRC 209 221 #define PRNG_CLK 210 222 #define PXO_SRC 211 223 #define SPDM_CY_PORT0_CLK 212 224 #define SPDM_CY_PORT1_CLK 213 225 #define SPDM_CY_PORT2_CLK 214 226 #define SPDM_CY_PORT3_CLK 215 227 #define SPDM_CY_PORT4_CLK 216 228 #define SPDM_CY_PORT5_CLK 217 229 #define SPDM_CY_PORT6_CLK 218 230 #define SPDM_CY_PORT7_CLK 219 231 #define PLL0 220 232 #define PLL0_VOTE 221 233 #define PLL3 222 234 #define PLL3_VOTE 223 235 #define PLL4_VOTE 225 236 #define PLL8 226 237 #define PLL8_VOTE 227 238 #define PLL9 228 239 #define PLL10 229 240 #define PLL11 230 241 #define PLL12 231 242 #define PLL14 232 243 #define PLL14_VOTE 233 244 #define PLL18 234 245 #define CE5_SRC 235 246 #define CE5_H_CLK 236 247 #define CE5_CORE_CLK 237 248 #define CE3_SLEEP_CLK 238 249 #define SFAB_AHB_S8_FCLK 239 250 #define SPDM_CY_PORT8_CLK 246 251 #define PCIE_ALT_REF_SRC 247 252 #define PCIE_ALT_REF_CLK 248 253 #define PCIE_1_A_CLK 249 254 #define PCIE_1_AUX_CLK 250 255 #define PCIE_1_H_CLK 251 256 #define PCIE_1_PHY_CLK 252 257 #define PCIE_1_ALT_REF_SRC 253 258 #define PCIE_1_ALT_REF_CLK 254 259 #define PCIE_2_A_CLK 255 260 #define PCIE_2_AUX_CLK 256 261 #define PCIE_2_H_CLK 257 262 #define PCIE_2_PHY_CLK 258 263 #define PCIE_2_ALT_REF_SRC 259 264 #define PCIE_2_ALT_REF_CLK 260 265 #define EBI2_CLK 261 266 #define USB30_SLEEP_CLK 262 267 #define USB30_UTMI_SRC 263 268 #define USB30_0_UTMI_CLK 264 269 #define USB30_1_UTMI_CLK 265 270 #define USB30_MASTER_SRC 266 271 #define USB30_0_MASTER_CLK 267 272 #define USB30_1_MASTER_CLK 268 273 #define GMAC_CORE1_CLK_SRC 269 274 #define GMAC_CORE2_CLK_SRC 270 275 #define GMAC_CORE3_CLK_SRC 271 276 #define GMAC_CORE4_CLK_SRC 272 277 #define GMAC_CORE1_CLK 273 278 #define GMAC_CORE2_CLK 274 279 #define GMAC_CORE3_CLK 275 280 #define GMAC_CORE4_CLK 276 281 #define UBI32_CORE1_CLK_SRC 277 282 #define UBI32_CORE2_CLK_SRC 278 283 #define UBI32_CORE1_CLK 279 284 #define UBI32_CORE2_CLK 280 285 #define EBI2_AON_CLK 281 286 #define NSSTCM_CLK_SRC 282 287 #define NSSTCM_CLK 283 288 289 #endif 290
Indexes created Tue Sep 30 11:09:46 GMT 2025