1 /* $NetBSD: sun50i_h6_ccu.c,v 1.4 2021/01/27 03:10:20 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(1, "$NetBSD: sun50i_h6_ccu.c,v 1.4 2021/01/27 03:10:20 thorpej Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/systm.h> 37 38 #include <dev/fdt/fdtvar.h> 39 40 #include <arm/sunxi/sunxi_ccu.h> 41 #include <arm/sunxi/sun50i_h6_ccu.h> 42 43 #define PLL_CPUX_CTRL_REG 0x000 44 #define PLL_PERI0_CTRL_REG 0x020 45 #define PSI_AHB1_AHB2_CFG_REG 0x510 46 #define AHB3_CFG_REG 0x51c 47 #define APB2_CFG_REG 0x524 48 #define MBUS_CFG_REG 0x540 49 #define DE_BGR_REG 0x60c 50 #define DI_BGR_REG 0x62c 51 #define GPU_BGR_REG 0x67c 52 #define CE_BGR_REG 0x68c 53 #define VE_BGR_REG 0x69c 54 #define EMCE_BGR_REG 0x6bc 55 #define VP9_BGR_REG 0x6cc 56 #define DMA_BGR_REG 0x70c 57 #define MSGBOX_BGR_REG 0x71c 58 #define SPINLOCK_BGR_REG 0x72c 59 #define HSTIMER_BGR_REG 0x73c 60 #define DBGSYS_BGR_REG 0x78c 61 #define PSI_BGR_REG 0x79c 62 #define PWM_BGR_REG 0x7ac 63 #define DRAM_CLK_REG 0x800 64 #define NAND_BGR_REG 0x82c 65 #define SMHC0_CLK_REG 0x830 66 #define SMHC1_CLK_REG 0x834 67 #define SMHC2_CLK_REG 0x838 68 #define SMHC_BGR_REG 0x84c 69 #define UART_BGR_REG 0x90c 70 #define TWI_BGR_REG 0x91c 71 #define SCR_BGR_REG 0x93c 72 #define SPI_BGR_REG 0x96c 73 #define EMAC_BGR_REG 0x97c 74 #define TS_BGR_REG 0x9bc 75 #define CIRTX_BGR_REG 0x9cc 76 #define THS_BGR_REG 0x9fc 77 #define I2S_PCM_BGR_REG 0xa1c 78 #define OWA_BGR_REG 0xa2c 79 #define DMIC_BGR_REG 0xa4c 80 #define AUDIO_HUB_BGR_REG 0xa6c 81 #define USB0_CLK_REG 0xa70 82 #define USB1_CLK_REG 0xa74 83 #define USB3_CLK_REG 0xa7c 84 #define USB_BGR_REG 0xa8c 85 #define PCIE_REF_CLK_REG 0xab0 86 #define PCIE_AXI_CLK_REG 0xab4 87 #define PCIE_AUX_CLK_REG 0xab8 88 #define PCIE_BGR_REG 0xabc 89 #define HDMI_BGR_REG 0xb1c 90 #define DISPLAY_IF_TOP_BGR_REG 0xb5c 91 #define TCON_LCD_BGR_REG 0xb7c 92 #define TCON_TV_BGR_REG 0xb9c 93 #define CSI_BGR_REG 0xc2c 94 #define HDMI_HDCP_BGR_REG 0xc4c 95 96 static int sun50i_h6_ccu_match(device_t, cfdata_t, void *); 97 static void sun50i_h6_ccu_attach(device_t, device_t, void *); 98 99 static const struct device_compatible_entry compat_data[] = { 100 { .compat = "allwinner,sun50i-h6-ccu" }, 101 DEVICE_COMPAT_EOL 102 }; 103 104 CFATTACH_DECL_NEW(sunxi_h6_ccu, sizeof(struct sunxi_ccu_softc), 105 sun50i_h6_ccu_match, sun50i_h6_ccu_attach, NULL, NULL); 106 107 static struct sunxi_ccu_reset sun50i_h6_ccu_resets[] = { 108 SUNXI_CCU_RESET(H6_RST_MBUS, MBUS_CFG_REG, 30), 109 110 SUNXI_CCU_RESET(H6_RST_BUS_DE, DE_BGR_REG, 16), 111 112 SUNXI_CCU_RESET(H6_RST_BUS_DEINTERLACE, DI_BGR_REG, 16), 113 114 SUNXI_CCU_RESET(H6_RST_BUS_GPU, GPU_BGR_REG, 16), 115 116 SUNXI_CCU_RESET(H6_RST_BUS_CE, CE_BGR_REG, 16), 117 118 SUNXI_CCU_RESET(H6_RST_BUS_VE, VE_BGR_REG, 16), 119 120 SUNXI_CCU_RESET(H6_RST_BUS_EMCE, EMCE_BGR_REG, 16), 121 122 SUNXI_CCU_RESET(H6_RST_BUS_VP9, VP9_BGR_REG, 16), 123 124 SUNXI_CCU_RESET(H6_RST_BUS_DMA, DMA_BGR_REG, 16), 125 126 SUNXI_CCU_RESET(H6_RST_BUS_MSGBOX, MSGBOX_BGR_REG, 16), 127 128 SUNXI_CCU_RESET(H6_RST_BUS_SPINLOCK, SPINLOCK_BGR_REG, 16), 129 130 SUNXI_CCU_RESET(H6_RST_BUS_HSTIMER, HSTIMER_BGR_REG, 16), 131 132 SUNXI_CCU_RESET(H6_RST_BUS_DBG, DBGSYS_BGR_REG, 16), 133 134 SUNXI_CCU_RESET(H6_RST_BUS_PSI, PSI_BGR_REG, 16), 135 136 SUNXI_CCU_RESET(H6_RST_BUS_PWM, PWM_BGR_REG, 16), 137 138 /* H6_RST_BUS_IOMMU: No bit defined in user manual */ 139 140 SUNXI_CCU_RESET(H6_RST_BUS_DRAM, DRAM_CLK_REG, 30), 141 142 SUNXI_CCU_RESET(H6_RST_BUS_NAND, NAND_BGR_REG, 16), 143 144 SUNXI_CCU_RESET(H6_RST_BUS_MMC0, SMHC_BGR_REG, 16), 145 SUNXI_CCU_RESET(H6_RST_BUS_MMC1, SMHC_BGR_REG, 17), 146 SUNXI_CCU_RESET(H6_RST_BUS_MMC2, SMHC_BGR_REG, 18), 147 148 SUNXI_CCU_RESET(H6_RST_BUS_UART0, UART_BGR_REG, 16), 149 SUNXI_CCU_RESET(H6_RST_BUS_UART1, UART_BGR_REG, 17), 150 SUNXI_CCU_RESET(H6_RST_BUS_UART2, UART_BGR_REG, 18), 151 SUNXI_CCU_RESET(H6_RST_BUS_UART3, UART_BGR_REG, 19), 152 153 SUNXI_CCU_RESET(H6_RST_BUS_I2C0, TWI_BGR_REG, 16), 154 SUNXI_CCU_RESET(H6_RST_BUS_I2C1, TWI_BGR_REG, 17), 155 SUNXI_CCU_RESET(H6_RST_BUS_I2C2, TWI_BGR_REG, 18), 156 SUNXI_CCU_RESET(H6_RST_BUS_I2C3, TWI_BGR_REG, 19), 157 158 SUNXI_CCU_RESET(H6_RST_BUS_SCR0, SCR_BGR_REG, 16), 159 SUNXI_CCU_RESET(H6_RST_BUS_SCR1, SCR_BGR_REG, 17), 160 161 SUNXI_CCU_RESET(H6_RST_BUS_SPI0, SPI_BGR_REG, 16), 162 SUNXI_CCU_RESET(H6_RST_BUS_SPI1, SPI_BGR_REG, 17), 163 164 SUNXI_CCU_RESET(H6_RST_BUS_EMAC, EMAC_BGR_REG, 16), 165 166 SUNXI_CCU_RESET(H6_RST_BUS_TS, TS_BGR_REG, 16), 167 168 SUNXI_CCU_RESET(H6_RST_BUS_IR_TX, CIRTX_BGR_REG, 16), 169 170 SUNXI_CCU_RESET(H6_RST_BUS_THS, THS_BGR_REG, 16), 171 172 SUNXI_CCU_RESET(H6_RST_BUS_I2S0, I2S_PCM_BGR_REG, 16), 173 SUNXI_CCU_RESET(H6_RST_BUS_I2S1, I2S_PCM_BGR_REG, 17), 174 SUNXI_CCU_RESET(H6_RST_BUS_I2S2, I2S_PCM_BGR_REG, 18), 175 SUNXI_CCU_RESET(H6_RST_BUS_I2S3, I2S_PCM_BGR_REG, 19), 176 177 SUNXI_CCU_RESET(H6_RST_BUS_SPDIF, OWA_BGR_REG, 16), 178 179 SUNXI_CCU_RESET(H6_RST_BUS_DMIC, DMIC_BGR_REG, 16), 180 181 SUNXI_CCU_RESET(H6_RST_BUS_AUDIO_HUB, AUDIO_HUB_BGR_REG, 16), 182 183 SUNXI_CCU_RESET(H6_RST_USB_PHY0, USB0_CLK_REG, 30), 184 185 SUNXI_CCU_RESET(H6_RST_USB_PHY1, USB1_CLK_REG, 30), 186 187 SUNXI_CCU_RESET(H6_RST_USB_PHY3, USB3_CLK_REG, 30), 188 SUNXI_CCU_RESET(H6_RST_USB_HSIC, USB3_CLK_REG, 28), 189 190 SUNXI_CCU_RESET(H6_RST_BUS_OHCI0, USB_BGR_REG, 16), 191 SUNXI_CCU_RESET(H6_RST_BUS_OHCI3, USB_BGR_REG, 19), 192 SUNXI_CCU_RESET(H6_RST_BUS_EHCI0, USB_BGR_REG, 20), 193 SUNXI_CCU_RESET(H6_RST_BUS_XHCI, USB_BGR_REG, 21), 194 SUNXI_CCU_RESET(H6_RST_BUS_EHCI3, USB_BGR_REG, 23), 195 SUNXI_CCU_RESET(H6_RST_BUS_OTG, USB_BGR_REG, 24), 196 197 SUNXI_CCU_RESET(H6_RST_BUS_PCIE, PCIE_BGR_REG, 16), 198 SUNXI_CCU_RESET(H6_RST_PCIE_POWERUP, PCIE_BGR_REG, 17), 199 200 SUNXI_CCU_RESET(H6_RST_BUS_HDMI, HDMI_BGR_REG, 16), 201 SUNXI_CCU_RESET(H6_RST_BUS_HDMI_SUB, HDMI_BGR_REG, 17), 202 203 SUNXI_CCU_RESET(H6_RST_BUS_TCON_TOP, DISPLAY_IF_TOP_BGR_REG, 16), 204 205 SUNXI_CCU_RESET(H6_RST_BUS_TCON_LCD0, TCON_LCD_BGR_REG, 16), 206 207 SUNXI_CCU_RESET(H6_RST_BUS_TCON_TV0, TCON_TV_BGR_REG, 16), 208 209 SUNXI_CCU_RESET(H6_RST_BUS_CSI, CSI_BGR_REG, 16), 210 211 SUNXI_CCU_RESET(H6_RST_BUS_HDCP, HDMI_HDCP_BGR_REG, 16), 212 }; 213 214 static const char *ahb3_parents[] = { "hosc", "losc", "psi", "pll_periph0" }; 215 static const char *apb2_parents[] = { "hosc", "losc", "psi", "pll_periph0" }; 216 static const char *mod_parents[] = { "hosc", "pll_periph0_2x", "pll_periph1_2x" }; 217 static const char *hosc_parent[] = { "hosc" }; 218 static const char *pll_periph0_parent[] = { "pll_periph0" }; 219 static const char *psi_ahb1_ahb2_parents[] = { "hosc", "losc", "iosc", "pll_periph0" }; 220 221 static struct sunxi_ccu_clk sun50i_h6_ccu_clks[] = { 222 SUNXI_CCU_FIXED_FACTOR(H6_CLK_OSC12M, "osc12m", "hosc", 2, 1), 223 224 SUNXI_CCU_NKMP_TABLE(H6_CLK_PLL_CPUX, "pll_cpux", "hosc", 225 PLL_CPUX_CTRL_REG, /* reg */ 226 __BITS(15,8), /* n */ 227 0, /* k */ 228 __BITS(1,0), /* m */ 229 __BITS(17,16), /* p */ 230 __BIT(31), /* enable */ 231 __BIT(28), /* lock */ 232 NULL, /* table */ 233 SUNXI_CCU_NKMP_SCALE_CLOCK | SUNXI_CCU_NKMP_FACTOR_P_POW2), 234 235 SUNXI_CCU_NKMP(H6_CLK_PLL_PERIPH0_4X, "pll_periph0_4x", "hosc", 236 PLL_PERI0_CTRL_REG, /* reg */ 237 __BITS(15,8), /* n */ 238 0, /* k */ 239 __BIT(1), /* m */ 240 __BIT(0), /* p */ 241 __BIT(31), /* enable */ 242 0), 243 SUNXI_CCU_FIXED_FACTOR(H6_CLK_PLL_PERIPH0_2X, "pll_periph0_2x", "pll_periph0_4x", 2, 1), 244 SUNXI_CCU_FIXED_FACTOR(H6_CLK_PLL_PERIPH0, "pll_periph0", "pll_periph0_4x", 4, 1), 245 246 SUNXI_CCU_NM(H6_CLK_AHB3, "ahb3", ahb3_parents, 247 AHB3_CFG_REG, /* reg */ 248 __BITS(9,8), /* n */ 249 __BITS(1,0), /* m */ 250 __BITS(25,24), /* sel */ 251 0, /* enable */ 252 SUNXI_CCU_NM_POWER_OF_TWO), 253 254 SUNXI_CCU_NM(H6_CLK_APB2, "apb2", apb2_parents, 255 APB2_CFG_REG, /* reg */ 256 __BITS(9,8), /* n */ 257 __BITS(1,0), /* m */ 258 __BITS(25,24), /* sel */ 259 0, /* enable */ 260 SUNXI_CCU_NM_POWER_OF_TWO), 261 262 SUNXI_CCU_NM(H6_CLK_MMC0, "mmc0", mod_parents, 263 SMHC0_CLK_REG, /* reg */ 264 __BITS(9,8), /* n */ 265 __BITS(3,0), /* m */ 266 __BITS(25,24), /* sel */ 267 __BIT(31), /* enable */ 268 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 269 SUNXI_CCU_NM(H6_CLK_MMC1, "mmc1", mod_parents, 270 SMHC1_CLK_REG, /* reg */ 271 __BITS(9,8), /* n */ 272 __BITS(3,0), /* m */ 273 __BITS(25,24), /* sel */ 274 __BIT(31), /* enable */ 275 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 276 SUNXI_CCU_NM(H6_CLK_MMC2, "mmc2", mod_parents, 277 SMHC2_CLK_REG, /* reg */ 278 __BITS(9,8), /* n */ 279 __BITS(3,0), /* m */ 280 __BITS(25,24), /* sel */ 281 __BIT(31), /* enable */ 282 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 283 SUNXI_CCU_GATE(H6_CLK_BUS_MMC0, "bus-mmc0", "mmc0", 284 SMHC_BGR_REG, 0), 285 SUNXI_CCU_GATE(H6_CLK_BUS_MMC1, "bus-mmc1", "mmc1", 286 SMHC_BGR_REG, 1), 287 SUNXI_CCU_GATE(H6_CLK_BUS_MMC2, "bus-mmc2", "mmc2", 288 SMHC_BGR_REG, 2), 289 290 SUNXI_CCU_GATE(H6_CLK_BUS_UART0, "bus-uart0", "apb2", 291 UART_BGR_REG, 0), 292 SUNXI_CCU_GATE(H6_CLK_BUS_UART1, "bus-uart1", "apb2", 293 UART_BGR_REG, 1), 294 SUNXI_CCU_GATE(H6_CLK_BUS_UART2, "bus-uart2", "apb2", 295 UART_BGR_REG, 2), 296 SUNXI_CCU_GATE(H6_CLK_BUS_UART3, "bus-uart3", "apb2", 297 UART_BGR_REG, 3), 298 299 SUNXI_CCU_GATE(H6_CLK_BUS_I2C0, "bus-i2c0", "apb2", 300 TWI_BGR_REG, 0), 301 SUNXI_CCU_GATE(H6_CLK_BUS_I2C1, "bus-i2c1", "apb2", 302 TWI_BGR_REG, 1), 303 SUNXI_CCU_GATE(H6_CLK_BUS_I2C2, "bus-i2c2", "apb2", 304 TWI_BGR_REG, 2), 305 SUNXI_CCU_GATE(H6_CLK_BUS_I2C3, "bus-i2c3", "apb2", 306 TWI_BGR_REG, 3), 307 308 SUNXI_CCU_GATE(H6_CLK_USB_OHCI0, "usb-ohci0", "ahb3", 309 USB0_CLK_REG, 31), 310 SUNXI_CCU_GATE(H6_CLK_USB_PHY0, "usb-phy0", "ahb3", 311 USB0_CLK_REG, 29), 312 313 SUNXI_CCU_GATE(H6_CLK_USB_PHY1, "usb-phy1", "ahb3", 314 USB1_CLK_REG, 29), 315 316 SUNXI_CCU_GATE(H6_CLK_USB_OHCI3, "usb-ohci3", "ahb3", 317 USB3_CLK_REG, 31), 318 SUNXI_CCU_GATE(H6_CLK_USB_PHY3, "usb-phy3", "ahb3", 319 USB3_CLK_REG, 29), 320 SUNXI_CCU_GATE(H6_CLK_USB_HSIC_12M, "usb-hsic-12m", "osc12m", 321 USB3_CLK_REG, 27), 322 SUNXI_CCU_GATE(H6_CLK_USB_HSIC, "usb-hsic", "ahb3", 323 USB3_CLK_REG, 26), 324 325 SUNXI_CCU_GATE(H6_CLK_BUS_OHCI0, "bus-ohci0", "ahb3", 326 USB_BGR_REG, 0), 327 SUNXI_CCU_GATE(H6_CLK_BUS_OHCI3, "bus-ohci3", "ahb3", 328 USB_BGR_REG, 3), 329 SUNXI_CCU_GATE(H6_CLK_BUS_EHCI0, "bus-ehci0", "ahb3", 330 USB_BGR_REG, 4), 331 SUNXI_CCU_GATE(H6_CLK_BUS_XHCI, "bus-xhci", "ahb3", 332 USB_BGR_REG, 5), 333 SUNXI_CCU_GATE(H6_CLK_BUS_EHCI3, "bus-ehci3", "ahb3", 334 USB_BGR_REG, 7), 335 SUNXI_CCU_GATE(H6_CLK_BUS_OTG, "bus-otg", "ahb3", 336 USB_BGR_REG, 8), 337 338 SUNXI_CCU_GATE(H6_CLK_BUS_EMAC, "bus-emac", "ahb3", 339 EMAC_BGR_REG, 0), 340 341 SUNXI_CCU_FIXED_FACTOR(H6_CLK_PCIE_REF_100M, "pcie_ref_100M", 342 "pll_periph0_4x", 24, 1), 343 SUNXI_CCU_GATE(H6_CLK_PCIE_REF, "pcie_ref", "pcie_ref_100M", 344 PCIE_REF_CLK_REG, 31), 345 SUNXI_CCU_GATE(H6_CLK_PCIE_REF_OUT, "pcie_ref_out", "pcie_ref", 346 PCIE_REF_CLK_REG, 30), 347 348 SUNXI_CCU_NM(H6_CLK_PSI_AHB1_AHB2, "psi_ahb1_ahb2", 349 psi_ahb1_ahb2_parents, 350 PSI_AHB1_AHB2_CFG_REG, /* reg */ 351 __BITS(9,8), /* n */ 352 __BITS(1,0), /* m */ 353 __BITS(25,24), /* sel */ 354 0, /* enable */ 355 SUNXI_CCU_NM_POWER_OF_TWO), 356 SUNXI_CCU_DIV_GATE(H6_CLK_PCIE_MAXI, "pcie_maxi", pll_periph0_parent, 357 PCIE_AXI_CLK_REG, /* reg */ 358 __BITS(3,0), /* div */ 359 0, /* sel */ 360 __BIT(31), /* enable */ 361 SUNXI_CCU_DIV_ZERO_IS_ONE), 362 SUNXI_CCU_DIV_GATE(H6_CLK_PCIE_AUX, "pcie_aux", hosc_parent, 363 PCIE_AUX_CLK_REG, /* reg */ 364 __BITS(4,0), /* div */ 365 0, /* sel */ 366 __BIT(31), /* enable */ 367 SUNXI_CCU_DIV_ZERO_IS_ONE), 368 369 SUNXI_CCU_GATE(H6_CLK_BUS_PCIE, "bus_pcie", "psi_ahb1_ahb2", 370 PCIE_BGR_REG, 0), 371 }; 372 373 static int 374 sun50i_h6_ccu_match(device_t parent, cfdata_t cf, void *aux) 375 { 376 struct fdt_attach_args * const faa = aux; 377 378 return of_compatible_match(faa->faa_phandle, compat_data); 379 } 380 381 static void 382 sun50i_h6_ccu_attach(device_t parent, device_t self, void *aux) 383 { 384 struct sunxi_ccu_softc * const sc = device_private(self); 385 struct fdt_attach_args * const faa = aux; 386 387 sc->sc_dev = self; 388 sc->sc_phandle = faa->faa_phandle; 389 sc->sc_bst = faa->faa_bst; 390 391 sc->sc_resets = sun50i_h6_ccu_resets; 392 sc->sc_nresets = __arraycount(sun50i_h6_ccu_resets); 393 394 sc->sc_clks = sun50i_h6_ccu_clks; 395 sc->sc_nclks = __arraycount(sun50i_h6_ccu_clks); 396 397 if (sunxi_ccu_attach(sc) != 0) 398 return; 399 400 aprint_naive("\n"); 401 aprint_normal(": H6 CCU\n"); 402 403 sunxi_ccu_print(sc); 404 } 405
Indexes created Fri Oct 03 02:09:57 GMT 2025