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      1 /*	$NetBSD: qcom,gcc-mdm9615.h,v 1.1.1.2 2020/01/03 14:33:04 skrll Exp $	*/
      2 
      3 /* SPDX-License-Identifier: GPL-2.0-only */
      4 /*
      5  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
      6  * Copyright (c) BayLibre, SAS.
      7  * Author : Neil Armstrong <narmstrong (at) baylibre.com>
      8  */
      9 
     10 #ifndef _DT_BINDINGS_CLK_MDM_GCC_9615_H
     11 #define _DT_BINDINGS_CLK_MDM_GCC_9615_H
     12 
     13 #define AFAB_CLK_SRC				0
     14 #define AFAB_CORE_CLK				1
     15 #define SFAB_MSS_Q6_SW_A_CLK			2
     16 #define SFAB_MSS_Q6_FW_A_CLK			3
     17 #define QDSS_STM_CLK				4
     18 #define SCSS_A_CLK				5
     19 #define SCSS_H_CLK				6
     20 #define SCSS_XO_SRC_CLK				7
     21 #define AFAB_EBI1_CH0_A_CLK			8
     22 #define AFAB_EBI1_CH1_A_CLK			9
     23 #define AFAB_AXI_S0_FCLK			10
     24 #define AFAB_AXI_S1_FCLK			11
     25 #define AFAB_AXI_S2_FCLK			12
     26 #define AFAB_AXI_S3_FCLK			13
     27 #define AFAB_AXI_S4_FCLK			14
     28 #define SFAB_CORE_CLK				15
     29 #define SFAB_AXI_S0_FCLK			16
     30 #define SFAB_AXI_S1_FCLK			17
     31 #define SFAB_AXI_S2_FCLK			18
     32 #define SFAB_AXI_S3_FCLK			19
     33 #define SFAB_AXI_S4_FCLK			20
     34 #define SFAB_AHB_S0_FCLK			21
     35 #define SFAB_AHB_S1_FCLK			22
     36 #define SFAB_AHB_S2_FCLK			23
     37 #define SFAB_AHB_S3_FCLK			24
     38 #define SFAB_AHB_S4_FCLK			25
     39 #define SFAB_AHB_S5_FCLK			26
     40 #define SFAB_AHB_S6_FCLK			27
     41 #define SFAB_AHB_S7_FCLK			28
     42 #define QDSS_AT_CLK_SRC				29
     43 #define QDSS_AT_CLK				30
     44 #define QDSS_TRACECLKIN_CLK_SRC			31
     45 #define QDSS_TRACECLKIN_CLK			32
     46 #define QDSS_TSCTR_CLK_SRC			33
     47 #define QDSS_TSCTR_CLK				34
     48 #define SFAB_ADM0_M0_A_CLK			35
     49 #define SFAB_ADM0_M1_A_CLK			36
     50 #define SFAB_ADM0_M2_H_CLK			37
     51 #define ADM0_CLK				38
     52 #define ADM0_PBUS_CLK				39
     53 #define MSS_XPU_CLK				40
     54 #define IMEM0_A_CLK				41
     55 #define QDSS_H_CLK				42
     56 #define PCIE_A_CLK				43
     57 #define PCIE_AUX_CLK				44
     58 #define PCIE_PHY_REF_CLK			45
     59 #define PCIE_H_CLK				46
     60 #define SFAB_CLK_SRC				47
     61 #define MAHB0_CLK				48
     62 #define Q6SW_CLK_SRC				49
     63 #define Q6SW_CLK				50
     64 #define Q6FW_CLK_SRC				51
     65 #define Q6FW_CLK				52
     66 #define SFAB_MSS_M_A_CLK			53
     67 #define SFAB_USB3_M_A_CLK			54
     68 #define SFAB_LPASS_Q6_A_CLK			55
     69 #define SFAB_AFAB_M_A_CLK			56
     70 #define AFAB_SFAB_M0_A_CLK			57
     71 #define AFAB_SFAB_M1_A_CLK			58
     72 #define SFAB_SATA_S_H_CLK			59
     73 #define DFAB_CLK_SRC				60
     74 #define DFAB_CLK				61
     75 #define SFAB_DFAB_M_A_CLK			62
     76 #define DFAB_SFAB_M_A_CLK			63
     77 #define DFAB_SWAY0_H_CLK			64
     78 #define DFAB_SWAY1_H_CLK			65
     79 #define DFAB_ARB0_H_CLK				66
     80 #define DFAB_ARB1_H_CLK				67
     81 #define PPSS_H_CLK				68
     82 #define PPSS_PROC_CLK				69
     83 #define PPSS_TIMER0_CLK				70
     84 #define PPSS_TIMER1_CLK				71
     85 #define PMEM_A_CLK				72
     86 #define DMA_BAM_H_CLK				73
     87 #define SIC_H_CLK				74
     88 #define SPS_TIC_H_CLK				75
     89 #define SLIMBUS_H_CLK				76
     90 #define SLIMBUS_XO_SRC_CLK			77
     91 #define CFPB_2X_CLK_SRC				78
     92 #define CFPB_CLK				79
     93 #define CFPB0_H_CLK				80
     94 #define CFPB1_H_CLK				81
     95 #define CFPB2_H_CLK				82
     96 #define SFAB_CFPB_M_H_CLK			83
     97 #define CFPB_MASTER_H_CLK			84
     98 #define SFAB_CFPB_S_H_CLK			85
     99 #define CFPB_SPLITTER_H_CLK			86
    100 #define TSIF_H_CLK				87
    101 #define TSIF_INACTIVITY_TIMERS_CLK		88
    102 #define TSIF_REF_SRC				89
    103 #define TSIF_REF_CLK				90
    104 #define CE1_H_CLK				91
    105 #define CE1_CORE_CLK				92
    106 #define CE1_SLEEP_CLK				93
    107 #define CE2_H_CLK				94
    108 #define CE2_CORE_CLK				95
    109 #define SFPB_H_CLK_SRC				97
    110 #define SFPB_H_CLK				98
    111 #define SFAB_SFPB_M_H_CLK			99
    112 #define SFAB_SFPB_S_H_CLK			100
    113 #define RPM_PROC_CLK				101
    114 #define RPM_BUS_H_CLK				102
    115 #define RPM_SLEEP_CLK				103
    116 #define RPM_TIMER_CLK				104
    117 #define RPM_MSG_RAM_H_CLK			105
    118 #define PMIC_ARB0_H_CLK				106
    119 #define PMIC_ARB1_H_CLK				107
    120 #define PMIC_SSBI2_SRC				108
    121 #define PMIC_SSBI2_CLK				109
    122 #define SDC1_H_CLK				110
    123 #define SDC2_H_CLK				111
    124 #define SDC3_H_CLK				112
    125 #define SDC4_H_CLK				113
    126 #define SDC5_H_CLK				114
    127 #define SDC1_SRC				115
    128 #define SDC2_SRC				116
    129 #define SDC3_SRC				117
    130 #define SDC4_SRC				118
    131 #define SDC5_SRC				119
    132 #define SDC1_CLK				120
    133 #define SDC2_CLK				121
    134 #define SDC3_CLK				122
    135 #define SDC4_CLK				123
    136 #define SDC5_CLK				124
    137 #define DFAB_A2_H_CLK				125
    138 #define USB_HS1_H_CLK				126
    139 #define USB_HS1_XCVR_SRC			127
    140 #define USB_HS1_XCVR_CLK			128
    141 #define USB_HSIC_H_CLK				129
    142 #define USB_HSIC_XCVR_FS_SRC			130
    143 #define USB_HSIC_XCVR_FS_CLK			131
    144 #define USB_HSIC_SYSTEM_CLK_SRC			132
    145 #define USB_HSIC_SYSTEM_CLK			133
    146 #define CFPB0_C0_H_CLK				134
    147 #define CFPB0_C1_H_CLK				135
    148 #define CFPB0_D0_H_CLK				136
    149 #define CFPB0_D1_H_CLK				137
    150 #define USB_FS1_H_CLK				138
    151 #define USB_FS1_XCVR_FS_SRC			139
    152 #define USB_FS1_XCVR_FS_CLK			140
    153 #define USB_FS1_SYSTEM_CLK			141
    154 #define USB_FS2_H_CLK				142
    155 #define USB_FS2_XCVR_FS_SRC			143
    156 #define USB_FS2_XCVR_FS_CLK			144
    157 #define USB_FS2_SYSTEM_CLK			145
    158 #define GSBI_COMMON_SIM_SRC			146
    159 #define GSBI1_H_CLK				147
    160 #define GSBI2_H_CLK				148
    161 #define GSBI3_H_CLK				149
    162 #define GSBI4_H_CLK				150
    163 #define GSBI5_H_CLK				151
    164 #define GSBI6_H_CLK				152
    165 #define GSBI7_H_CLK				153
    166 #define GSBI8_H_CLK				154
    167 #define GSBI9_H_CLK				155
    168 #define GSBI10_H_CLK				156
    169 #define GSBI11_H_CLK				157
    170 #define GSBI12_H_CLK				158
    171 #define GSBI1_UART_SRC				159
    172 #define GSBI1_UART_CLK				160
    173 #define GSBI2_UART_SRC				161
    174 #define GSBI2_UART_CLK				162
    175 #define GSBI3_UART_SRC				163
    176 #define GSBI3_UART_CLK				164
    177 #define GSBI4_UART_SRC				165
    178 #define GSBI4_UART_CLK				166
    179 #define GSBI5_UART_SRC				167
    180 #define GSBI5_UART_CLK				168
    181 #define GSBI6_UART_SRC				169
    182 #define GSBI6_UART_CLK				170
    183 #define GSBI7_UART_SRC				171
    184 #define GSBI7_UART_CLK				172
    185 #define GSBI8_UART_SRC				173
    186 #define GSBI8_UART_CLK				174
    187 #define GSBI9_UART_SRC				175
    188 #define GSBI9_UART_CLK				176
    189 #define GSBI10_UART_SRC				177
    190 #define GSBI10_UART_CLK				178
    191 #define GSBI11_UART_SRC				179
    192 #define GSBI11_UART_CLK				180
    193 #define GSBI12_UART_SRC				181
    194 #define GSBI12_UART_CLK				182
    195 #define GSBI1_QUP_SRC				183
    196 #define GSBI1_QUP_CLK				184
    197 #define GSBI2_QUP_SRC				185
    198 #define GSBI2_QUP_CLK				186
    199 #define GSBI3_QUP_SRC				187
    200 #define GSBI3_QUP_CLK				188
    201 #define GSBI4_QUP_SRC				189
    202 #define GSBI4_QUP_CLK				190
    203 #define GSBI5_QUP_SRC				191
    204 #define GSBI5_QUP_CLK				192
    205 #define GSBI6_QUP_SRC				193
    206 #define GSBI6_QUP_CLK				194
    207 #define GSBI7_QUP_SRC				195
    208 #define GSBI7_QUP_CLK				196
    209 #define GSBI8_QUP_SRC				197
    210 #define GSBI8_QUP_CLK				198
    211 #define GSBI9_QUP_SRC				199
    212 #define GSBI9_QUP_CLK				200
    213 #define GSBI10_QUP_SRC				201
    214 #define GSBI10_QUP_CLK				202
    215 #define GSBI11_QUP_SRC				203
    216 #define GSBI11_QUP_CLK				204
    217 #define GSBI12_QUP_SRC				205
    218 #define GSBI12_QUP_CLK				206
    219 #define GSBI1_SIM_CLK				207
    220 #define GSBI2_SIM_CLK				208
    221 #define GSBI3_SIM_CLK				209
    222 #define GSBI4_SIM_CLK				210
    223 #define GSBI5_SIM_CLK				211
    224 #define GSBI6_SIM_CLK				212
    225 #define GSBI7_SIM_CLK				213
    226 #define GSBI8_SIM_CLK				214
    227 #define GSBI9_SIM_CLK				215
    228 #define GSBI10_SIM_CLK				216
    229 #define GSBI11_SIM_CLK				217
    230 #define GSBI12_SIM_CLK				218
    231 #define USB_HSIC_HSIC_CLK_SRC			219
    232 #define USB_HSIC_HSIC_CLK			220
    233 #define USB_HSIC_HSIO_CAL_CLK			221
    234 #define SPDM_CFG_H_CLK				222
    235 #define SPDM_MSTR_H_CLK				223
    236 #define SPDM_FF_CLK_SRC				224
    237 #define SPDM_FF_CLK				225
    238 #define SEC_CTRL_CLK				226
    239 #define SEC_CTRL_ACC_CLK_SRC			227
    240 #define SEC_CTRL_ACC_CLK			228
    241 #define TLMM_H_CLK				229
    242 #define TLMM_CLK				230
    243 #define SFAB_MSS_S_H_CLK			231
    244 #define MSS_SLP_CLK				232
    245 #define MSS_Q6SW_JTAG_CLK			233
    246 #define MSS_Q6FW_JTAG_CLK			234
    247 #define MSS_S_H_CLK				235
    248 #define MSS_CXO_SRC_CLK				236
    249 #define SATA_H_CLK				237
    250 #define SATA_CLK_SRC				238
    251 #define SATA_RXOOB_CLK				239
    252 #define SATA_PMALIVE_CLK			240
    253 #define SATA_PHY_REF_CLK			241
    254 #define TSSC_CLK_SRC				242
    255 #define TSSC_CLK				243
    256 #define PDM_SRC					244
    257 #define PDM_CLK					245
    258 #define GP0_SRC					246
    259 #define GP0_CLK					247
    260 #define GP1_SRC					248
    261 #define GP1_CLK					249
    262 #define GP2_SRC					250
    263 #define GP2_CLK					251
    264 #define MPM_CLK					252
    265 #define EBI1_CLK_SRC				253
    266 #define EBI1_CH0_CLK				254
    267 #define EBI1_CH1_CLK				255
    268 #define EBI1_2X_CLK				256
    269 #define EBI1_CH0_DQ_CLK				257
    270 #define EBI1_CH1_DQ_CLK				258
    271 #define EBI1_CH0_CA_CLK				259
    272 #define EBI1_CH1_CA_CLK				260
    273 #define EBI1_XO_CLK				261
    274 #define SFAB_SMPSS_S_H_CLK			262
    275 #define PRNG_SRC				263
    276 #define PRNG_CLK				264
    277 #define PXO_SRC					265
    278 #define LPASS_CXO_CLK				266
    279 #define LPASS_PXO_CLK				267
    280 #define SPDM_CY_PORT0_CLK			268
    281 #define SPDM_CY_PORT1_CLK			269
    282 #define SPDM_CY_PORT2_CLK			270
    283 #define SPDM_CY_PORT3_CLK			271
    284 #define SPDM_CY_PORT4_CLK			272
    285 #define SPDM_CY_PORT5_CLK			273
    286 #define SPDM_CY_PORT6_CLK			274
    287 #define SPDM_CY_PORT7_CLK			275
    288 #define PLL0					276
    289 #define PLL0_VOTE				277
    290 #define PLL3					278
    291 #define PLL3_VOTE				279
    292 #define PLL4_VOTE				280
    293 #define PLL5					281
    294 #define PLL5_VOTE				282
    295 #define PLL6					283
    296 #define PLL6_VOTE				284
    297 #define PLL7_VOTE				285
    298 #define PLL8					286
    299 #define PLL8_VOTE				287
    300 #define PLL9					288
    301 #define PLL10					289
    302 #define PLL11					290
    303 #define PLL12					291
    304 #define PLL13					292
    305 #define PLL14					293
    306 #define PLL14_VOTE				294
    307 #define USB_HS3_H_CLK				295
    308 #define USB_HS3_XCVR_SRC			296
    309 #define USB_HS3_XCVR_CLK			297
    310 #define USB_HS4_H_CLK				298
    311 #define USB_HS4_XCVR_SRC			299
    312 #define USB_HS4_XCVR_CLK			300
    313 #define SATA_PHY_CFG_CLK			301
    314 #define SATA_A_CLK				302
    315 #define CE3_SRC					303
    316 #define CE3_CORE_CLK				304
    317 #define CE3_H_CLK				305
    318 #define USB_HS1_SYSTEM_CLK_SRC			306
    319 #define USB_HS1_SYSTEM_CLK			307
    320 #define EBI2_CLK				308
    321 #define EBI2_AON_CLK				309
    322 
    323 #endif
    324