| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsMachineFunction.cpp | 76 Register V0 = RegInfo.createVirtualRegister(RC);
83 // lui $v0, %hi(%neg(%gp_rel(fname)))
84 // daddu $v1, $v0, $t9
87 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
89 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
99 // lui $v0, %hi(__gnu_local_gp)
100 // addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
101 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
103 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
112 // lui $v0, %hi(%neg(%gp_rel(fname))
[all...] |
| Mips16ISelDAGToDAG.cpp | 75 Register V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg(MF);
78 V0 = RegInfo.createVirtualRegister(RC);
83 BuildMI(MBB, I, DL, TII.get(Mips::LiRxImmX16), V0)
88 BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16);
|
| MipsISelLowering.cpp | 1058 // (sub v0 (mul v1, v2)) => (msub v1, v2, v0)
1073 // (add v0 (mul v1, v2)) => (madd v1, v2, v0)
1082 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
2543 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and
2546 unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0;
3727 // the sret argument into $v0 for the return. Save the argument into
3860 // the sret argument into $v0 for the return. We saved the argument int
[all...] |
| /src/lib/libm/src/ |
| e_j1.c | 54 * V(z) = 1 + v0[0]*z + ... + v0[4]*z^5
136 static const double V0[5] = {
189 v = one+z*(V0[0]+z*(V0[1]+z*(V0[2]+z*(V0[3]+z*V0[4]))));
|
| e_j1f.c | 97 static const float V0[5] = {
150 v = one+z*(V0[0]+z*(V0[1]+z*(V0[2]+z*(V0[3]+z*V0[4]))));
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 222 SDValue V0 = N->getOperand(i+1);
224 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg();
|
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/ |
| LibCallsShrinkWrap.cpp | 470 Constant *V0 = ConstantFP::get(CI->getContext(), APFloat(0.0f));
474 V0 = ConstantExpr::getFPExtend(V0, Exp->getType());
477 Value *Cond0 = BBBuilder.CreateFCmp(CmpInst::FCMP_OLE, Base, V0);
|
| /src/external/gpl2/groff/dist/src/roff/troff/ |
| number.cpp | 33 vunits V0;
|
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/ |
| Reassociate.cpp | 127 Value *V0 = I->getOperand(0);
130 if (match(V0, m_APInt(C)))
131 std::swap(V0, V1);
135 SymbolicPart = V0;
1030 Value *V0 = Sub->getOperand(0);
1031 if (isReassociableOp(V0, Instruction::Add, Instruction::FAdd) ||
1032 isReassociableOp(V0, Instruction::Sub, Instruction::FSub))
|
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/Vectorize/ |
| VectorCombine.cpp | 320 // opcode (extelt V0, Ext0), (ext V1, Ext1) -->
321 // extelt (opcode (splat V0, Ext0), V1), Ext1
341 // opcode (extelt V0, C0), (extelt V1, C1) --> extelt (opcode V0, V1), C
405 /// cmp (ext0 V0, C), (ext1 V1, C)
413 // cmp Pred (extelt V0, C), (extelt V1, C) --> extelt (cmp Pred V0, V1), C
416 Value *V0 = Ext0->getVectorOperand(), *V1 = Ext1->getVectorOperand();
417 Value *VecCmp = Builder.CreateCmp(Pred, V0, V1);
424 /// bo (ext0 V0, C), (ext1 V1, C
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Analysis/ |
| VectorUtils.cpp | 852 Value *V0 = ResList[i], *V1 = ResList[i + 1];
853 assert((V0->getType() == V1->getType() || i == NumVecs - 2) &&
856 TmpList.push_back(concatenateTwoVectors(Builder, V0, V1));
|
| ValueTracking.cpp | 3522 Value *V0 = I->getOperand(0), *V1 = I->getOperand(1);
3541 return isPositiveNum(V0) || isPositiveNum(V1);
5023 // V = extractvalue V0, idx
5024 // V2 = extractvalue V0, idx2
5025 // V0's elements are all poison or not. (e.g., add_with_overflow)
|
| /src/external/bsd/pcc/dist/pcc/arch/mips/ |
| macdefs.h | 140 #define V0 2
230 F0 : V0)
263 { V0V1, -1 }, /* $v0 */ \
297 { V0, V1, -1 }, /* $v0:$v1 */ \
|
| /src/external/gpl3/gdb/dist/sim/aarch64/ |
| cpustate.h | 92 V0,
|
| /src/external/gpl3/gdb.old/dist/sim/aarch64/ |
| cpustate.h | 92 V0,
|
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/ |
| InstCombineAddSub.cpp | 391 Value *V0 = I->getOperand(0);
393 if (ConstantFP *C = dyn_cast<ConstantFP>(V0)) {
399 Addend0.set(C, V0);
469 Value *V0 = I->getOperand(0);
471 InstQuota = ((!isa<Constant>(V0) && V0->hasOneUse()) &&
1828 Value *V0, *V1;
1829 if (match(Op0, m_AddRdx(V0)) && match(Op1, m_AddRdx(V1)) &&
1830 V0->getType() == V1->getType()) {
1832 // add_rdx(V0) - add_rdx(V1) --> add_rdx(V0 - V1
[all...] |
| /src/external/gpl3/gcc/dist/contrib/ |
| paranoia.cc | 78 E2 Exp2 N V0
989 FLOAT V, V0, V9;
2134 V0 = V9;
2135 if (V - Y == V + V0)
2151 if (Z < V0)
2153 if (Y < V0)
2155 if (V0 - V < V0)
2156 V = V0;
2165 printf ("Overflow saturates at V0 = %s .\n", V0.str())
[all...] |
| /src/external/gpl3/gcc.old/dist/contrib/ |
| paranoia.cc | 78 E2 Exp2 N V0
989 FLOAT V, V0, V9;
2134 V0 = V9;
2135 if (V - Y == V + V0)
2151 if (Z < V0)
2153 if (Y < V0)
2155 if (V0 - V < V0)
2156 V = V0;
2165 printf ("Overflow saturates at V0 = %s .\n", V0.str())
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/IR/ |
| AutoUpgrade.cpp | 2697 Value *V0 = (Imm & 0x02) ? CI->getArgOperand(1) : CI->getArgOperand(0);
2701 V0 = (Imm & 0x08) ? ConstantAggregateZero::get(CI->getType()) : V0;
2714 Rep = Builder.CreateShuffleVector(V0, V1, ShuffleMask);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonISelDAGToDAG.cpp | 2164 SDValue V0 = L0.Value;
2170 if ((RootWeights.count(V0.getNode()) && RootWeights[V0.getNode()] == -2) ||
2176 ConstantSDNode *V0C = dyn_cast<ConstantSDNode>(V0);
2182 std::swap(V0, V1);
2187 assert(NodeHeights.count(V0) && NodeHeights.count(V1) &&
2189 int Height = std::max(NodeHeights[V0], NodeHeights[V1]) + 1;
2194 ISD::SHL, SDLoc(V0), VT, V0,
2197 TLI.getScalarShiftAmountTy(DL, V0.getValueType())))
[all...] |
| HexagonISelLowering.cpp | 813 return Reg - Hexagon::V0 + 1;
2485 SDValue V0 = DAG.getConstant(Val, dl, MVT::i64);
2486 return DAG.getBitcast(VecTy, V0);
3258 // (vselect (xor x, ptrue), v0, v1) -> (vselect x, v1, v0)
3339 case 'v': // V0-V31
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| M68kISelLowering.cpp | 1820 SDValue V0 = DAG.getNode(ISD::TRUNCATE, DL, VT, WideVal.getOperand(0));
1822 Op = DAG.getNode(ConvertedOp, DL, VT, V0, V1);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | 324 SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
325 SDNode *createSRegPairNode(EVT VT, SDValue V0, SDValue V1);
326 SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
327 SDNode *createQRegPairNode(EVT VT, SDValue V0, SDValue V1);
330 SDNode *createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
331 SDNode *createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
332 SDNode *createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
1829 SDNode *ARMDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) {
1830 SDLoc dl(V0.getNode());
1835 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeIntegerTypes.cpp | 4634 SDValue V0 = GetPromotedInteger(N->getOperand(0));
4636 EVT OutVT = V0.getValueType();
4638 return DAG.getNode(ISD::VECTOR_SPLICE, dl, OutVT, V0, V1, N->getOperand(2));
4704 SDValue V0 = GetPromotedInteger(N->getOperand(0));
4705 EVT OutVT = V0.getValueType();
4707 return DAG.getNode(ISD::VECTOR_REVERSE, dl, OutVT, V0);
4717 SDValue V0 = GetPromotedInteger(N->getOperand(0));
4719 EVT OutVT = V0.getValueType();
4721 return DAG.getVectorShuffle(OutVT, dl, V0, V1, NewMask);
4876 SDValue V0 = GetPromotedInteger(N->getOperand(0))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.cpp | 2690 SDValue V0 = DAG.getSelectCC(DL, VLow3, DAG.getConstant(3, DL, MVT::i32),
2694 V1 = DAG.getNode(ISD::OR, DL, MVT::i32, V0, V1);
|
