| /src/external/apache2/llvm/dist/llvm/lib/Support/ |
| xxhash.cpp | 80 uint64_t V1 = Seed + PRIME64_1 + PRIME64_2;
86 V1 = round(V1, endian::read64le(P));
96 H64 = rotl64(V1, 1) + rotl64(V2, 7) + rotl64(V3, 12) + rotl64(V4, 18);
97 H64 = mergeRound(H64, V1);
|
| FileUtilities.cpp | 92 double V1 = 0.0, V2 = 0.0;
110 V1 = strtod(F1P, const_cast<char**>(&F1NumEnd));
119 V1 = strtod(&StrTmp[0], const_cast<char**>(&F1NumEnd));
146 if (AbsTolerance < std::abs(V1-V2)) {
150 Diff = std::abs(V1/V2 - 1.0);
151 else if (V1)
152 Diff = std::abs(V2/V1 - 1.0);
158 << "Compared: " << V1 << " and " << V2 << '\n'
159 << "abs. diff = " << std::abs(V1-V2) << " rel.diff = " << Diff << '\n'
|
| /src/external/apache2/llvm/dist/llvm/examples/IRTransforms/ |
| SimplifyCFG.cpp | 49 enum TutorialVersion { V1, V2, V3 };
52 cl::Hidden, cl::ValueOptional, cl::init(V1),
53 cl::values(clEnumValN(V1, "v1", "version 1"),
381 if (Version != V1)
392 case V1:
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| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsMachineFunction.cpp | 77 Register V1 = RegInfo.createVirtualRegister(RC);
84 // daddu $v1, $v0, $t9
85 // daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
89 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
91 BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
113 // addu $v1, $v0, $t9
114 // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
118 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
119 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
|
| Mips16ISelDAGToDAG.cpp | 75 Register V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg(MF);
79 V1 = RegInfo.createVirtualRegister(RC);
85 BuildMI(MBB, I, DL, TII.get(Mips::AddiuRxPcImmX16), V1)
90 .addReg(V1)
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonGenInsert.cpp | 238 bool operator() (const BitTracker::BitValue &V1,
246 bool BitValueOrdering::operator() (const BitTracker::BitValue &V1,
248 if (V1 == V2)
250 // V1==0 => true, V2==0 => false
251 if (V1.is(0) || V2.is(0))
252 return V1.is(0);
253 // Neither of V1,V2 is 0, and V1!=V2.
254 // V2==1 => false, V1==1 => true
255 if (V2.is(1) || V1.is(1)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 223 SDValue V1 = N->getOperand(i+2);
225 unsigned Reg1 = cast<RegisterSDNode>(V1)->getReg();
|
| /src/external/gpl3/gdb.old/dist/gdb/testsuite/gdb.base/ |
| max-depth.c | 218 struct V1 { int v1 = 1; } v1; variable in typeref:struct:V1
219 struct V2 : virtual V1 { int v2 = 2; } v2;
220 struct V3 : virtual V1 { int v3 = 3; } v3;
|
| /src/external/gpl3/gdb/dist/gdb/testsuite/gdb.base/ |
| max-depth.c | 218 struct V1 { int v1 = 1; } v1; variable in typeref:struct:V1
219 struct V2 : virtual V1 { int v2 = 2; } v2;
220 struct V3 : virtual V1 { int v3 = 3; } v3;
|
| /src/external/bsd/openldap/dist/contrib/slapd-modules/comp_match/ |
| crl.h | 27 #define V1 0
31 typedef ComponentInt ComponentVersion; /* INTEGER { V1 (0), V2 (1), V3 (2) } */
|
| certificate.h | 49 #define V1 0
53 typedef ComponentInt ComponentVersion; /* INTEGER { V1 (0), V2 (1), V3 (2) } */
324 ComponentVersion* version; /* [0] Version DEFAULT v1 */
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| AArch64PostLegalizerLowering.cpp | 257 Register V1 = MI.getOperand(1).getReg();
259 MatchInfo = ShuffleVectorPseudo(Opc, Dst, {V1, V2});
278 Register V1 = MI.getOperand(1).getReg();
280 MatchInfo = ShuffleVectorPseudo(Opc, Dst, {V1, V2});
294 Register V1 = MI.getOperand(1).getReg();
296 MatchInfo = ShuffleVectorPseudo(Opc, Dst, {V1, V2});
384 Register V1 = MI.getOperand(1).getReg();
387 std::swap(V1, V2);
388 uint64_t ExtFactor = MRI.getType(V1).getScalarSizeInBits() / 8;
390 MatchInfo = ShuffleVectorPseudo(AArch64::G_EXT, Dst, {V1, V2, Imm})
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/ |
| Reassociate.cpp | 128 Value *V1 = I->getOperand(1);
131 std::swap(V0, V1);
133 if (match(V1, m_APInt(C))) {
1034 Value *V1 = Sub->getOperand(1);
1035 if (isReassociableOp(V1, Instruction::Add, Instruction::FAdd) ||
1036 isReassociableOp(V1, Instruction::Sub, Instruction::FSub))
1132 Value *V1 = Ops.pop_back_val();
1134 return CreateAdd(V2, V1, "reass.add", I, I);
|
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/Vectorize/ |
| VectorCombine.cpp | 320 // opcode (extelt V0, Ext0), (ext V1, Ext1) -->
321 // extelt (opcode (splat V0, Ext0), V1), Ext1
341 // opcode (extelt V0, C0), (extelt V1, C1) --> extelt (opcode V0, V1), C
405 /// cmp (ext0 V0, C), (ext1 V1, C)
413 // cmp Pred (extelt V0, C), (extelt V1, C) --> extelt (cmp Pred V0, V1), C
416 Value *V0 = Ext0->getVectorOperand(), *V1 = Ext1->getVectorOperand();
417 Value *VecCmp = Builder.CreateCmp(Pred, V0, V1);
424 /// bo (ext0 V0, C), (ext1 V1, C
[all...] |
| /src/external/apache2/llvm/dist/clang/lib/CodeGen/ |
| CGValue.h | 47 llvm::PointerIntPair<llvm::Value *, 2, Flavor> V1;
52 bool isScalar() const { return V1.getInt() == Scalar; }
53 bool isComplex() const { return V1.getInt() == Complex; }
54 bool isAggregate() const { return V1.getInt() == Aggregate; }
61 return V1.getPointer();
67 return std::make_pair(V1.getPointer(), V2.getPointer());
74 return Address(V1.getPointer(), CharUnits::fromQuantity(align));
78 return V1.getPointer();
88 ER.V1.setPointer(V);
89 ER.V1.setInt(Scalar)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Analysis/ |
| VectorUtils.cpp | 820 static Value *concatenateTwoVectors(IRBuilderBase &Builder, Value *V1,
822 VectorType *VecTy1 = dyn_cast<VectorType>(V1->getType());
839 V1, V2, createSequentialMask(0, NumElts1 + NumElts2, 0));
852 Value *V0 = ResList[i], *V1 = ResList[i + 1];
853 assert((V0->getType() == V1->getType() || i == NumVecs - 2) &&
856 TmpList.push_back(concatenateTwoVectors(Builder, V0, V1));
|
| /src/external/apache2/llvm/dist/llvm/lib/IR/ |
| ConstantFold.cpp | 770 Constant *V1, Constant *V2) {
773 if (Cond->isAllOnesValue()) return V1;
782 Constant *V1Element = ConstantExpr::getExtractElement(V1,
806 return PoisonValue::get(V1->getType());
809 if (isa<UndefValue>(V1)) return V1;
813 if (V1 == V2) return V1;
815 if (isa<PoisonValue>(V1))
818 return V1;
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/ |
| InstCombineLoadStoreAlloca.cpp | 537 /// select ((cmp load V1, load V2), V1, V2).
542 // Check that select is select ((cmp load V1, load V2), V1, V2) - minmax
1002 // load (select (Cond, &V1, &V2)) --> select(Cond, load &V1, load &V2).
1008 LoadInst *V1 =
1015 V1->setAlignment(Alignment);
1016 V1->setAtomic(LI.getOrdering(), LI.getSyncScopeID());
1019 return SelectInst::Create(SI->getCondition(), V1, V2)
[all...] |
| InstCombineShifts.cpp | 734 Value *V1;
745 match(Op0BO->getOperand(1), m_Shr(m_Value(V1),
750 Value *X = Builder.CreateBinOp(Op0BO->getOpcode(), YS, V1,
761 match(Op0BOOp1, m_And(m_OneUse(m_Shr(m_Value(V1), m_Specific(Op1))),
767 V1, ConstantExpr::getShl(ConstantInt::get(Ty, *CC), Op1),
768 V1->getName() + ".mask");
777 match(Op0BO->getOperand(0), m_Shr(m_Value(V1),
782 Value *X = Builder.CreateBinOp(Op0BO->getOpcode(), V1, YS,
793 m_And(m_OneUse(m_Shr(m_Value(V1), m_Specific(Op1))),
799 V1, ConstantExpr::getShl(ConstantInt::get(Ty, *CC), Op1)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/ |
| SCCPSolver.cpp | 945 Value *V1 = isConstant(V1State) ? getConstant(V1State) : I.getOperand(0);
947 Value *R = SimplifyBinOp(I.getOpcode(), V1, V2, SimplifyQuery(DL));
|
| /src/external/bsd/pcc/dist/pcc/arch/mips/ |
| macdefs.h | 141 #define V1 3
264 { V0V1, -1 }, /* $v1 */ \
297 { V0, V1, -1 }, /* $v0:$v1 */ \
|
| /src/external/gpl3/binutils/dist/opcodes/ |
| mips-opc.c | 316 #define V1 (INSN_4100 | INSN_4111 | INSN_4120)
1210 {"hibernate", "", 0x42000023, 0xffffffff, 0, 0, V1, 0, 0 },
1970 {"standby", "", 0x42000021, 0xffffffff, 0, 0, V1, 0, 0 },
1991 {"suspend", "", 0x42000022, 0xffffffff, 0, 0, V1, 0, 0 },
|
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| mips-opc.c | 316 #define V1 (INSN_4100 | INSN_4111 | INSN_4120)
1210 {"hibernate", "", 0x42000023, 0xffffffff, 0, 0, V1, 0, 0 },
1970 {"standby", "", 0x42000021, 0xffffffff, 0, 0, V1, 0, 0 },
1991 {"suspend", "", 0x42000022, 0xffffffff, 0, 0, V1, 0, 0 },
|
| /src/external/gpl3/gdb.old/dist/sim/aarch64/ |
| cpustate.h | 93 V1,
162 the float vector operations using indexing e.g. V1.D[1], V1.S[3]
|
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| mips-opc.c | 316 #define V1 (INSN_4100 | INSN_4111 | INSN_4120)
1210 {"hibernate", "", 0x42000023, 0xffffffff, 0, 0, V1, 0, 0 },
1970 {"standby", "", 0x42000021, 0xffffffff, 0, 0, V1, 0, 0 },
1991 {"suspend", "", 0x42000022, 0xffffffff, 0, 0, V1, 0, 0 },
|
