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    Searched defs:VAddr0Idx (Results 1 - 6 of 6) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
GCNNSAReassign.cpp 165 int VAddr0Idx =
171 const MachineOperand &Op = MI.getOperand(VAddr0Idx + I);
275 int VAddr0Idx =
282 const MachineOperand &Op = MI->getOperand(VAddr0Idx + I);
SIShrinkInstructions.cpp 224 int VAddr0Idx =
247 const MachineOperand &Op = MI.getOperand(VAddr0Idx + i);
290 MI.getOperand(VAddr0Idx).setReg(RC->getRegister(VgprBase));
291 MI.getOperand(VAddr0Idx).setIsUndef(IsUndef);
292 MI.getOperand(VAddr0Idx).setIsKill(IsKill);
295 MI.RemoveOperand(VAddr0Idx + 1);
SILoadStoreOptimizer.cpp 441 int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0);
442 if (VAddr0Idx >= 0) {
444 Result.NumVAddrs = SRsrcIdx - VAddr0Idx;
SIInstrInfo.cpp 348 int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0);
349 if (VAddr0Idx >= 0) {
351 for (int I = VAddr0Idx; I < SRsrcIdx; ++I)
4200 int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opcode,
4223 bool IsNSA = SRsrcIdx - VAddr0Idx > 1;
4230 VAddrWords = SRsrcIdx - VAddr0Idx;
4232 const TargetRegisterClass *RC = getOpRegClass(MI, VAddr0Idx);
7134 int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0);
7135 if (VAddr0Idx < 0)
7139 return 8 + 4 * ((RSrcIdx - VAddr0Idx + 2) / 4)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Disassembler/
AMDGPUDisassembler.cpp 588 int VAddr0Idx =
592 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1;
593 if (VAddr0Idx >= 0 && NSAArgs > 0) {
599 MI.insert(MI.begin() + VAddr0Idx + 1 + i,
686 int VAddr0Idx =
785 unsigned VAddr0 = MI.getOperand(VAddr0Idx).getReg();
789 auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass;
808 MI.getOperand(VAddr0Idx) = MCOperand::createReg(NewVAddr0);
811 MI.erase(MI.begin() + VAddr0Idx + AddrSize,
812 MI.begin() + VAddr0Idx + Info->VAddrDwords)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AsmParser/
AMDGPUAsmParser.cpp 3421 int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0);
3426 assert(VAddr0Idx != -1);
3428 assert(SrsrcIdx > VAddr0Idx);
3435 bool IsNSA = SrsrcIdx - VAddr0Idx > 1;
3437 IsNSA ? SrsrcIdx - VAddr0Idx
3438 : AMDGPU::getRegOperandSize(getMRI(), Desc, VAddr0Idx) / 4;

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