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    Searched defs:VLESIMM (Results 1 - 4 of 4) sorted by relevancy

  /src/external/gpl3/binutils/dist/opcodes/
ppc-opc.c 2463 /* The VLESIMM field in an I16A form instruction. This is split. */
3878 /* The VLESIMM field in a D form instruction. */
3879 #define VLESIMM URC + 1
3884 #define VLENSIMM VLESIMM + 1
10246 {"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
10248 {"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
10249 {"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
10251 {"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
10253 {"e_add2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
  /src/external/gpl3/binutils.old/dist/opcodes/
ppc-opc.c 2463 /* The VLESIMM field in an I16A form instruction. This is split. */
3877 /* The VLESIMM field in a D form instruction. */
3878 #define VLESIMM URC + 1
3883 #define VLENSIMM VLESIMM + 1
10181 {"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
10183 {"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
10184 {"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
10186 {"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
10188 {"e_add2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
  /src/external/gpl3/gdb/dist/opcodes/
ppc-opc.c 2395 /* The VLESIMM field in an I16A form instruction. This is split. */
3799 /* The VLESIMM field in a D form instruction. */
3800 #define VLESIMM URC + 1
3805 #define VLENSIMM VLESIMM + 1
10038 {"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
10040 {"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
10041 {"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
10043 {"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
10045 {"e_add2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
  /src/external/gpl3/gdb.old/dist/opcodes/
ppc-opc.c 2395 /* The VLESIMM field in an I16A form instruction. This is split. */
3799 /* The VLESIMM field in a D form instruction. */
3800 #define VLESIMM URC + 1
3805 #define VLENSIMM VLESIMM + 1
10027 {"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
10029 {"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
10030 {"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
10032 {"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
10034 {"e_add2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},

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