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    Searched defs:VLMUL (Results 1 - 2 of 2) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/MCTargetDesc/
RISCVBaseInfo.cpp 109 // 2:0 | vlmul[2:0] | Vector register group multiplier (LMUL) setting
110 unsigned RISCVVType::encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW,
113 unsigned VLMULBits = static_cast<unsigned>(VLMUL);
125 RISCVII::VLMUL VLMUL = getVLMUL(VType);
130 switch (VLMUL) {
131 case RISCVII::VLMUL::LMUL_RESERVED:
133 case RISCVII::VLMUL::LMUL_1:
134 case RISCVII::VLMUL::LMUL_2
    [all...]
RISCVBaseInfo.h 89 enum VLMUL {
111 static inline VLMUL getLMul(uint64_t TSFlags) {
112 return static_cast<VLMUL>((TSFlags & VLMulMask) >> VLMulShift);
322 unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic,
325 inline static RISCVII::VLMUL getVLMUL(unsigned VType) {
326 unsigned VLMUL = VType & 0x7;
327 return static_cast<RISCVII::VLMUL>(VLMUL);

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