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    Searched defs:VR1 (Results 1 - 6 of 6) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsSEFrameLowering.cpp 201 // load $vr1, FI + 4
202 // copy hi, $vr1
208 Register VR1 = MRI.createVirtualRegister(RC);
217 TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize);
218 BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill);
226 // mfhi $vr1, src
227 // store $vr1, FI + 4
233 Register VR1 = MRI.createVirtualRegister(RC);
240 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill);
241 TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize)
    [all...]
MipsSEISelLowering.cpp 3032 // li $vr1, 1
3034 // $vr0 = phi($vr2, $fbb, $vr1, $tbb)
3073 Register VR1 = RegInfo.createVirtualRegister(RC);
3074 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
3082 .addReg(VR1)
  /src/external/gpl3/binutils/dist/opcodes/
v850-opc.c 1268 #define VR1 (VECTOR5 + 1)
1271 #define VR2 (VR1 + 1)
1762 { "sttc.vr", two (0x07e0, 0x0852), two (0x07e0, 0xffff), {VR1, R2}, 0, PROCESSOR_V850E3V5_UP },
  /src/external/gpl3/binutils.old/dist/opcodes/
v850-opc.c 1268 #define VR1 (VECTOR5 + 1)
1271 #define VR2 (VR1 + 1)
1762 { "sttc.vr", two (0x07e0, 0x0852), two (0x07e0, 0xffff), {VR1, R2}, 0, PROCESSOR_V850E3V5_UP },
  /src/external/gpl3/gdb/dist/opcodes/
v850-opc.c 1268 #define VR1 (VECTOR5 + 1)
1271 #define VR2 (VR1 + 1)
1762 { "sttc.vr", two (0x07e0, 0x0852), two (0x07e0, 0xffff), {VR1, R2}, 0, PROCESSOR_V850E3V5_UP },
  /src/external/gpl3/gdb.old/dist/opcodes/
v850-opc.c 1268 #define VR1 (VECTOR5 + 1)
1271 #define VR2 (VR1 + 1)
1762 { "sttc.vr", two (0x07e0, 0x0852), two (0x07e0, 0xffff), {VR1, R2}, 0, PROCESSOR_V850E3V5_UP },

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