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    Searched defs:Val2 (Results 1 - 8 of 8) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
SelectionDAG.cpp 129 APFloat Val2 = APFloat(Val);
131 (void) Val2.convert(SelectionDAG::EVTToAPFloatSemantics(VT),
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPURegBankCombiner.cpp 55 Register Val0, Val1, Val2;
138 {MatchInfo.Val0, MatchInfo.Val1, MatchInfo.Val2}, MI.getFlags());
  /src/external/apache2/llvm/dist/clang/lib/AST/
ASTStructuralEquivalence.cpp 1633 llvm::APSInt Val2 = EC2->getInitVal();
1634 if (!llvm::APSInt::isSameValue(Val1, Val2) ||
  /src/external/apache2/llvm/dist/clang/lib/CodeGen/
CGAtomic.cpp 367 Address Val1, Address Val2,
374 llvm::Value *Desired = CGF.Builder.CreateLoad(Val2);
417 Address Val1, Address Val2,
448 emitAtomicCmpXchg(CGF, E, IsWeak, Dest, Ptr, Val1, Val2, Size, SuccessOrder,
473 emitAtomicCmpXchg(CGF, E, IsWeak, Dest, Ptr, Val1, Val2,
478 emitAtomicCmpXchg(CGF, E, IsWeak, Dest, Ptr, Val1, Val2, Size, SuccessOrder,
483 emitAtomicCmpXchg(CGF, E, IsWeak, Dest, Ptr, Val1, Val2, Size, SuccessOrder,
513 Address Ptr, Address Val1, Address Val2,
528 emitAtomicCmpXchgFailureSet(CGF, E, false, Dest, Ptr, Val1, Val2,
533 emitAtomicCmpXchgFailureSet(CGF, E, true, Dest, Ptr, Val1, Val2,
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/
InstCombineCalls.cpp 1244 // sat(sat(X + Val2) + Val) -> sat(X + (Val+Val2))
1245 // sat(sat(X - Val2) - Val) -> sat(X - (Val+Val2))
1246 // if Val and Val2 have the same sign
1249 const APInt *Val, *Val2;
1256 match(Other->getArgOperand(1), m_APInt(Val2))) {
1258 NewVal = Val->uadd_sat(*Val2);
1259 else if (Val->isNonNegative() == Val2->isNonNegative()) {
1261 NewVal = Val->sadd_ov(*Val2, Overflow)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelDAGToDAG.cpp 3072 SDValue Val2 = Ins2.getOperand(1);
3073 if (Val1.getOpcode() == ISD::FP_ROUND || Val2.getOpcode() == ISD::FP_ROUND)
3079 (Val2.getOpcode() == ISD::EXTRACT_VECTOR_ELT ||
3080 Val2.getOpcode() == ARMISD::VGETLANEu) &&
3082 isa<ConstantSDNode>(Val2.getOperand(1)) &&
3085 (Val2.getOperand(0).getValueType() == MVT::v8f16 ||
3086 Val2.getOperand(0).getValueType() == MVT::v8i16)) {
3088 unsigned ExtractLane2 = Val2.getConstantOperandVal(1);
3092 if (Val1.getOperand(0) == Val2.getOperand(0) && ExtractLane2 % 2 == 0 &&
3109 ARM::ssub_0 + ExtractLane2 / 2, dl, MVT::f32, Val2.getOperand(0))
    [all...]
ARMISelLowering.cpp 5078 int64_t Val2 = cast<ConstantSDNode>(K2)->getSExtValue();
5079 int64_t PosVal = std::max(Val1, Val2);
5080 int64_t NegVal = std::min(Val1, Val2);
5082 if (!((Val1 > Val2 && isLTorLE(CC1)) || (Val1 < Val2 && isLTorLE(CC2))) ||
5091 if (Val1 == ~Val2)
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 12558 /// <tt>(or (shl VAL1, \#N), (srl VAL2, \#RegWidth-N))</tt> and replaces it
12693 // Attempt to form an EXTR from (or (shl VAL1, #N), (srl VAL2, #RegWidth-N))
13436 SDValue Val2 = Op2.getOperand(0);
13439 SDValue AddVal = DAG.getNode(ISD::ADD, DL, ValVT, Val1, Val2);

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