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    Searched defs:VerilogDataWidth (Results 1 - 4 of 4) sorted by relevancy

  /src/external/gpl3/binutils/dist/bfd/
verilog.c 63 unsigned int VerilogDataWidth = 1;
222 + ((end - data) / VerilogDataWidth) /* Number of spaces we want to emit. */
234 if (VerilogDataWidth == 1)
250 and VerilogDataWidth is 4 then we want to emit:
254 for (src = data; src < (end - VerilogDataWidth); src += VerilogDataWidth)
256 for (i = VerilogDataWidth - 1; i >= 0; i--)
281 if ((src - data) % VerilogDataWidth == 0)
303 if (list->where % VerilogDataWidth)
309 verilog_write_address (abfd, list->where / VerilogDataWidth);
    [all...]
  /src/external/gpl3/binutils.old/dist/bfd/
verilog.c 63 unsigned int VerilogDataWidth = 1;
222 + ((end - data) / VerilogDataWidth) /* Number of spaces we want to emit. */
234 if (VerilogDataWidth == 1)
250 and VerilogDataWidth is 4 then we want to emit:
254 for (src = data; src < (end - VerilogDataWidth); src += VerilogDataWidth)
256 for (i = VerilogDataWidth - 1; i >= 0; i--)
281 if ((src - data) % VerilogDataWidth == 0)
303 if (list->where % VerilogDataWidth)
309 verilog_write_address (abfd, list->where / VerilogDataWidth);
    [all...]
  /src/external/gpl3/gdb/dist/bfd/
verilog.c 63 unsigned int VerilogDataWidth = 1;
222 + ((end - data) / VerilogDataWidth) /* Number of spaces we want to emit. */
234 if (VerilogDataWidth == 1)
250 and VerilogDataWidth is 4 then we want to emit:
254 for (src = data; src < (end - VerilogDataWidth); src += VerilogDataWidth)
256 for (i = VerilogDataWidth - 1; i >= 0; i--)
281 if ((src - data) % VerilogDataWidth == 0)
303 if (list->where % VerilogDataWidth)
309 verilog_write_address (abfd, list->where / VerilogDataWidth);
    [all...]
  /src/external/gpl3/gdb.old/dist/bfd/
verilog.c 63 unsigned int VerilogDataWidth = 1;
222 + ((end - data) / VerilogDataWidth) /* Number of spaces we want to emit. */
234 if (VerilogDataWidth == 1)
250 and VerilogDataWidth is 4 then we want to emit:
254 for (src = data; src < (end - VerilogDataWidth); src += VerilogDataWidth)
256 for (i = VerilogDataWidth - 1; i >= 0; i--)
281 if ((src - data) % VerilogDataWidth == 0)
303 if (list->where % VerilogDataWidth)
309 verilog_write_address (abfd, list->where / VerilogDataWidth);
    [all...]

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