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    Searched defs:WR (Results 1 - 8 of 8) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/fb/
nouveau_nvkm_subdev_fb_sddr2.c 69 int CL, WR, DLL = 0, ODT = 0;
74 WR = ram->next->bios.timing_10_WR;
80 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16;
93 WR = ramxlat(ramddr2_wr, WR);
94 if (CL < 0 || WR < 0)
98 ram->mr[0] |= (WR & 0x07) << 9;
nouveau_nvkm_subdev_fb_gddr3.c 78 int CL, WR, CWL, DLL = 0, ODT = 0, RON, hi;
84 WR = ram->next->bios.timing_10_WR;
92 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16;
108 WR = ramxlat(ramgddr3_wr_lo, WR);
109 if (CL < 0 || CWL < 1 || CWL > 7 || WR < 0)
120 ram->mr[1] |= (WR & 0x03) << 4;
121 ram->mr[1] |= (WR & 0x04) << 5;
nouveau_nvkm_subdev_fb_gddr5.c 43 int WL, CL, WR, at[2], dt, ds;
65 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16;
75 if (WL < 1 || WL > 7 || CL < 5 || CL > 36 || WR < 4 || WR > 35)
78 WR -= 4;
81 ram->mr[0] |= (WR & 0x0f) << 8;
123 ram->mr[8] |= (WR & 0x10) >> 3;
nouveau_nvkm_subdev_fb_sddr3.c 78 int CWL, CL, WR, DLL = 0, ODT = 0;
90 WR = ram->next->bios.timing_10_WR;
96 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16;
108 WR = ramxlat(ramddr3_wr, WR);
109 if (CL < 0 || CWL < 0 || WR < 0)
113 ram->mr[0] |= (WR & 0x07) << 9;
  /src/usr.bin/tail/
extern.h 34 #define WR(p, size) \
  /src/external/bsd/less/dist/lesstest/
pipeline.c 8 #define WR 1
29 if (verbose) fprintf(stderr, "less child: in %d, out %d, close %d,%d\n", less_in_pipe[RD], screen_in_pipe[WR], less_in_pipe[WR], screen_in_pipe[RD]);
30 close(less_in_pipe[WR]);
32 dup_std(less_in_pipe[RD], screen_in_pipe[WR]);
52 if (verbose) fprintf(stderr, "screen child: in %d, out %d, close %d\n", screen_in_pipe[RD], screen_out_pipe[WR], screen_out_pipe[RD]);
54 dup_std(screen_in_pipe[RD], screen_out_pipe[WR]);
87 pipeline->less_in_pipe[RD] = pipeline->less_in_pipe[WR] = -1;
88 pipeline->screen_in_pipe[RD] = pipeline->screen_in_pipe[WR] = -1;
89 pipeline->screen_out_pipe[RD] = pipeline->screen_out_pipe[WR] = -1
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/MCA/HardwareUnits/
RegisterFile.cpp 119 WriteRef &WR = RegisterMappings[RegID].first;
120 if (WR.getWriteState() == &WS)
121 WR.notifyExecuted(CurrentCycle);
336 WriteRef &WR = RegisterMappings[RegID].first;
337 if (WR.getWriteState() == &WS)
338 WR.commit();
469 unsigned RegisterFile::getElapsedCyclesFromWriteBack(const WriteRef &WR) const {
470 assert(WR.hasKnownWriteBackCycle() && "Write hasn't been committed yet!");
471 return CurrentCycle - WR.getWriteBackCycle();
491 const WriteRef &WR = RegisterMappings[RegID].first
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Analysis/
MemorySSA.cpp 874 UpwardsWalkResult WR = walkToPhiOrClobber(Paths[Paused]);
875 if (WR.IsKnownClobber)
876 Clobbers.push_back({WR.Result, Paused});
879 DefChainEnd = WR.Result;

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