| /src/external/gpl3/binutils/dist/opcodes/ |
| mips16-opc.c | 165 #define WR_1 INSN_WRITE_1
171 #define MOD_1 (WR_1|RD_1)
214 {"la", "x,A", 0x0800, 0xf800, WR_1, RD_PC|AL, I1, 0, 0 },
216 {"addiu", "y,x,F", 0x4000, 0xf810, WR_1|RD_2, 0, I1, 0, 0 },
220 {"addiu", "x,P,V", 0x0800, 0xf800, WR_1, RD_PC, I1, 0, 0 },
221 {"addiu", "x,S,V", 0x0000, 0xf800, WR_1, SH|RD_SP, 0, E2, 0 },
222 {"addiu", "x,S,V", 0x0000, 0xf800, WR_1, RD_SP, I1, 0, 0 },
223 {"addiu", "x,S,V", 0xf0000000, 0xf800f8e0, WR_1, RD_SP, 0, E2, 0 },
224 {"addiu", "x,G,V", 0xf0000020, 0xf800f8e0, WR_1|RD_2, 0, 0, E2, 0 },
225 {"addu", "z,v,y", 0xe001, 0xf803, WR_1|RD_2|RD_3, SH, I1, 0, 0 }
[all...] |
| micromips-opc.c | 219 #define WR_1 INSN_WRITE_1
225 #define MOD_1 (WR_1|RD_1)
313 {"li", "md,mI", 0xec00, 0xfc00, WR_1, 0, I1, 0, 0 },
314 {"li", "t,j", 0x30000000, 0xfc1f0000, WR_1, AL, I1, 0, 0 }, /* addiu */
315 {"li", "t,i", 0x50000000, 0xfc1f0000, WR_1, AL, I1, 0, 0 }, /* ori */
318 {"move", "mp,mj", 0x0c00, 0xfc00, WR_1|RD_2, 0, I1, 0, 0 },
319 {"move", "d,s", 0x00000290, 0xffe007ff, WR_1|RD_2, AL, I1, 0, 0 }, /* or */
320 {"move", "d,s", 0x58000150, 0xffe007ff, WR_1|RD_2, AL, I3, 0, 0 }, /* daddu */
321 {"move", "d,s", 0x00000150, 0xffe007ff, WR_1|RD_2, AL, I1, 0, 0 }, /* addu */
331 {"abs.d", "T,V", 0x5400237b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 }
[all...] |
| mips-opc.c | 233 #define WR_1 INSN_WRITE_1
240 #define MOD_1 (WR_1|RD_1)
458 {"li", "t,j", 0x24000000, 0xffe00000, WR_1, AL, I1, 0, 0 }, /* addiu */
459 {"li", "t,i", 0x34000000, 0xffe00000, WR_1, AL, I1, 0, 0 }, /* ori */
462 {"move", "d,s", 0x00000025, 0xfc1f07ff, WR_1|RD_2, AL, I1, 0, 0 },/* or */
463 {"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_1|RD_2, AL, I3, 0, 0 },/* daddu */
464 {"move", "d,s", 0x00000021, 0xfc1f07ff, WR_1|RD_2, AL, I1, 0, 0 },/* addu */
471 {"lapc", "s,-A", 0xec000000, 0xfc180000, WR_1, RD_pc, I37, 0, 0 },
477 {"campi", "d,s", 0x70000075, 0xfc1f07ff, WR_1|RD_2, 0, 0, LCAM, 0 },
478 {"campv", "d,s", 0x70000035, 0xfc1f07ff, WR_1|RD_2, 0, 0, LCAM, 0 }
[all...] |
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| mips16-opc.c | 165 #define WR_1 INSN_WRITE_1
171 #define MOD_1 (WR_1|RD_1)
214 {"la", "x,A", 0x0800, 0xf800, WR_1, RD_PC|AL, I1, 0, 0 },
216 {"addiu", "y,x,F", 0x4000, 0xf810, WR_1|RD_2, 0, I1, 0, 0 },
220 {"addiu", "x,P,V", 0x0800, 0xf800, WR_1, RD_PC, I1, 0, 0 },
221 {"addiu", "x,S,V", 0x0000, 0xf800, WR_1, SH|RD_SP, 0, E2, 0 },
222 {"addiu", "x,S,V", 0x0000, 0xf800, WR_1, RD_SP, I1, 0, 0 },
223 {"addiu", "x,S,V", 0xf0000000, 0xf800f8e0, WR_1, RD_SP, 0, E2, 0 },
224 {"addiu", "x,G,V", 0xf0000020, 0xf800f8e0, WR_1|RD_2, 0, 0, E2, 0 },
225 {"addu", "z,v,y", 0xe001, 0xf803, WR_1|RD_2|RD_3, SH, I1, 0, 0 }
[all...] |
| micromips-opc.c | 219 #define WR_1 INSN_WRITE_1
225 #define MOD_1 (WR_1|RD_1)
313 {"li", "md,mI", 0xec00, 0xfc00, WR_1, 0, I1, 0, 0 },
314 {"li", "t,j", 0x30000000, 0xfc1f0000, WR_1, AL, I1, 0, 0 }, /* addiu */
315 {"li", "t,i", 0x50000000, 0xfc1f0000, WR_1, AL, I1, 0, 0 }, /* ori */
318 {"move", "mp,mj", 0x0c00, 0xfc00, WR_1|RD_2, 0, I1, 0, 0 },
319 {"move", "d,s", 0x00000290, 0xffe007ff, WR_1|RD_2, AL, I1, 0, 0 }, /* or */
320 {"move", "d,s", 0x58000150, 0xffe007ff, WR_1|RD_2, AL, I3, 0, 0 }, /* daddu */
321 {"move", "d,s", 0x00000150, 0xffe007ff, WR_1|RD_2, AL, I1, 0, 0 }, /* addu */
331 {"abs.d", "T,V", 0x5400237b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 }
[all...] |
| mips-opc.c | 233 #define WR_1 INSN_WRITE_1
240 #define MOD_1 (WR_1|RD_1)
458 {"li", "t,j", 0x24000000, 0xffe00000, WR_1, AL, I1, 0, 0 }, /* addiu */
459 {"li", "t,i", 0x34000000, 0xffe00000, WR_1, AL, I1, 0, 0 }, /* ori */
462 {"move", "d,s", 0x00000025, 0xfc1f07ff, WR_1|RD_2, AL, I1, 0, 0 },/* or */
463 {"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_1|RD_2, AL, I3, 0, 0 },/* daddu */
464 {"move", "d,s", 0x00000021, 0xfc1f07ff, WR_1|RD_2, AL, I1, 0, 0 },/* addu */
471 {"lapc", "s,-A", 0xec000000, 0xfc180000, WR_1, RD_pc, I37, 0, 0 },
477 {"campi", "d,s", 0x70000075, 0xfc1f07ff, WR_1|RD_2, 0, 0, LCAM, 0 },
478 {"campv", "d,s", 0x70000035, 0xfc1f07ff, WR_1|RD_2, 0, 0, LCAM, 0 }
[all...] |
| /src/external/gpl3/gdb/dist/opcodes/ |
| mips16-opc.c | 165 #define WR_1 INSN_WRITE_1
171 #define MOD_1 (WR_1|RD_1)
214 {"la", "x,A", 0x0800, 0xf800, WR_1, RD_PC|AL, I1, 0, 0 },
216 {"addiu", "y,x,F", 0x4000, 0xf810, WR_1|RD_2, 0, I1, 0, 0 },
220 {"addiu", "x,P,V", 0x0800, 0xf800, WR_1, RD_PC, I1, 0, 0 },
221 {"addiu", "x,S,V", 0x0000, 0xf800, WR_1, SH|RD_SP, 0, E2, 0 },
222 {"addiu", "x,S,V", 0x0000, 0xf800, WR_1, RD_SP, I1, 0, 0 },
223 {"addiu", "x,S,V", 0xf0000000, 0xf800f8e0, WR_1, RD_SP, 0, E2, 0 },
224 {"addiu", "x,G,V", 0xf0000020, 0xf800f8e0, WR_1|RD_2, 0, 0, E2, 0 },
225 {"addu", "z,v,y", 0xe001, 0xf803, WR_1|RD_2|RD_3, SH, I1, 0, 0 }
[all...] |
| micromips-opc.c | 219 #define WR_1 INSN_WRITE_1
225 #define MOD_1 (WR_1|RD_1)
313 {"li", "md,mI", 0xec00, 0xfc00, WR_1, 0, I1, 0, 0 },
314 {"li", "t,j", 0x30000000, 0xfc1f0000, WR_1, AL, I1, 0, 0 }, /* addiu */
315 {"li", "t,i", 0x50000000, 0xfc1f0000, WR_1, AL, I1, 0, 0 }, /* ori */
318 {"move", "mp,mj", 0x0c00, 0xfc00, WR_1|RD_2, 0, I1, 0, 0 },
319 {"move", "d,s", 0x00000290, 0xffe007ff, WR_1|RD_2, AL, I1, 0, 0 }, /* or */
320 {"move", "d,s", 0x58000150, 0xffe007ff, WR_1|RD_2, AL, I3, 0, 0 }, /* daddu */
321 {"move", "d,s", 0x00000150, 0xffe007ff, WR_1|RD_2, AL, I1, 0, 0 }, /* addu */
331 {"abs.d", "T,V", 0x5400237b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 }
[all...] |
| mips-opc.c | 233 #define WR_1 INSN_WRITE_1
240 #define MOD_1 (WR_1|RD_1)
458 {"li", "t,j", 0x24000000, 0xffe00000, WR_1, AL, I1, 0, 0 }, /* addiu */
459 {"li", "t,i", 0x34000000, 0xffe00000, WR_1, AL, I1, 0, 0 }, /* ori */
462 {"move", "d,s", 0x00000025, 0xfc1f07ff, WR_1|RD_2, AL, I1, 0, 0 },/* or */
463 {"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_1|RD_2, AL, I3, 0, 0 },/* daddu */
464 {"move", "d,s", 0x00000021, 0xfc1f07ff, WR_1|RD_2, AL, I1, 0, 0 },/* addu */
471 {"lapc", "s,-A", 0xec000000, 0xfc180000, WR_1, RD_pc, I37, 0, 0 },
477 {"campi", "d,s", 0x70000075, 0xfc1f07ff, WR_1|RD_2, 0, 0, LCAM, 0 },
478 {"campv", "d,s", 0x70000035, 0xfc1f07ff, WR_1|RD_2, 0, 0, LCAM, 0 }
[all...] |
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| mips16-opc.c | 165 #define WR_1 INSN_WRITE_1
171 #define MOD_1 (WR_1|RD_1)
214 {"la", "x,A", 0x0800, 0xf800, WR_1, RD_PC|AL, I1, 0, 0 },
216 {"addiu", "y,x,F", 0x4000, 0xf810, WR_1|RD_2, 0, I1, 0, 0 },
220 {"addiu", "x,P,V", 0x0800, 0xf800, WR_1, RD_PC, I1, 0, 0 },
221 {"addiu", "x,S,V", 0x0000, 0xf800, WR_1, SH|RD_SP, 0, E2, 0 },
222 {"addiu", "x,S,V", 0x0000, 0xf800, WR_1, RD_SP, I1, 0, 0 },
223 {"addiu", "x,S,V", 0xf0000000, 0xf800f8e0, WR_1, RD_SP, 0, E2, 0 },
224 {"addiu", "x,G,V", 0xf0000020, 0xf800f8e0, WR_1|RD_2, 0, 0, E2, 0 },
225 {"addu", "z,v,y", 0xe001, 0xf803, WR_1|RD_2|RD_3, SH, I1, 0, 0 }
[all...] |
| micromips-opc.c | 211 #define WR_1 INSN_WRITE_1
217 #define MOD_1 (WR_1|RD_1)
302 {"li", "md,mI", 0xec00, 0xfc00, WR_1, 0, I1, 0, 0 },
303 {"li", "t,j", 0x30000000, 0xfc1f0000, WR_1, INSN2_ALIAS, I1, 0, 0 }, /* addiu */
304 {"li", "t,i", 0x50000000, 0xfc1f0000, WR_1, INSN2_ALIAS, I1, 0, 0 }, /* ori */
307 {"move", "mp,mj", 0x0c00, 0xfc00, WR_1|RD_2, 0, I1, 0, 0 },
308 {"move", "d,s", 0x00000290, 0xffe007ff, WR_1|RD_2, INSN2_ALIAS, I1, 0, 0 }, /* or */
309 {"move", "d,s", 0x58000150, 0xffe007ff, WR_1|RD_2, INSN2_ALIAS, I3, 0, 0 }, /* daddu */
310 {"move", "d,s", 0x00000150, 0xffe007ff, WR_1|RD_2, INSN2_ALIAS, I1, 0, 0 }, /* addu */
320 {"abs.d", "T,V", 0x5400237b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 }
[all...] |
| mips-opc.c | 232 #define WR_1 INSN_WRITE_1
239 #define MOD_1 (WR_1|RD_1)
457 {"li", "t,j", 0x24000000, 0xffe00000, WR_1, INSN2_ALIAS, I1, 0, 0 }, /* addiu */
458 {"li", "t,i", 0x34000000, 0xffe00000, WR_1, INSN2_ALIAS, I1, 0, 0 }, /* ori */
461 {"move", "d,s", 0x00000025, 0xfc1f07ff, WR_1|RD_2, INSN2_ALIAS, I1, 0, 0 },/* or */
462 {"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_1|RD_2, INSN2_ALIAS, I3, 0, 0 },/* daddu */
463 {"move", "d,s", 0x00000021, 0xfc1f07ff, WR_1|RD_2, INSN2_ALIAS, I1, 0, 0 },/* addu */
470 {"lapc", "s,-A", 0xec000000, 0xfc180000, WR_1, RD_pc, I37, 0, 0 },
476 {"campi", "d,s", 0x70000075, 0xfc1f07ff, WR_1|RD_2, 0, 0, LCAM, 0 },
477 {"campv", "d,s", 0x70000035, 0xfc1f07ff, WR_1|RD_2, 0, 0, LCAM, 0 }
[all...] |
