| /src/external/gpl3/binutils/dist/opcodes/ |
| micromips-opc.c | 246 #define WR_C2 INSN_COP 574 {"ctc2", "t,g", 0x0000dd3c, 0xfc00ffff, RD_1|WR_C2|WR_CC, 0, I1, 0, 0 }, 658 {"dmtc2", "t,G", 0x00007d3c, 0xfc00ffff, RD_1|WR_C2|WR_CC, 0, I3, 0, 0 }, 659 /*{"dmtc2", "t,G,H", 0x58000683, 0xfc001fff, RD_1|WR_C2|WR_CC, 0, I3, 0, 0 },*/ 933 {"mtc2", "t,G", 0x00005d3c, 0xfc00ffff, RD_1|WR_C2|WR_CC, 0, I1, 0, 0 }, 940 {"mthc2", "t,G", 0x00009d3c, 0xfc00ffff, RD_1|WR_C2|WR_CC, 0, I1, 0, 0 }, 953 {"mttc2", "t,G", 0x00000446, 0xfc00ffff, RD_1|WR_C2|WR_CC|TRAP|CM, AL, 0, MT32, 0 }, 958 {"mtthc2", "t,G", 0x00000646, 0xfc00ffff, RD_1|WR_C2|WR_CC|TRAP|CM, AL, 0, MT32, 0 },
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| mips-opc.c | 252 #define WR_C2 INSN_COP 1285 {"ldc2", "E,+:(d)", 0x49c00000, 0xffe00000, RD_3|WR_C2|CLD, 0, I37, 0, 0 }, 1316 {"lqc2", "+7,o(b)", 0xd8000000, 0xfc000000, RD_3|WR_C2|LM, 0, EE, 0, 0 }, 1332 {"lwc2", "E,+:(d)", 0x49400000, 0xffe00000, RD_3|WR_C2|CLD, 0, I37, 0, 0 }, 1575 {"mttc2", "t,G", 0x41800024, 0xffe007ff, RD_1|WR_C2|WR_CC|TRAP|CM, AL, 0, MT32, IOCT|IOCTP|IOCT2 }, 1580 {"mtthc2", "t,G", 0x41800034, 0xffe007ff, RD_1|WR_C2|WR_CC|TRAP|CM, AL, 0, MT32, IOCT|IOCTP|IOCT2 }, 3387 {"dmtc2", "t,i", 0x48a00000, 0xffe00000, RD_1|WR_C2|WR_CC|CM, 0, IOCT, 0, 0 }, 3388 {"dmtc2", "t,G", 0x48a00000, 0xffe007ff, RD_1|WR_C2|WR_CC|CM, 0, I3, 0, N54|IOCT|IOCTP|IOCT2|EE }, 3389 {"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, RD_1|WR_C2|WR_CC|CM, 0, I64, 0, IOCT|IOCTP|IOCT2 }, 3396 {"mtc2", "t,G", 0x48800000, 0xffe007ff, RD_1|WR_C2|WR_CC|CM, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|EE } [all...] |
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| micromips-opc.c | 246 #define WR_C2 INSN_COP 574 {"ctc2", "t,g", 0x0000dd3c, 0xfc00ffff, RD_1|WR_C2|WR_CC, 0, I1, 0, 0 }, 658 {"dmtc2", "t,G", 0x00007d3c, 0xfc00ffff, RD_1|WR_C2|WR_CC, 0, I3, 0, 0 }, 659 /*{"dmtc2", "t,G,H", 0x58000683, 0xfc001fff, RD_1|WR_C2|WR_CC, 0, I3, 0, 0 },*/ 933 {"mtc2", "t,G", 0x00005d3c, 0xfc00ffff, RD_1|WR_C2|WR_CC, 0, I1, 0, 0 }, 940 {"mthc2", "t,G", 0x00009d3c, 0xfc00ffff, RD_1|WR_C2|WR_CC, 0, I1, 0, 0 }, 953 {"mttc2", "t,G", 0x00000446, 0xfc00ffff, RD_1|WR_C2|WR_CC|TRAP|CM, AL, 0, MT32, 0 }, 958 {"mtthc2", "t,G", 0x00000646, 0xfc00ffff, RD_1|WR_C2|WR_CC|TRAP|CM, AL, 0, MT32, 0 },
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| mips-opc.c | 252 #define WR_C2 INSN_COP 1285 {"ldc2", "E,+:(d)", 0x49c00000, 0xffe00000, RD_3|WR_C2|CLD, 0, I37, 0, 0 }, 1316 {"lqc2", "+7,o(b)", 0xd8000000, 0xfc000000, RD_3|WR_C2|LM, 0, EE, 0, 0 }, 1332 {"lwc2", "E,+:(d)", 0x49400000, 0xffe00000, RD_3|WR_C2|CLD, 0, I37, 0, 0 }, 1575 {"mttc2", "t,G", 0x41800024, 0xffe007ff, RD_1|WR_C2|WR_CC|TRAP|CM, AL, 0, MT32, IOCT|IOCTP|IOCT2 }, 1580 {"mtthc2", "t,G", 0x41800034, 0xffe007ff, RD_1|WR_C2|WR_CC|TRAP|CM, AL, 0, MT32, IOCT|IOCTP|IOCT2 }, 3387 {"dmtc2", "t,i", 0x48a00000, 0xffe00000, RD_1|WR_C2|WR_CC|CM, 0, IOCT, 0, 0 }, 3388 {"dmtc2", "t,G", 0x48a00000, 0xffe007ff, RD_1|WR_C2|WR_CC|CM, 0, I3, 0, N54|IOCT|IOCTP|IOCT2|EE }, 3389 {"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, RD_1|WR_C2|WR_CC|CM, 0, I64, 0, IOCT|IOCTP|IOCT2 }, 3396 {"mtc2", "t,G", 0x48800000, 0xffe007ff, RD_1|WR_C2|WR_CC|CM, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|EE } [all...] |
| /src/external/gpl3/gdb/dist/opcodes/ |
| micromips-opc.c | 246 #define WR_C2 INSN_COP 574 {"ctc2", "t,g", 0x0000dd3c, 0xfc00ffff, RD_1|WR_C2|WR_CC, 0, I1, 0, 0 }, 658 {"dmtc2", "t,G", 0x00007d3c, 0xfc00ffff, RD_1|WR_C2|WR_CC, 0, I3, 0, 0 }, 659 /*{"dmtc2", "t,G,H", 0x58000683, 0xfc001fff, RD_1|WR_C2|WR_CC, 0, I3, 0, 0 },*/ 933 {"mtc2", "t,G", 0x00005d3c, 0xfc00ffff, RD_1|WR_C2|WR_CC, 0, I1, 0, 0 }, 940 {"mthc2", "t,G", 0x00009d3c, 0xfc00ffff, RD_1|WR_C2|WR_CC, 0, I1, 0, 0 }, 953 {"mttc2", "t,G", 0x00000446, 0xfc00ffff, RD_1|WR_C2|WR_CC|TRAP|CM, AL, 0, MT32, 0 }, 958 {"mtthc2", "t,G", 0x00000646, 0xfc00ffff, RD_1|WR_C2|WR_CC|TRAP|CM, AL, 0, MT32, 0 },
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| mips-opc.c | 252 #define WR_C2 INSN_COP 1285 {"ldc2", "E,+:(d)", 0x49c00000, 0xffe00000, RD_3|WR_C2|CLD, 0, I37, 0, 0 }, 1316 {"lqc2", "+7,o(b)", 0xd8000000, 0xfc000000, RD_3|WR_C2|LM, 0, EE, 0, 0 }, 1332 {"lwc2", "E,+:(d)", 0x49400000, 0xffe00000, RD_3|WR_C2|CLD, 0, I37, 0, 0 }, 1575 {"mttc2", "t,G", 0x41800024, 0xffe007ff, RD_1|WR_C2|WR_CC|TRAP|CM, AL, 0, MT32, IOCT|IOCTP|IOCT2 }, 1580 {"mtthc2", "t,G", 0x41800034, 0xffe007ff, RD_1|WR_C2|WR_CC|TRAP|CM, AL, 0, MT32, IOCT|IOCTP|IOCT2 }, 3387 {"dmtc2", "t,i", 0x48a00000, 0xffe00000, RD_1|WR_C2|WR_CC|CM, 0, IOCT, 0, 0 }, 3388 {"dmtc2", "t,G", 0x48a00000, 0xffe007ff, RD_1|WR_C2|WR_CC|CM, 0, I3, 0, N54|IOCT|IOCTP|IOCT2|EE }, 3389 {"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, RD_1|WR_C2|WR_CC|CM, 0, I64, 0, IOCT|IOCTP|IOCT2 }, 3396 {"mtc2", "t,G", 0x48800000, 0xffe007ff, RD_1|WR_C2|WR_CC|CM, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|EE } [all...] |
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| micromips-opc.c | 238 #define WR_C2 INSN_COP 560 {"ctc2", "t,g", 0x0000dd3c, 0xfc00ffff, RD_1|WR_C2|WR_CC, 0, I1, 0, 0 }, 641 {"dmtc2", "t,G", 0x00007d3c, 0xfc00ffff, RD_1|WR_C2|WR_CC, 0, I3, 0, 0 }, 642 /*{"dmtc2", "t,G,H", 0x58000683, 0xfc001fff, RD_1|WR_C2|WR_CC, 0, I3, 0, 0 },*/ 890 {"mtc2", "t,G", 0x00005d3c, 0xfc00ffff, RD_1|WR_C2|WR_CC, 0, I1, 0, 0 }, 899 {"mthc2", "t,G", 0x00009d3c, 0xfc00ffff, RD_1|WR_C2|WR_CC, 0, I1, 0, 0 },
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| mips-opc.c | 251 #define WR_C2 INSN_COP 1284 {"ldc2", "E,+:(d)", 0x49c00000, 0xffe00000, RD_3|WR_C2|CLD, 0, I37, 0, 0 }, 1315 {"lqc2", "+7,o(b)", 0xd8000000, 0xfc000000, RD_3|WR_C2|LM, 0, EE, 0, 0 }, 1331 {"lwc2", "E,+:(d)", 0x49400000, 0xffe00000, RD_3|WR_C2|CLD, 0, I37, 0, 0 }, 1568 {"mttc2", "t,G", 0x41800024, 0xffe007ff, RD_1|WR_C2|WR_CC|TRAP|CM, 0, 0, MT32, IOCT|IOCTP|IOCT2 }, 1575 {"mtthc2", "t,G", 0x41800034, 0xffe007ff, RD_1|WR_C2|WR_CC|TRAP|CM, 0, 0, MT32, IOCT|IOCTP|IOCT2 }, 3382 {"dmtc2", "t,i", 0x48a00000, 0xffe00000, RD_1|WR_C2|WR_CC|CM, 0, IOCT, 0, 0 }, 3383 {"dmtc2", "t,G", 0x48a00000, 0xffe007ff, RD_1|WR_C2|WR_CC|CM, 0, I3, 0, N54|IOCT|IOCTP|IOCT2|EE }, 3384 {"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, RD_1|WR_C2|WR_CC|CM, 0, I64, 0, IOCT|IOCTP|IOCT2 }, 3391 {"mtc2", "t,G", 0x48800000, 0xffe007ff, RD_1|WR_C2|WR_CC|CM, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|EE } [all...] |