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    Searched defs:Writes (Results 1 - 10 of 10) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/MCA/Stages/
InOrderIssueStage.cpp 97 SmallVector<WriteRef, 4> Writes;
104 PRF.collectWrites(STI, RS, Writes, CommittedWrites);
105 for (const WriteRef &WR : Writes) {
125 Writes.clear();
166 // Delay the instruction to ensure that writes occur in program order
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
MachineInstrBundle.h 223 /// Writes - One of the operands writes the virtual register.
224 bool Writes;
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
LoopDataPrefetch.cpp 41 PrefetchWrites("loop-prefetch-writes", cl::Hidden, cl::init(false),
235 bool Writes;
241 : LSCEVAddRec(L), InsertPt(nullptr), Writes(false), MemI(nullptr) {
246 /// one, 'InsertPt' and 'Writes' will be updated as required.
254 Writes = isa<StoreInst>(I);
265 Writes = true;
404 ConstantInt::get(I32, P.Writes),
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMParallelDSP.cpp 352 SmallVector<Instruction*, 8> Writes;
361 Writes.push_back(&I);
376 // Record any writes that may alias a load.
378 for (auto Write : Writes) {
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
CodeGenSchedule.h 45 /// or a sequence of writes on one operand.
109 /// Writes and ReadDefs are empty. ProcIndices contains 0 for any processor.
118 /// provided InstrRW records for this class. ItinClassDef or Writes/Reads may
126 /// that mapped the itinerary class to the variant Writes or Reads.
132 IdxVec Writes;
152 return ItinClassDef == IC && makeArrayRef(Writes) == W &&
562 void findRWs(const RecVec &RWDefs, IdxVec &Writes, IdxVec &Reads) const;
638 void collectRWResources(ArrayRef<unsigned> Writes, ArrayRef<unsigned> Reads,
SubtargetEmitter.cpp 1023 IdxVec Writes = SC.Writes;
1037 Writes.clear();
1040 Writes, Reads);
1043 if (Writes.empty()) {
1049 Writes, Reads);
1053 if (Writes.empty()) {
1060 // Sum resources across all operand writes.
1065 for (unsigned W : Writes) {
CodeGenSchedule.cpp 569 RecVec Seq = RWDef->getValueAsListOfDefs("Writes");
588 // Reserve idx=0 for invalid writes/reads.
658 // itinerary resources. Index reads and writes in separate domains.
673 findRWs(CGRW.TheDef->getValueAsListOfDefs("Writes"), CGRW.Sequence,
687 dbgs() << "\n+++ SCHED READS and WRITES (collectSchedRW) +++\n";
708 /// Compute a SchedWrite name from a sequence of writes.
756 IdxVec &Writes, IdxVec &Reads) const {
760 findRWs(WriteDefs, Writes, false);
829 // Find the existing SchedWrite that models this sequence of writes.
874 IdxVec Writes, Reads
    [all...]
  /src/external/apache2/llvm/dist/llvm/include/llvm/MCA/
Instruction.h 11 /// register writes and instructions.
38 // Operand index. The index is negative for implicit writes only.
39 // For implicit writes, the actual operand index is computed performing
108 // For implicit writes, this field always matches the value of
131 // that we don't break the WAW, and the two writes can be merged together.
226 /// writes only partially update the register associated to this read.
233 // Number of writes that contribute to the definition of RegisterID.
238 // the latency of all the dependent writes. It defaults to UNKNOWN_CYCLES.
243 // dependent writes (i.e. field DependentWrite) is zero, this value is
248 // This field is set to true only if there are no dependent writes, an
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
MachinePipeliner.cpp 2561 bool Reads, Writes;
2562 std::tie(Reads, Writes) =
2572 } else if (MO.isUse() && Writes && stageScheduled(*I) == StageInst1) {
2581 } else if (MO.isUse() && Writes && stageScheduled(*I) > StageInst1) {
2589 } else if (MO.isUse() && Writes && stageScheduled(*I) < StageInst1) {
RegisterCoalescer.cpp 1751 bool Reads, Writes;
1752 std::tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops);
2683 // An IMPLICIT_DEF writes undef values.

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