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      1 /*	$NetBSD: x1830-cgu.h,v 1.1.1.1 2021/11/07 16:49:59 jmcneill Exp $	*/
      2 
      3 /* SPDX-License-Identifier: GPL-2.0 */
      4 /*
      5  * This header provides clock numbers for the ingenic,x1830-cgu DT binding.
      6  *
      7  * They are roughly ordered as:
      8  *   - external clocks
      9  *   - PLLs
     10  *   - muxes/dividers in the order they appear in the x1830 programmers manual
     11  *   - gates in order of their bit in the CLKGR* registers
     12  */
     13 
     14 #ifndef __DT_BINDINGS_CLOCK_X1830_CGU_H__
     15 #define __DT_BINDINGS_CLOCK_X1830_CGU_H__
     16 
     17 #define X1830_CLK_EXCLK			0
     18 #define X1830_CLK_RTCLK			1
     19 #define X1830_CLK_APLL			2
     20 #define X1830_CLK_MPLL			3
     21 #define X1830_CLK_EPLL			4
     22 #define X1830_CLK_VPLL			5
     23 #define X1830_CLK_OTGPHY		6
     24 #define X1830_CLK_SCLKA			7
     25 #define X1830_CLK_CPUMUX		8
     26 #define X1830_CLK_CPU			9
     27 #define X1830_CLK_L2CACHE		10
     28 #define X1830_CLK_AHB0			11
     29 #define X1830_CLK_AHB2PMUX		12
     30 #define X1830_CLK_AHB2			13
     31 #define X1830_CLK_PCLK			14
     32 #define X1830_CLK_DDR			15
     33 #define X1830_CLK_MAC			16
     34 #define X1830_CLK_LCD			17
     35 #define X1830_CLK_MSCMUX		18
     36 #define X1830_CLK_MSC0			19
     37 #define X1830_CLK_MSC1			20
     38 #define X1830_CLK_SSIPLL		21
     39 #define X1830_CLK_SSIPLL_DIV2	22
     40 #define X1830_CLK_SSIMUX		23
     41 #define X1830_CLK_EMC			24
     42 #define X1830_CLK_EFUSE			25
     43 #define X1830_CLK_OTG			26
     44 #define X1830_CLK_SSI0			27
     45 #define X1830_CLK_SMB0			28
     46 #define X1830_CLK_SMB1			29
     47 #define X1830_CLK_SMB2			30
     48 #define X1830_CLK_UART0			31
     49 #define X1830_CLK_UART1			32
     50 #define X1830_CLK_SSI1			33
     51 #define X1830_CLK_SFC			34
     52 #define X1830_CLK_PDMA			35
     53 #define X1830_CLK_TCU			36
     54 #define X1830_CLK_DTRNG			37
     55 #define X1830_CLK_OST			38
     56 #define X1830_CLK_EXCLK_DIV512	39
     57 #define X1830_CLK_RTC			40
     58 
     59 #endif /* __DT_BINDINGS_CLOCK_X1830_CGU_H__ */
     60