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    Searched defs:X86 (Results 1 - 10 of 10) sorted by relevancy

  /src/sys/arch/i386/bioscall/
Makefile 7 X86=${KSRC}/arch/x86
25 x86:
26 @rm -f x86 && ln -s ${X86}/include x86
36 assym.h: machine x86 genassym.cf
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/
X86FixupKinds.h 1 //===-- X86FixupKinds.h - X86 Specific Fixup Entries ------------*- C++ -*-===//
15 namespace X86 {
X86BaseInfo.h 1 //===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===//
10 // the X86 target useful for the compiler back-end and the MC libraries.
26 namespace X86 {
78 // X86 specific condition code. These correspond to X86_*_COND in
102 // which can't be represented on x86 with a single condition. These
145 case X86::TEST16i16:
146 case X86::TEST16mr:
147 case X86::TEST16ri:
148 case X86::TEST16rr:
149 case X86::TEST32i32
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  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86InstrInfo.h 1 //===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===//
9 // This file contains the X86 implementation of the TargetInstrInfo class.
29 namespace X86 {
71 } // namespace X86
113 return Op + X86::AddrSegmentReg <= MI.getNumOperands() &&
114 MI.getOperand(Op + X86::AddrBaseReg).isReg() &&
115 isScale(MI.getOperand(Op + X86::AddrScaleAmt)) &&
116 MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
117 (MI.getOperand(Op + X86::AddrDisp).isImm() ||
118 MI.getOperand(Op + X86::AddrDisp).isGlobal() |
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X86ISelLowering.h 1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
9 // This file defines the interfaces that X86 uses to lower LLVM code into a
24 // X86 Specific DAG Nodes
34 /// X86 funnel/double shift i16 instructions. These correspond to
35 /// X86::SHLDW and X86::SHRDW instructions which have different amt
42 /// to X86::ANDPS or X86::ANDPD.
46 /// to X86::ORPS or X86::ORPD
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  /src/external/apache2/llvm/dist/llvm/include/llvm/Support/
X86TargetParser.h 1 //===-- X86TargetParser - Parser for X86 features ---------------*- C++ -*-===//
9 // This file implements a target parser to recognise X86 hardware features.
22 namespace X86 {
157 } // namespace X86
  /src/external/apache2/llvm/dist/clang/include/clang/Basic/
TargetBuiltins.h 108 /// X86 builtins
109 namespace X86 {
326 X86::LastTSBuiltin, VE::LastTSBuiltin, RISCV::LastTSBuiltin,
  /src/external/apache2/llvm/dist/llvm/include/llvm/BinaryFormat/
Minidump.h 148 } X86;
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/Disassembler/
X86Disassembler.cpp 1 //===-- X86Disassembler.cpp - Disassembler for x86 and x86_64 -------------===//
9 // This file is part of the X86 Disassembler.
14 // The X86 disassembler is a table-driven disassembler for the 16-, 32-, and
15 // 64-bit X86 instruction sets. The main decode sequence for an assembly
94 #define DEBUG_TYPE "x86-disassembler"
233 ((nextByte & 0xfe) == 0x86 || (nextByte & 0xf8) == 0x90))) {
1657 namespace X86 {
1666 } // namespace X86
1676 /// Generic disassembler for all X86 platforms. All each platform class should
1701 if (FB[X86::Mode16Bit])
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  /src/external/apache2/llvm/dist/llvm/include/llvm/MC/
MCAsmInfo.h 42 X86, /// Windows x86, uses no CFI, just EH tables
769 WinEHEncodingType != WinEH::EncodingType::X86);

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