| /src/external/gpl3/binutils/dist/opcodes/ |
| ppc-opc.c | 4104 #define P_XX1_MASK (PREFIX_MASK | XX1_MASK)
4644 #define XX1_MASK X (0x3f, 0x3ff)
4646 /* An XX1_MASK with the RB field fixed. */
4647 #define XX1RB_MASK (XX1_MASK | RB_MASK)
7242 {"lxsiwzx", X(31,12), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
7244 {"lxvrbx", X(31,13), XX1_MASK, POWER10, 0, {XT6, RA0, RB}},
7307 {"lxvrhx", X(31,45), XX1_MASK, POWER10, 0, {XT6, RA0, RB}},
7317 {"lxsiwax", X(31,76), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
7319 {"lxvrwx", X(31,77), XX1_MASK, POWER10, 0, {XT6, RA0, RB}},
7416 {"lxvrdx", X(31,109), XX1_MASK, POWER10, 0, {XT6, RA0, RB}}
[all...] |
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| ppc-opc.c | 4103 #define P_XX1_MASK (PREFIX_MASK | XX1_MASK)
4628 #define XX1_MASK X (0x3f, 0x3ff)
4630 /* An XX1_MASK with the RB field fixed. */
4631 #define XX1RB_MASK (XX1_MASK | RB_MASK)
7214 {"lxsiwzx", X(31,12), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
7216 {"lxvrbx", X(31,13), XX1_MASK, POWER10, 0, {XT6, RA0, RB}},
7278 {"lxvrhx", X(31,45), XX1_MASK, POWER10, 0, {XT6, RA0, RB}},
7286 {"lxsiwax", X(31,76), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
7288 {"lxvrwx", X(31,77), XX1_MASK, POWER10, 0, {XT6, RA0, RB}},
7385 {"lxvrdx", X(31,109), XX1_MASK, POWER10, 0, {XT6, RA0, RB}}
[all...] |
| /src/external/gpl3/gdb/dist/opcodes/ |
| ppc-opc.c | 4013 #define P_XX1_MASK (PREFIX_MASK | XX1_MASK)
4520 #define XX1_MASK X (0x3f, 0x3ff)
4522 /* An XX1_MASK with the RB field fixed. */
4523 #define XX1RB_MASK (XX1_MASK | RB_MASK)
7095 {"lxsiwzx", X(31,12), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
7097 {"lxvrbx", X(31,13), XX1_MASK, POWER10, 0, {XT6, RA0, RB}},
7159 {"lxvrhx", X(31,45), XX1_MASK, POWER10, 0, {XT6, RA0, RB}},
7167 {"lxsiwax", X(31,76), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
7169 {"lxvrwx", X(31,77), XX1_MASK, POWER10, 0, {XT6, RA0, RB}},
7266 {"lxvrdx", X(31,109), XX1_MASK, POWER10, 0, {XT6, RA0, RB}}
[all...] |
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| ppc-opc.c | 4013 #define P_XX1_MASK (PREFIX_MASK | XX1_MASK)
4520 #define XX1_MASK X (0x3f, 0x3ff)
4522 /* An XX1_MASK with the RB field fixed. */
4523 #define XX1RB_MASK (XX1_MASK | RB_MASK)
7095 {"lxsiwzx", X(31,12), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
7097 {"lxvrbx", X(31,13), XX1_MASK, POWER10, 0, {XT6, RA0, RB}},
7159 {"lxvrhx", X(31,45), XX1_MASK, POWER10, 0, {XT6, RA0, RB}},
7167 {"lxsiwax", X(31,76), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
7169 {"lxvrwx", X(31,77), XX1_MASK, POWER10, 0, {XT6, RA0, RB}},
7266 {"lxvrdx", X(31,109), XX1_MASK, POWER10, 0, {XT6, RA0, RB}}
[all...] |
