| /src/crypto/external/apache2/openssl/dist/crypto/md4/ |
| md4_dgst.c | 49 unsigned MD32_REG_T XX0, XX1, XX2, XX3, XX4, XX5, XX6, XX7,
|
| /src/crypto/external/apache2/openssl/dist/crypto/md5/ |
| md5_dgst.c | 49 unsigned MD32_REG_T XX0, XX1, XX2, XX3, XX4, XX5, XX6, XX7,
|
| /src/crypto/external/apache2/openssl/dist/crypto/ripemd/ |
| rmd_dgst.c | 49 unsigned MD32_REG_T XX0, XX1, XX2, XX3, XX4, XX5, XX6, XX7,
|
| /src/crypto/external/bsd/openssl/dist/crypto/md4/ |
| md4_dgst.c | 49 unsigned MD32_REG_T XX0, XX1, XX2, XX3, XX4, XX5, XX6, XX7,
|
| /src/crypto/external/bsd/openssl/dist/crypto/md5/ |
| md5_dgst.c | 49 unsigned MD32_REG_T XX0, XX1, XX2, XX3, XX4, XX5, XX6, XX7,
|
| /src/crypto/external/bsd/openssl/dist/crypto/ripemd/ |
| rmd_dgst.c | 49 unsigned MD32_REG_T XX0, XX1, XX2, XX3, XX4, XX5, XX6, XX7,
|
| /src/crypto/external/bsd/openssl.old/dist/crypto/md4/ |
| md4_dgst.c | 43 unsigned MD32_REG_T XX0, XX1, XX2, XX3, XX4, XX5, XX6, XX7,
|
| /src/crypto/external/bsd/openssl.old/dist/crypto/md5/ |
| md5_dgst.c | 43 unsigned MD32_REG_T XX0, XX1, XX2, XX3, XX4, XX5, XX6, XX7,
|
| /src/crypto/external/bsd/openssl.old/dist/crypto/ripemd/ |
| rmd_dgst.c | 43 unsigned MD32_REG_T XX0, XX1, XX2, XX3, XX4, XX5, XX6, XX7,
|
| /src/crypto/external/apache2/openssl/dist/crypto/sha/ |
| sha_local.h | 147 unsigned MD32_REG_T XX0, XX1, XX2, XX3, XX4, XX5, XX6, XX7,
|
| /src/crypto/external/bsd/openssl/dist/crypto/sha/ |
| sha_local.h | 142 unsigned MD32_REG_T XX0, XX1, XX2, XX3, XX4, XX5, XX6, XX7,
|
| /src/crypto/external/bsd/openssl.old/dist/crypto/sha/ |
| sha_local.h | 141 unsigned MD32_REG_T XX0, XX1, XX2, XX3, XX4, XX5, XX6, XX7,
|
| /src/external/apache2/mDNSResponder/dist/mDNSCore/ |
| DNSDigest.c | 1062 unsigned MD32_REG_T XX0, XX1, XX2, XX3, XX4, XX5, XX6, XX7,
|
| /src/external/gpl3/binutils/dist/opcodes/ |
| ppc-opc.c | 2362 /* The XC field in an XX4 form instruction. This is split. */
3957 /* The XC field in an XX4 form instruction. This is split. */
4599 /* An XX4 form instruction. */
4600 #define XX4(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x3) << 4))
4705 /* The mask for an XX4 form instruction. */
4706 #define XX4_MASK XX4 (0x3f, 0x3)
9419 {"xxsel", XX4(60,3), XX4_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, XC6}},
10005 {"xxblendvb", P8RR|XX4(33,0), P_XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6}},
10006 {"xxblendvh", P8RR|XX4(33,1), P_XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6}},
10007 {"xxblendvw", P8RR|XX4(33,2), P_XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6}}
[all...] |
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| ppc-opc.c | 2362 /* The XC field in an XX4 form instruction. This is split. */
3956 /* The XC field in an XX4 form instruction. This is split. */
4589 /* An XX4 form instruction. */
4590 #define XX4(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x3) << 4))
4689 /* The mask for an XX4 form instruction. */
4690 #define XX4_MASK XX4 (0x3f, 0x3)
9354 {"xxsel", XX4(60,3), XX4_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, XC6}},
9940 {"xxblendvb", P8RR|XX4(33,0), P_XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6}},
9941 {"xxblendvh", P8RR|XX4(33,1), P_XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6}},
9942 {"xxblendvw", P8RR|XX4(33,2), P_XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6}}
[all...] |
| /src/external/gpl3/gdb/dist/opcodes/ |
| ppc-opc.c | 2316 /* The XC field in an XX4 form instruction. This is split. */
3878 /* The XC field in an XX4 form instruction. This is split. */
4481 /* An XX4 form instruction. */
4482 #define XX4(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x3) << 4))
4570 /* The mask for an XX4 form instruction. */
4571 #define XX4_MASK XX4 (0x3f, 0x3)
9235 {"xxsel", XX4(60,3), XX4_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, XC6}},
9797 {"xxblendvb", P8RR|XX4(33,0), P_XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6}},
9798 {"xxblendvh", P8RR|XX4(33,1), P_XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6}},
9799 {"xxblendvw", P8RR|XX4(33,2), P_XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6}}
[all...] |
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| ppc-opc.c | 2316 /* The XC field in an XX4 form instruction. This is split. */
3878 /* The XC field in an XX4 form instruction. This is split. */
4481 /* An XX4 form instruction. */
4482 #define XX4(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x3) << 4))
4570 /* The mask for an XX4 form instruction. */
4571 #define XX4_MASK XX4 (0x3f, 0x3)
9235 {"xxsel", XX4(60,3), XX4_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, XC6}},
9786 {"xxblendvb", P8RR|XX4(33,0), P_XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6}},
9787 {"xxblendvh", P8RR|XX4(33,1), P_XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6}},
9788 {"xxblendvw", P8RR|XX4(33,2), P_XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6}}
[all...] |
