| /src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/ |
| InstCombineNegator.cpp | 182 case Instruction::Xor:
405 case Instruction::Xor: {
407 // `xor` is negatible if one of its operands is invertible.
410 Value *Xor = Builder.CreateXor(Ops[0], ConstantExpr::getNot(C));
411 return Builder.CreateAdd(Xor, ConstantInt::get(Xor->getType(), 1),
|
| InstCombineSimplifyDemanded.cpp | 219 case Instruction::Xor: {
230 auto *Xor = Builder.CreateXor(LHS, RHS);
231 return Builder.CreateUnaryIntrinsic(Intrinsic::ctpop, Xor);
245 // These bits cannot contribute to the result of the 'xor'.
289 // are flipping are known to be set, then the xor is just resetting those
290 // bits to zero. We can just knock out bits from the 'and' and the 'xor',
922 case Instruction::Xor: {
|
| InstCombineAndOrXor.cpp | 768 APInt Xor = *C1 ^ *C2;
769 if (Xor.isPowerOf2()) {
776 Value *Or = Builder.CreateOr(X, ConstantInt::get(X->getType(), Xor));
1567 /// Fold {and,or,xor} (cast X), C.
1606 /// Fold {and,or,xor} (cast X), Y.
1647 if (LogicOpc == Instruction::Xor)
1714 // Operand complexity canonicalization guarantees that the 'xor' is Op0.
1743 // This transform could also apply to {or, and, xor}, but there are better
1803 if (Instruction *Xor = foldAndToXor(I, Builder))
1804 return Xor;
[all...] |
| InstCombineCompares.cpp | 1567 /// Fold icmp (xor X, Y), C.
1569 BinaryOperator *Xor,
1571 Value *X = Xor->getOperand(0);
1572 Value *Y = Xor->getOperand(1);
1578 // fold the xor.
1584 // the operation, just stop using the Xor.
1597 if (Xor->hasOneUse()) {
1598 // (icmp u/s (xor X SignMask), C) -> (icmp s/u X, (xor C SignMask))
1604 // (icmp u/s (xor X ~SignMask), C) -> (icmp s/u X, (xor C ~SignMask)
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/Analysis/ |
| IVDescriptors.h | 43 Xor, ///< Bitwise or logical XOR of integers.
59 /// Basic recurrences are defined as the summation, product, OR, AND, XOR, min,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| SILowerControlFlow.cpp | 240 MachineInstr *Xor = nullptr;
242 Xor =
246 setImpSCCDefDead(*Xor, ImpDefSCC.isDead());
276 LIS->InsertMachineInstrInMaps(*Xor);
321 MachineInstr *Xor =
344 LIS->InsertMachineInstrInMaps(*Xor);
|
| SIInstrInfo.cpp | 6224 // invert either source and then perform the XOR. If either source is a
6231 MachineInstr *Xor;
6240 Xor = BuildMI(MBB, MII, DL, get(AMDGPU::S_XOR_B32), NewDest)
6245 Xor = BuildMI(MBB, MII, DL, get(AMDGPU::S_XOR_B32), NewDest)
6249 Xor = BuildMI(MBB, MII, DL, get(AMDGPU::S_XOR_B32), Temp)
6259 Worklist.insert(Xor);
6549 MachineInstr &Xor = *BuildMI(MBB, MII, DL, get(AMDGPU::S_XOR_B64), NewDest)
6555 Worklist.insert(&Xor);
|
| /src/external/apache2/llvm/dist/llvm/bindings/ocaml/llvm/ |
| llvm.ml | 207 | Xor
291 | Xor
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| M68kISelLowering.cpp | 1693 case ISD::XOR: {
1749 case ISD::XOR:
1763 case ISD::XOR:
1764 Opcode = M68kISD::XOR;
1779 case M68kISD::XOR:
1812 case ISD::XOR:
1813 ConvertedOp = M68kISD::XOR;
1951 SDValue Xor = DAG.getNode(ISD::XOR, DL, MVT::i1, Op0, Op1);
1952 return DAG.getSetCC(DL, VT, Xor, DAG.getConstant(0, DL, MVT::i1), CC)
[all...] |
| /src/external/apache2/llvm/dist/llvm/bindings/go/llvm/ |
| ir.go | 160 Xor Opcode = C.LLVMXor
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| TargetLowering.cpp | 518 case ISD::XOR:
527 if (Opcode == ISD::XOR && DemandedBits.isSubsetOf(C))
744 case ISD::XOR: {
1206 // Bitwise-not (xor X, -1) is a special case: we don't usually shrink its
1208 // the xor, then this 'and' can be eliminated by shrinking the mask of
1209 // the xor. For example, for a 32-bit X:
1210 // and (xor (srl X, 31), -1), 1 --> xor (srl X, 31), 1
1213 SDValue Xor = TLO.DAG.getNode(ISD::XOR, dl, VT, Op0.getOperand(0), Op1)
[all...] |
| DAGCombiner.cpp | 1648 case ISD::XOR: return visitXOR(N);
1773 case ISD::XOR:
2314 (TLI.isOperationLegal(ISD::XOR, X.getValueType()) &&
2417 // fold (add (xor a, -1), 1) -> (sub 0, a)
2422 // fold (add (add (xor a, -1), b), 1) -> (sub b, a)
2426 SDValue A, Xor;
2430 Xor = N0.getOperand(0);
2433 Xor = N0.getOperand(1);
2436 if (Xor)
2437 return DAG.getNode(ISD::SUB, DL, VT, A, Xor.getOperand(0))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| LegalizerHelper.cpp | 5711 auto Xor = MIRBuilder.buildXor(S64, LPlusS, S);
5712 auto R = MIRBuilder.buildUITOFP(S32, Xor);
6804 // Implement vector G_SELECT in terms of XOR, AND, OR.
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 410 // Custom lowering hooks are needed for XOR
412 setOperationAction(ISD::XOR, MVT::i32, Custom);
413 setOperationAction(ISD::XOR, MVT::i64, Custom);
880 setTargetDAGCombine(ISD::XOR);
1526 setOperationAction(ISD::XOR, VT, Custom);
1676 case ISD::XOR:
3041 // (xor (overflow_op_bool, 1))
3067 // (xor x, (select_cc a, b, cc, 0, -1) )
3069 // (csel x, (xor x, -1), cc ...)
3104 TVal = DAG.getNode(ISD::XOR, dl, Other.getValueType(), Other
[all...] |
