1 /* $NetBSD: bus_defs.h,v 1.2 2019/09/23 16:17:56 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 1996, 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1996 Charles M. Hannum. All rights reserved. 35 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Christopher G. Demetriou 48 * for the NetBSD Project. 49 * 4. The name of the author may not be used to endorse or promote products 50 * derived from this software without specific prior written permission 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 53 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 54 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 55 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 56 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 57 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 61 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 */ 63 64 #ifndef _LANDISK_BUS_DEFS_H_ 65 #define _LANDISK_BUS_DEFS_H_ 66 67 #include <sys/types.h> 68 69 #ifdef _KERNEL 70 typedef u_long bus_addr_t; 71 typedef u_long bus_size_t; 72 73 #define PRIxBUSADDR "lx" 74 #define PRIxBUSSIZE "lx" 75 #define PRIuBUSSIZE "lu" 76 77 typedef struct _bus_space *bus_space_tag_t; 78 typedef u_long bus_space_handle_t; 79 80 #define PRIxBSH "lx" 81 82 /* 83 * Turn on BUS_SPACE_DEBUG if the global DEBUG option is enabled. 84 */ 85 #if defined(DEBUG) && !defined(BUS_SPACE_DEBUG) 86 #define BUS_SPACE_DEBUG 87 #endif 88 89 #ifdef BUS_SPACE_DEBUG 90 #include <sys/systm.h> /* for printf() prototype */ 91 /* 92 * Macros for checking the aligned-ness of pointers passed to bus 93 * space ops. Strict alignment is required by the Alpha architecture, 94 * and a trap will occur if unaligned access is performed. These 95 * may aid in the debugging of a broken device driver by displaying 96 * useful information about the problem. 97 */ 98 #define __BUS_SPACE_ALIGNED_ADDRESS(p, t) \ 99 ((((u_long)(p)) & (sizeof(t)-1)) == 0) 100 101 #define __BUS_SPACE_ADDRESS_SANITY(p, t, d) \ 102 ({ \ 103 if (__BUS_SPACE_ALIGNED_ADDRESS((p), t) == 0) { \ 104 printf("%s 0x%lx not aligned to %lu bytes %s:%d\n", \ 105 d, (u_long)(p), (u_long)sizeof(t), __FILE__, __LINE__); \ 106 } \ 107 (void) 0; \ 108 }) 109 110 #define BUS_SPACE_ALIGNED_POINTER(p, t) __BUS_SPACE_ALIGNED_ADDRESS(p, t) 111 #else 112 #define __BUS_SPACE_ADDRESS_SANITY(p, t, d) (void) 0 113 #define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t) 114 #endif /* BUS_SPACE_DEBUG */ 115 #endif /* _KERNEL */ 116 117 struct _bus_space { 118 /* cookie */ 119 void *bs_cookie; 120 121 /* mapping/unmapping */ 122 int (*bs_map)(void *, bus_addr_t, bus_size_t, 123 int, bus_space_handle_t *); 124 void (*bs_unmap)(void *, bus_space_handle_t, 125 bus_size_t); 126 int (*bs_subregion)(void *, bus_space_handle_t, 127 bus_size_t, bus_size_t, bus_space_handle_t *); 128 129 /* allocation/deallocation */ 130 int (*bs_alloc)(void *, bus_addr_t, bus_addr_t, 131 bus_size_t, bus_size_t, bus_size_t, int, 132 bus_addr_t *, bus_space_handle_t *); 133 void (*bs_free)(void *, bus_space_handle_t, 134 bus_size_t); 135 136 /* get kernel virtual address */ 137 void * (*bs_vaddr)(void *, bus_space_handle_t); 138 139 /* mmap bus space for user */ 140 paddr_t (*bs_mmap)(void *, bus_addr_t, off_t, int, int); 141 142 /* read (single) */ 143 uint8_t (*bs_r_1)(void *, bus_space_handle_t, 144 bus_size_t); 145 uint16_t (*bs_r_2)(void *, bus_space_handle_t, 146 bus_size_t); 147 uint32_t (*bs_r_4)(void *, bus_space_handle_t, 148 bus_size_t); 149 uint64_t (*bs_r_8)(void *, bus_space_handle_t, 150 bus_size_t); 151 152 /* read multiple */ 153 void (*bs_rm_1)(void *, bus_space_handle_t, 154 bus_size_t, uint8_t *, bus_size_t); 155 void (*bs_rm_2)(void *, bus_space_handle_t, 156 bus_size_t, uint16_t *, bus_size_t); 157 void (*bs_rm_4)(void *, bus_space_handle_t, 158 bus_size_t, uint32_t *, bus_size_t); 159 void (*bs_rm_8)(void *, bus_space_handle_t, 160 bus_size_t, uint64_t *, bus_size_t); 161 162 /* read region */ 163 void (*bs_rr_1)(void *, bus_space_handle_t, 164 bus_size_t, uint8_t *, bus_size_t); 165 void (*bs_rr_2)(void *, bus_space_handle_t, 166 bus_size_t, uint16_t *, bus_size_t); 167 void (*bs_rr_4)(void *, bus_space_handle_t, 168 bus_size_t, uint32_t *, bus_size_t); 169 void (*bs_rr_8)(void *, bus_space_handle_t, 170 bus_size_t, uint64_t *, bus_size_t); 171 172 /* write (single) */ 173 void (*bs_w_1)(void *, bus_space_handle_t, 174 bus_size_t, uint8_t); 175 void (*bs_w_2)(void *, bus_space_handle_t, 176 bus_size_t, uint16_t); 177 void (*bs_w_4)(void *, bus_space_handle_t, 178 bus_size_t, uint32_t); 179 void (*bs_w_8)(void *, bus_space_handle_t, 180 bus_size_t, uint64_t); 181 182 /* write multiple */ 183 void (*bs_wm_1)(void *, bus_space_handle_t, 184 bus_size_t, const uint8_t *, bus_size_t); 185 void (*bs_wm_2)(void *, bus_space_handle_t, 186 bus_size_t, const uint16_t *, bus_size_t); 187 void (*bs_wm_4)(void *, bus_space_handle_t, 188 bus_size_t, const uint32_t *, bus_size_t); 189 void (*bs_wm_8)(void *, bus_space_handle_t, 190 bus_size_t, const uint64_t *, bus_size_t); 191 192 /* write region */ 193 void (*bs_wr_1)(void *, bus_space_handle_t, 194 bus_size_t, const uint8_t *, bus_size_t); 195 void (*bs_wr_2)(void *, bus_space_handle_t, 196 bus_size_t, const uint16_t *, bus_size_t); 197 void (*bs_wr_4)(void *, bus_space_handle_t, 198 bus_size_t, const uint32_t *, bus_size_t); 199 void (*bs_wr_8)(void *, bus_space_handle_t, 200 bus_size_t, const uint64_t *, bus_size_t); 201 202 /* set multiple */ 203 void (*bs_sm_1)(void *, bus_space_handle_t, 204 bus_size_t, uint8_t, bus_size_t); 205 void (*bs_sm_2)(void *, bus_space_handle_t, 206 bus_size_t, uint16_t, bus_size_t); 207 void (*bs_sm_4)(void *, bus_space_handle_t, 208 bus_size_t, uint32_t, bus_size_t); 209 void (*bs_sm_8)(void *, bus_space_handle_t, 210 bus_size_t, uint64_t, bus_size_t); 211 212 /* set region */ 213 void (*bs_sr_1)(void *, bus_space_handle_t, 214 bus_size_t, uint8_t, bus_size_t); 215 void (*bs_sr_2)(void *, bus_space_handle_t, 216 bus_size_t, uint16_t, bus_size_t); 217 void (*bs_sr_4)(void *, bus_space_handle_t, 218 bus_size_t, uint32_t, bus_size_t); 219 void (*bs_sr_8)(void *, bus_space_handle_t, 220 bus_size_t, uint64_t, bus_size_t); 221 222 /* copy */ 223 void (*bs_c_1)(void *, bus_space_handle_t, bus_size_t, 224 bus_space_handle_t, bus_size_t, bus_size_t); 225 void (*bs_c_2)(void *, bus_space_handle_t, bus_size_t, 226 bus_space_handle_t, bus_size_t, bus_size_t); 227 void (*bs_c_4)(void *, bus_space_handle_t, bus_size_t, 228 bus_space_handle_t, bus_size_t, bus_size_t); 229 void (*bs_c_8)(void *, bus_space_handle_t, bus_size_t, 230 bus_space_handle_t, bus_size_t, bus_size_t); 231 }; 232 233 #define BUS_SPACE_MAP_CACHEABLE 0x01 234 #define BUS_SPACE_MAP_LINEAR 0x02 235 #define BUS_SPACE_MAP_PREFETCHABLE 0x04 236 237 #define __BUS_SPACE_HAS_STREAM_METHODS 238 239 #define BUS_SPACE_BARRIER_READ 0x01 240 #define BUS_SPACE_BARRIER_WRITE 0x02 241 242 /* 243 * Flags used in various bus DMA methods. 244 */ 245 #define BUS_DMA_WAITOK 0x000 /* safe to sleep (pseudo-flag) */ 246 #define BUS_DMA_NOWAIT 0x001 /* not safe to sleep */ 247 #define BUS_DMA_ALLOCNOW 0x002 /* perform resource allocation now */ 248 #define BUS_DMA_COHERENT 0x004 /* map memory to not require sync */ 249 #define BUS_DMA_STREAMING 0x008 /* hint: sequential, unidirectional */ 250 #define BUS_DMA_BUS1 0x010 /* placeholders for bus functions... */ 251 #define BUS_DMA_BUS2 0x020 252 #define BUS_DMA_BUS3 0x040 253 #define BUS_DMA_BUS4 0x080 254 #define BUS_DMA_READ 0x100 /* mapping is device -> memory only */ 255 #define BUS_DMA_WRITE 0x200 /* mapping is memory -> device only */ 256 #define BUS_DMA_NOCACHE 0x400 /* hint: map non-cached memory */ 257 258 /* Forwards needed by prototypes below. */ 259 struct mbuf; 260 struct uio; 261 262 /* 263 * Operations performed by bus_dmamap_sync(). 264 */ 265 #define BUS_DMASYNC_PREREAD 0x01 266 #define BUS_DMASYNC_POSTREAD 0x02 267 #define BUS_DMASYNC_PREWRITE 0x04 268 #define BUS_DMASYNC_POSTWRITE 0x08 269 270 typedef struct _bus_dma_tag *bus_dma_tag_t; 271 typedef struct _bus_dmamap *bus_dmamap_t; 272 273 #define BUS_DMA_TAG_VALID(t) ((t) != (bus_dma_tag_t)0) 274 275 /* 276 * bus_dma_segment_t 277 * 278 * Describes a single contiguous DMA transaction. Values 279 * are suitable for programming into DMA registers. 280 */ 281 struct _bus_dma_segment { 282 bus_addr_t ds_addr; /* DMA address */ 283 bus_size_t ds_len; /* length of transfer */ 284 285 /* private section */ 286 bus_addr_t _ds_vaddr; /* virtual address */ 287 }; 288 typedef struct _bus_dma_segment bus_dma_segment_t; 289 290 /* 291 * bus_dma_tag_t 292 * 293 * A machine-dependent opaque type describing the implementation of 294 * DMA for a given bus. 295 */ 296 297 struct _bus_dma_tag { 298 void *_cookie; /* cookie used in the guts */ 299 300 /* 301 * DMA mapping methods. 302 */ 303 int (*_dmamap_create)(bus_dma_tag_t, bus_size_t, int, 304 bus_size_t, bus_size_t, int, bus_dmamap_t *); 305 void (*_dmamap_destroy)(bus_dma_tag_t, bus_dmamap_t); 306 int (*_dmamap_load)(bus_dma_tag_t, bus_dmamap_t, void *, 307 bus_size_t, struct proc *, int); 308 int (*_dmamap_load_mbuf)(bus_dma_tag_t, bus_dmamap_t, 309 struct mbuf *, int); 310 int (*_dmamap_load_uio)(bus_dma_tag_t, bus_dmamap_t, 311 struct uio *, int); 312 int (*_dmamap_load_raw)(bus_dma_tag_t, bus_dmamap_t, 313 bus_dma_segment_t *, int, bus_size_t, int); 314 void (*_dmamap_unload)(bus_dma_tag_t, bus_dmamap_t); 315 void (*_dmamap_sync)(bus_dma_tag_t, bus_dmamap_t, 316 bus_addr_t, bus_size_t, int); 317 318 /* 319 * DMA memory utility functions. 320 */ 321 int (*_dmamem_alloc)(bus_dma_tag_t, bus_size_t, bus_size_t, 322 bus_size_t, bus_dma_segment_t *, int, int *, int); 323 void (*_dmamem_free)(bus_dma_tag_t, 324 bus_dma_segment_t *, int); 325 int (*_dmamem_map)(bus_dma_tag_t, bus_dma_segment_t *, 326 int, size_t, void **, int); 327 void (*_dmamem_unmap)(bus_dma_tag_t, void *, size_t); 328 paddr_t (*_dmamem_mmap)(bus_dma_tag_t, bus_dma_segment_t *, 329 int, off_t, int, int); 330 }; 331 332 /* 333 * bus_dmamap_t 334 * 335 * Describes a DMA mapping. 336 */ 337 struct _bus_dmamap { 338 /* 339 * PRIVATE MEMBERS: not for use my machine-independent code. 340 */ 341 bus_size_t _dm_size; /* largest DMA transfer mappable */ 342 int _dm_segcnt; /* number of segs this map can map */ 343 bus_size_t _dm_maxsegsz; /* largest possible segment */ 344 bus_size_t _dm_boundary; /* don't cross this */ 345 int _dm_flags; /* misc. flags */ 346 347 void *_dm_cookie; /* cookie for bus-specific functions */ 348 349 /* 350 * PUBLIC MEMBERS: these are used by machine-independent code. 351 */ 352 bus_size_t dm_mapsize; /* size of the mapping */ 353 int dm_nsegs; /* # valid segments in mapping */ 354 bus_dma_segment_t dm_segs[1]; /* segments; variable length */ 355 }; 356 357 #endif /* _LANDISK_BUS_DEFS_H_ */ 358
Indexes created Wed Oct 22 13:09:56 GMT 2025