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      1 /*	$NetBSD: rambo.h,v 1.9 2025/04/26 04:58:48 tsutsui Exp $	*/
      2 /*-
      3  * Copyright (c) 2000 The NetBSD Foundation, Inc.
      4  * All rights reserved.
      5  *
      6  * This code is derived from software contributed to The NetBSD Foundation
      7  * by Wayne Knowles
      8  *
      9  * Redistribution and use in source and binary forms, with or without
     10  * modification, are permitted provided that the following conditions
     11  * are met:
     12  * 1. Redistributions of source code must retain the above copyright
     13  *    notice, this list of conditions and the following disclaimer.
     14  * 2. Redistributions in binary form must reproduce the above copyright
     15  *    notice, this list of conditions and the following disclaimer in the
     16  *    documentation and/or other materials provided with the distribution.
     17  *
     18  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     19  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     20  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     21  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     22  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     28  * POSSIBILITY OF SUCH DAMAGE.
     29  */
     30 
     31 /*
     32  *  RAMBO DMA controller/timer asic used on the Mips 3230 (Pizazz)
     33  */
     34 
     35 #ifndef _MACHINE_RAMBO_H
     36 #define _MACHINE_RAMBO_H 1
     37 
     38 /* Register layout of a single RAMBO DMA channel */
     39 struct	rambo_ch {
     40 	u_long	dma_laddr;	/* DMA load address reg	32b R/W */
     41 	u_long  __0[63];
     42 	u_long  dma_diag;	/* DMA Diagnostic reg	32b R   */
     43 	u_long	__1[63];
     44 	u_short __2;
     45 	u_short	dma_fifo;	/* FIFO Buffer 16 bits	16b R/W */
     46 	u_long	__3[63];
     47 	u_long	dma_mode;	/* DMA Mode Register	32b R/W */
     48 	u_long	__4[63];
     49 	u_short __5;
     50 	u_short	dma_block;	/* DMA Block Count	16b R/W */
     51 	u_long	__6[63];
     52 	u_long	dma_caddr;	/* DMA Current Address	32b R   */
     53 	u_long	__7[63];
     54 };
     55 
     56 #define RAMBO_LADDR	0x0000
     57 #define RAMBO_DIAG	0x0100
     58 #define	RAMBO_FIFO	0x0202
     59 #define	RAMBO_MODE	0x0300
     60 #define	RAMBO_BLKCNT	0x0402
     61 #define	RAMBO_CADDR	0x0500
     62 
     63 /* DMA mode register (dma_mode) (R/W) */
     64 
     65 #define	RB_CLRFIFO	0x80000000 /* Clear DMA FIFO */
     66 #define	RB_DMA_ENABLE	0x40000000 /* Enable DMA Transfer */
     67 #define	RB_AUTORELOAD	0x20000000 /* Auto restart DMA */
     68 #define	RB_INT_ENABLE  	0X10000000 /* INterrupt on terminal count */
     69 
     70 #define RB_DMA_WR	0x08000000 /* Xfer into memory */
     71 #define RB_DMA_RD	0x00000000 /* Xfer from memory */
     72 
     73 #define	RB_CLRERROR	0x04000000 /* Clear DMA Error register */
     74 
     75 /* status bits of mode register (R) */
     76 
     77 #define	RB_FIFO_FULL	0x00000800 /* FIFO Buffer is full */
     78 #define	RB_FIFO_EMPTY	0x00000400 /* FIFO Buffer is empty */
     79 #define	RB_DMA_ERROR	0x00000200 /* Error has occurred */
     80 #define	RB_INTR_PEND	0x00000100 /* Interrupt is pending */
     81 
     82 #define	RB_CNT_MASK	0x000000ff /* half-words left in FIFO */
     83 
     84 /* Offsets to other registers in the RAMBO asic */
     85 #define	RB_TCOUNT	0x0c00
     86 #define	RB_TBREAK	0x0d00
     87 #define RB_ERRREG	0x0e00
     88 #define	RB_CTLREG	0x0f00
     89 
     90 /* Hardware Register */
     91 
     92 #define	RB_BUZZ0	0x00	/* 1524 Hz */
     93 #define	RB_BUZZ1	0x10	/* 762 Hz */
     94 #define	RB_BUZZ2	0x20	/* 381 Hz */
     95 #define	RB_BUZZ3	0x30	/* 190 Hz */
     96 #define	RB_BUZZOFF	0x08	/* Buzzer Enable - Active Low  */
     97 #define	RB_PARITY_EN	0x04	/* Enable Parity - Active High */
     98 #define	RB_CLR_PAR	0x02	/* Clear SysParErr - Active High */
     99 #define	RB_CLR_IOERR	0x01	/* Clear ErrIntB - Active Low */
    100 
    101 #define	RB_BLK_SHIFT	6
    102 #define	RB_BLK_CNT	32	/* half-word byte count */
    103 #define	RB_BLK_MASK	0x3f	/* Alignment mask */
    104 #define	RB_BLK_SIZE	64	/* Bytes in a DMA Block */
    105 
    106 /* DMA cannot cross 512k boundary (2^19 == 512k) */
    107 #define RB_BSIZE	19
    108 #define RB_BMASK	((1<<RB_BSIZE)-1)
    109 #define	RB_BOUNDRY	(1<<RB_BSIZE)
    110 
    111 /* Rambo cycle counter is fed by 25MHz clock then divided by 4 */
    112 #define	RB_FREQUENCY		6250000L
    113 #define	HZ_TO_TICKS(hz)		(RB_FREQUENCY/(hz))
    114 #endif
    115