1 /* $NetBSD: a9ptmr.c,v 1.3 2022/11/05 17:30:20 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2019 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Nick Hudson 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: a9ptmr.c,v 1.3 2022/11/05 17:30:20 jmcneill Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/cpu.h> 38 #include <sys/device.h> 39 #include <sys/kernel.h> 40 #include <sys/xcall.h> 41 42 #include <prop/proplib.h> 43 44 #include <arm/cortex/a9tmr_reg.h> 45 #include <arm/cortex/a9ptmr_var.h> 46 47 #include <arm/cortex/mpcore_var.h> 48 49 static struct a9ptmr_softc *a9ptmr_sc; 50 51 static int a9ptmr_match(device_t, cfdata_t, void *); 52 static void a9ptmr_attach(device_t, device_t, void *); 53 54 struct a9ptmr_softc { 55 device_t sc_dev; 56 bus_space_tag_t sc_memt; 57 bus_space_handle_t sc_memh; 58 59 uint32_t sc_ctl; 60 uint32_t sc_freq; 61 uint32_t sc_load; 62 63 uint32_t sc_prescaler; 64 }; 65 66 67 CFATTACH_DECL_NEW(arma9ptmr, sizeof(struct a9ptmr_softc), 68 a9ptmr_match, a9ptmr_attach, NULL, NULL); 69 70 static bool attached; 71 72 static inline uint32_t 73 a9ptmr_read(struct a9ptmr_softc *sc, bus_size_t o) 74 { 75 return bus_space_read_4(sc->sc_memt, sc->sc_memh, o); 76 } 77 78 static inline void 79 a9ptmr_write(struct a9ptmr_softc *sc, bus_size_t o, uint32_t v) 80 { 81 bus_space_write_4(sc->sc_memt, sc->sc_memh, o, v); 82 } 83 84 /* ARGSUSED */ 85 static int 86 a9ptmr_match(device_t parent, cfdata_t cf, void *aux) 87 { 88 struct mpcore_attach_args * const mpcaa = aux; 89 90 if (attached) 91 return 0; 92 93 if (!CPU_ID_CORTEX_A9_P(curcpu()->ci_arm_cpuid) && 94 !CPU_ID_CORTEX_A5_P(curcpu()->ci_arm_cpuid)) 95 return 0; 96 97 if (strcmp(mpcaa->mpcaa_name, cf->cf_name) != 0) 98 return 0; 99 100 #if 0 101 /* 102 * This isn't present on UP A9s (since CBAR isn't present). 103 */ 104 uint32_t mpidr = armreg_mpidr_read(); 105 if (mpidr == 0 || (mpidr & MPIDR_U)) 106 return 0; 107 #endif 108 109 return 1; 110 } 111 112 113 static void 114 a9ptmr_attach(device_t parent, device_t self, void *aux) 115 { 116 struct a9ptmr_softc * const sc = device_private(self); 117 struct mpcore_attach_args * const mpcaa = aux; 118 prop_dictionary_t dict = device_properties(self); 119 char freqbuf[sizeof("XXX SHz")]; 120 const char *cpu_type; 121 122 123 sc->sc_dev = self; 124 sc->sc_memt = mpcaa->mpcaa_memt; 125 126 bus_space_subregion(sc->sc_memt, mpcaa->mpcaa_memh, 127 mpcaa->mpcaa_off1, TMR_PRIVATE_SIZE, &sc->sc_memh); 128 129 /* 130 * This runs at the ARM PERIPHCLOCK. 131 * The MD code should have setup our frequency for us. 132 */ 133 if (!prop_dictionary_get_uint32(dict, "frequency", &sc->sc_freq)) { 134 dict = device_properties(parent); 135 prop_dictionary_get_uint32(dict, "frequency", &sc->sc_freq); 136 } 137 138 humanize_number(freqbuf, sizeof(freqbuf), sc->sc_freq, "Hz", 1000); 139 140 a9ptmr_sc = sc; 141 sc->sc_dev = self; 142 sc->sc_memt = mpcaa->mpcaa_memt; 143 sc->sc_memh = mpcaa->mpcaa_memh; 144 145 sc->sc_ctl = a9ptmr_read(sc, TMR_CTL); 146 147 sc->sc_prescaler = 1; 148 #if 0 149 /* 150 * Let's hope the timer frequency isn't prime. 151 */ 152 for (size_t div = 256; div >= 2; div--) { 153 if (sc->sc_freq % div == 0) { 154 sc->sc_prescaler = div; 155 break; 156 } 157 } 158 sc->sc_freq /= sc->sc_prescaler; 159 #endif 160 161 aprint_debug(": freq %d prescaler %d", sc->sc_freq, 162 sc->sc_prescaler); 163 sc->sc_ctl = TMR_CTL_INT_ENABLE | TMR_CTL_AUTO_RELOAD | TMR_CTL_ENABLE; 164 sc->sc_ctl |= __SHIFTIN(sc->sc_prescaler - 1, TMR_CTL_PRESCALER); 165 166 sc->sc_load = (sc->sc_freq / hz) - 1; 167 168 aprint_debug(": load %d ", sc->sc_load); 169 170 a9ptmr_init_cpu_clock(curcpu()); 171 172 aprint_naive("\n"); 173 if (CPU_ID_CORTEX_A5_P(curcpu()->ci_arm_cpuid)) { 174 cpu_type = "A5"; 175 } else { 176 cpu_type = "A9"; 177 } 178 aprint_normal(": %s Private Timer (%s)\n", cpu_type, freqbuf); 179 180 attached = true; 181 } 182 183 184 185 void 186 a9ptmr_delay(unsigned int n) 187 { 188 struct a9ptmr_softc * const sc = a9ptmr_sc; 189 190 KASSERT(sc != NULL); 191 192 uint32_t freq = sc->sc_freq ? sc->sc_freq : 193 curcpu()->ci_data.cpu_cc_freq / 2; 194 KASSERT(freq != 0); 195 196 const uint64_t counts_per_usec = freq / 1000000; 197 uint32_t delta, usecs, last, curr; 198 199 KASSERT(sc != NULL); 200 201 last = a9ptmr_read(sc, TMR_CTR); 202 203 delta = usecs = 0; 204 while (n > usecs) { 205 curr = a9ptmr_read(sc, TMR_CTR); 206 207 /* Check to see if the timer has reloaded. */ 208 if (curr > last) 209 delta += (sc->sc_load - curr) + last; 210 else 211 delta += last - curr; 212 213 last = curr; 214 215 if (delta >= counts_per_usec) { 216 usecs += delta / counts_per_usec; 217 delta %= counts_per_usec; 218 } 219 } 220 } 221 222 223 void 224 a9ptmr_cpu_initclocks(void) 225 { 226 struct a9ptmr_softc * const sc __diagused = a9ptmr_sc; 227 228 KASSERT(sc->sc_dev != NULL); 229 KASSERT(sc->sc_freq != 0); 230 231 } 232 233 void 234 a9ptmr_init_cpu_clock(struct cpu_info *ci) 235 { 236 struct a9ptmr_softc * const sc = a9ptmr_sc; 237 238 /* Disable Private timer and acknowledge any event */ 239 a9ptmr_write(sc, TMR_CTL, 0); 240 a9ptmr_write(sc, TMR_INT, TMR_INT_EVENT); 241 242 /* 243 * Provide the auto load value for the decrementing counter and 244 * start it. 245 */ 246 a9ptmr_write(sc, TMR_LOAD, sc->sc_load); 247 a9ptmr_write(sc, TMR_CTL, sc->sc_ctl); 248 249 } 250 251 252 253 /* 254 * a9ptmr_intr: 255 * 256 * Handle the hardclock interrupt. 257 */ 258 int 259 a9ptmr_intr(void *arg) 260 { 261 struct clockframe * const cf = arg; 262 struct a9ptmr_softc * const sc = a9ptmr_sc; 263 264 a9ptmr_write(sc, TMR_INT, TMR_INT_EVENT); 265 hardclock(cf); 266 267 return 1; 268 } 269 270 static void 271 a9ptmr_update_freq_cb(void *arg1, void *arg2) 272 { 273 a9ptmr_init_cpu_clock(curcpu()); 274 } 275 276 void 277 a9ptmr_update_freq(uint32_t freq) 278 { 279 struct a9ptmr_softc * const sc = a9ptmr_sc; 280 uint64_t xc; 281 282 KASSERT(sc->sc_dev != NULL); 283 KASSERT(freq != 0); 284 285 sc->sc_freq = freq; 286 sc->sc_load = (sc->sc_freq / hz) - 1; 287 288 xc = xc_broadcast(0, a9ptmr_update_freq_cb, NULL, NULL); 289 xc_wait(xc); 290 } 291
Indexes created Mon Sep 22 13:09:51 GMT 2025