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    Searched defs:allowed_sclk_vddc_table (Results 1 - 2 of 2) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
amdgpu_smu7_hwmgr.c 2465 struct phm_clock_voltage_dependency_table *allowed_sclk_vddc_table = hwmgr->dyn_state.vddc_dependency_on_sclk; local in function:smu7_set_private_data_based_on_pptable_v0
2469 PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table != NULL,
2472 PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table->count >= 1,
2483 data->min_vddc_in_pptable = (uint16_t)allowed_sclk_vddc_table->entries[0].v;
2484 data->max_vddc_in_pptable = (uint16_t)allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
2487 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
2491 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_ci_dpm.c 3450 struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table = local in function:ci_setup_default_dpm_tables
3458 if (allowed_sclk_vddc_table == NULL)
3460 if (allowed_sclk_vddc_table->count < 1)
3486 for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3489 allowed_sclk_vddc_table->entries[i].clk)) {
3491 allowed_sclk_vddc_table->entries[i].clk;
3511 for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3513 allowed_sclk_vddc_table->entries[i].v;
3518 pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count;
4926 struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table local in function:ci_set_private_data_variables_based_on_pptable
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