1 /* $NetBSD: amdgpu_atom.c,v 1.4 2021/12/18 23:44:58 riastradh Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Author: Stanislaw Skowronek 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: amdgpu_atom.c,v 1.4 2021/12/18 23:44:58 riastradh Exp $"); 29 30 #include <linux/module.h> 31 #include <linux/sched.h> 32 #include <linux/slab.h> 33 #include <asm/unaligned.h> 34 35 #include <drm/drm_util.h> 36 37 #define ATOM_DEBUG 38 39 #include "atom.h" 40 #include "atom-names.h" 41 #include "atom-bits.h" 42 #include "amdgpu.h" 43 44 #define ATOM_COND_ABOVE 0 45 #define ATOM_COND_ABOVEOREQUAL 1 46 #define ATOM_COND_ALWAYS 2 47 #define ATOM_COND_BELOW 3 48 #define ATOM_COND_BELOWOREQUAL 4 49 #define ATOM_COND_EQUAL 5 50 #define ATOM_COND_NOTEQUAL 6 51 52 #define ATOM_PORT_ATI 0 53 #define ATOM_PORT_PCI 1 54 #define ATOM_PORT_SYSIO 2 55 56 #define ATOM_UNIT_MICROSEC 0 57 #define ATOM_UNIT_MILLISEC 1 58 59 #define PLL_INDEX 2 60 #define PLL_DATA 3 61 62 typedef struct { 63 struct atom_context *ctx; 64 uint32_t *ps, *ws; 65 int ps_shift; 66 uint16_t start; 67 unsigned last_jump; 68 unsigned long last_jump_jiffies; 69 bool abort; 70 } atom_exec_context; 71 72 int amdgpu_atom_debug = 0; 73 static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params); 74 int amdgpu_atom_execute_table(struct atom_context *ctx, int index, uint32_t * params); 75 76 static uint32_t atom_arg_mask[8] = 77 { 0xFFFFFFFF, 0xFFFF, 0xFFFF00, 0xFFFF0000, 0xFF, 0xFF00, 0xFF0000, 78 0xFF000000 }; 79 static int atom_arg_shift[8] = { 0, 0, 8, 16, 0, 8, 16, 24 }; 80 81 static int atom_dst_to_src[8][4] = { 82 /* translate destination alignment field to the source alignment encoding */ 83 {0, 0, 0, 0}, 84 {1, 2, 3, 0}, 85 {1, 2, 3, 0}, 86 {1, 2, 3, 0}, 87 {4, 5, 6, 7}, 88 {4, 5, 6, 7}, 89 {4, 5, 6, 7}, 90 {4, 5, 6, 7}, 91 }; 92 static int atom_def_dst[8] = { 0, 0, 1, 2, 0, 1, 2, 3 }; 93 94 static int debug_depth = 0; 95 #undef DEBUG /* XXX NetBSD kludge */ 96 #ifdef ATOM_DEBUG 97 static void debug_print_spaces(int n) 98 { 99 while (n--) 100 printk(" "); 101 } 102 103 #define DEBUG(...) do if (amdgpu_atom_debug) { printk(KERN_DEBUG __VA_ARGS__); } while (0) 104 #define SDEBUG(...) do if (amdgpu_atom_debug) { printk(KERN_DEBUG); debug_print_spaces(debug_depth); printk(__VA_ARGS__); } while (0) 105 #else 106 #define DEBUG(...) do { } while (0) 107 #define SDEBUG(...) do { } while (0) 108 #endif 109 110 static uint32_t atom_iio_execute(struct atom_context *ctx, int base, 111 uint32_t index, uint32_t data) 112 { 113 uint32_t temp = 0xCDCDCDCD; 114 115 while (1) 116 switch (CU8(base)) { 117 case ATOM_IIO_NOP: 118 base++; 119 break; 120 case ATOM_IIO_READ: 121 temp = ctx->card->ioreg_read(ctx->card, CU16(base + 1)); 122 base += 3; 123 break; 124 case ATOM_IIO_WRITE: 125 ctx->card->ioreg_write(ctx->card, CU16(base + 1), temp); 126 base += 3; 127 break; 128 case ATOM_IIO_CLEAR: 129 temp &= 130 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << 131 CU8(base + 2)); 132 base += 3; 133 break; 134 case ATOM_IIO_SET: 135 temp |= 136 (0xFFFFFFFF >> (32 - CU8(base + 1))) << CU8(base + 137 2); 138 base += 3; 139 break; 140 case ATOM_IIO_MOVE_INDEX: 141 temp &= 142 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << 143 CU8(base + 3)); 144 temp |= 145 ((index >> CU8(base + 2)) & 146 (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base + 147 3); 148 base += 4; 149 break; 150 case ATOM_IIO_MOVE_DATA: 151 temp &= 152 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << 153 CU8(base + 3)); 154 temp |= 155 ((data >> CU8(base + 2)) & 156 (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base + 157 3); 158 base += 4; 159 break; 160 case ATOM_IIO_MOVE_ATTR: 161 temp &= 162 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << 163 CU8(base + 3)); 164 temp |= 165 ((ctx-> 166 io_attr >> CU8(base + 2)) & (0xFFFFFFFF >> (32 - 167 CU8 168 (base 169 + 170 1)))) 171 << CU8(base + 3); 172 base += 4; 173 break; 174 case ATOM_IIO_END: 175 return temp; 176 default: 177 pr_info("Unknown IIO opcode\n"); 178 return 0; 179 } 180 } 181 182 static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr, 183 int *ptr, uint32_t *saved, int print) 184 { 185 uint32_t idx, val = 0xCDCDCDCD, align, arg; 186 struct atom_context *gctx = ctx->ctx; 187 arg = attr & 7; 188 align = (attr >> 3) & 7; 189 switch (arg) { 190 case ATOM_ARG_REG: 191 idx = U16(*ptr); 192 (*ptr) += 2; 193 if (print) 194 DEBUG("REG[0x%04X]", idx); 195 idx += gctx->reg_block; 196 switch (gctx->io_mode) { 197 case ATOM_IO_MM: 198 val = gctx->card->reg_read(gctx->card, idx); 199 break; 200 case ATOM_IO_PCI: 201 pr_info("PCI registers are not implemented\n"); 202 return 0; 203 case ATOM_IO_SYSIO: 204 pr_info("SYSIO registers are not implemented\n"); 205 return 0; 206 default: 207 if (!(gctx->io_mode & 0x80)) { 208 pr_info("Bad IO mode\n"); 209 return 0; 210 } 211 if (!gctx->iio[gctx->io_mode & 0x7F]) { 212 pr_info("Undefined indirect IO read method %d\n", 213 gctx->io_mode & 0x7F); 214 return 0; 215 } 216 val = 217 atom_iio_execute(gctx, 218 gctx->iio[gctx->io_mode & 0x7F], 219 idx, 0); 220 } 221 break; 222 case ATOM_ARG_PS: 223 idx = U8(*ptr); 224 (*ptr)++; 225 /* get_unaligned_le32 avoids unaligned accesses from atombios 226 * tables, noticed on a DEC Alpha. */ 227 val = get_unaligned_le32((u32 *)&ctx->ps[idx]); 228 if (print) 229 DEBUG("PS[0x%02X,0x%04X]", idx, val); 230 break; 231 case ATOM_ARG_WS: 232 idx = U8(*ptr); 233 (*ptr)++; 234 if (print) 235 DEBUG("WS[0x%02X]", idx); 236 switch (idx) { 237 case ATOM_WS_QUOTIENT: 238 val = gctx->divmul[0]; 239 break; 240 case ATOM_WS_REMAINDER: 241 val = gctx->divmul[1]; 242 break; 243 case ATOM_WS_DATAPTR: 244 val = gctx->data_block; 245 break; 246 case ATOM_WS_SHIFT: 247 val = gctx->shift; 248 break; 249 case ATOM_WS_OR_MASK: 250 val = 1 << gctx->shift; 251 break; 252 case ATOM_WS_AND_MASK: 253 val = ~(1 << gctx->shift); 254 break; 255 case ATOM_WS_FB_WINDOW: 256 val = gctx->fb_base; 257 break; 258 case ATOM_WS_ATTRIBUTES: 259 val = gctx->io_attr; 260 break; 261 case ATOM_WS_REGPTR: 262 val = gctx->reg_block; 263 break; 264 default: 265 val = ctx->ws[idx]; 266 } 267 break; 268 case ATOM_ARG_ID: 269 idx = U16(*ptr); 270 (*ptr) += 2; 271 if (print) { 272 if (gctx->data_block) 273 DEBUG("ID[0x%04X+%04X]", idx, gctx->data_block); 274 else 275 DEBUG("ID[0x%04X]", idx); 276 } 277 val = U32(idx + gctx->data_block); 278 break; 279 case ATOM_ARG_FB: 280 idx = U8(*ptr); 281 (*ptr)++; 282 if ((gctx->fb_base + (idx * 4)) > gctx->scratch_size_bytes) { 283 DRM_ERROR("ATOM: fb read beyond scratch region: %d vs. %d\n", 284 gctx->fb_base + (idx * 4), gctx->scratch_size_bytes); 285 val = 0; 286 } else 287 val = gctx->scratch[(gctx->fb_base / 4) + idx]; 288 if (print) 289 DEBUG("FB[0x%02X]", idx); 290 break; 291 case ATOM_ARG_IMM: 292 switch (align) { 293 case ATOM_SRC_DWORD: 294 val = U32(*ptr); 295 (*ptr) += 4; 296 if (print) 297 DEBUG("IMM 0x%08X\n", val); 298 return val; 299 case ATOM_SRC_WORD0: 300 case ATOM_SRC_WORD8: 301 case ATOM_SRC_WORD16: 302 val = U16(*ptr); 303 (*ptr) += 2; 304 if (print) 305 DEBUG("IMM 0x%04X\n", val); 306 return val; 307 case ATOM_SRC_BYTE0: 308 case ATOM_SRC_BYTE8: 309 case ATOM_SRC_BYTE16: 310 case ATOM_SRC_BYTE24: 311 val = U8(*ptr); 312 (*ptr)++; 313 if (print) 314 DEBUG("IMM 0x%02X\n", val); 315 return val; 316 } 317 return 0; 318 case ATOM_ARG_PLL: 319 idx = U8(*ptr); 320 (*ptr)++; 321 if (print) 322 DEBUG("PLL[0x%02X]", idx); 323 val = gctx->card->pll_read(gctx->card, idx); 324 break; 325 case ATOM_ARG_MC: 326 idx = U8(*ptr); 327 (*ptr)++; 328 if (print) 329 DEBUG("MC[0x%02X]", idx); 330 val = gctx->card->mc_read(gctx->card, idx); 331 break; 332 } 333 if (saved) 334 *saved = val; 335 val &= atom_arg_mask[align]; 336 val >>= atom_arg_shift[align]; 337 if (print) 338 switch (align) { 339 case ATOM_SRC_DWORD: 340 DEBUG(".[31:0] -> 0x%08X\n", val); 341 break; 342 case ATOM_SRC_WORD0: 343 DEBUG(".[15:0] -> 0x%04X\n", val); 344 break; 345 case ATOM_SRC_WORD8: 346 DEBUG(".[23:8] -> 0x%04X\n", val); 347 break; 348 case ATOM_SRC_WORD16: 349 DEBUG(".[31:16] -> 0x%04X\n", val); 350 break; 351 case ATOM_SRC_BYTE0: 352 DEBUG(".[7:0] -> 0x%02X\n", val); 353 break; 354 case ATOM_SRC_BYTE8: 355 DEBUG(".[15:8] -> 0x%02X\n", val); 356 break; 357 case ATOM_SRC_BYTE16: 358 DEBUG(".[23:16] -> 0x%02X\n", val); 359 break; 360 case ATOM_SRC_BYTE24: 361 DEBUG(".[31:24] -> 0x%02X\n", val); 362 break; 363 } 364 return val; 365 } 366 367 static void atom_skip_src_int(atom_exec_context *ctx, uint8_t attr, int *ptr) 368 { 369 uint32_t align = (attr >> 3) & 7, arg = attr & 7; 370 switch (arg) { 371 case ATOM_ARG_REG: 372 case ATOM_ARG_ID: 373 (*ptr) += 2; 374 break; 375 case ATOM_ARG_PLL: 376 case ATOM_ARG_MC: 377 case ATOM_ARG_PS: 378 case ATOM_ARG_WS: 379 case ATOM_ARG_FB: 380 (*ptr)++; 381 break; 382 case ATOM_ARG_IMM: 383 switch (align) { 384 case ATOM_SRC_DWORD: 385 (*ptr) += 4; 386 return; 387 case ATOM_SRC_WORD0: 388 case ATOM_SRC_WORD8: 389 case ATOM_SRC_WORD16: 390 (*ptr) += 2; 391 return; 392 case ATOM_SRC_BYTE0: 393 case ATOM_SRC_BYTE8: 394 case ATOM_SRC_BYTE16: 395 case ATOM_SRC_BYTE24: 396 (*ptr)++; 397 return; 398 } 399 return; 400 } 401 } 402 403 static uint32_t atom_get_src(atom_exec_context *ctx, uint8_t attr, int *ptr) 404 { 405 return atom_get_src_int(ctx, attr, ptr, NULL, 1); 406 } 407 408 static uint32_t atom_get_src_direct(atom_exec_context *ctx, uint8_t align, int *ptr) 409 { 410 uint32_t val = 0xCDCDCDCD; 411 412 switch (align) { 413 case ATOM_SRC_DWORD: 414 val = U32(*ptr); 415 (*ptr) += 4; 416 break; 417 case ATOM_SRC_WORD0: 418 case ATOM_SRC_WORD8: 419 case ATOM_SRC_WORD16: 420 val = U16(*ptr); 421 (*ptr) += 2; 422 break; 423 case ATOM_SRC_BYTE0: 424 case ATOM_SRC_BYTE8: 425 case ATOM_SRC_BYTE16: 426 case ATOM_SRC_BYTE24: 427 val = U8(*ptr); 428 (*ptr)++; 429 break; 430 } 431 return val; 432 } 433 434 static uint32_t atom_get_dst(atom_exec_context *ctx, int arg, uint8_t attr, 435 int *ptr, uint32_t *saved, int print) 436 { 437 return atom_get_src_int(ctx, 438 arg | atom_dst_to_src[(attr >> 3) & 439 7][(attr >> 6) & 3] << 3, 440 ptr, saved, print); 441 } 442 443 static void atom_skip_dst(atom_exec_context *ctx, int arg, uint8_t attr, int *ptr) 444 { 445 atom_skip_src_int(ctx, 446 arg | atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 447 3] << 3, ptr); 448 } 449 450 static void atom_put_dst(atom_exec_context *ctx, int arg, uint8_t attr, 451 int *ptr, uint32_t val, uint32_t saved) 452 { 453 uint32_t align = 454 atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3], old_val = 455 val, idx; 456 struct atom_context *gctx = ctx->ctx; 457 old_val &= atom_arg_mask[align] >> atom_arg_shift[align]; 458 val <<= atom_arg_shift[align]; 459 val &= atom_arg_mask[align]; 460 saved &= ~atom_arg_mask[align]; 461 val |= saved; 462 switch (arg) { 463 case ATOM_ARG_REG: 464 idx = U16(*ptr); 465 (*ptr) += 2; 466 DEBUG("REG[0x%04X]", idx); 467 idx += gctx->reg_block; 468 switch (gctx->io_mode) { 469 case ATOM_IO_MM: 470 if (idx == 0) 471 gctx->card->reg_write(gctx->card, idx, 472 val << 2); 473 else 474 gctx->card->reg_write(gctx->card, idx, val); 475 break; 476 case ATOM_IO_PCI: 477 pr_info("PCI registers are not implemented\n"); 478 return; 479 case ATOM_IO_SYSIO: 480 pr_info("SYSIO registers are not implemented\n"); 481 return; 482 default: 483 if (!(gctx->io_mode & 0x80)) { 484 pr_info("Bad IO mode\n"); 485 return; 486 } 487 if (!gctx->iio[gctx->io_mode & 0xFF]) { 488 pr_info("Undefined indirect IO write method %d\n", 489 gctx->io_mode & 0x7F); 490 return; 491 } 492 atom_iio_execute(gctx, gctx->iio[gctx->io_mode & 0xFF], 493 idx, val); 494 } 495 break; 496 case ATOM_ARG_PS: 497 idx = U8(*ptr); 498 (*ptr)++; 499 DEBUG("PS[0x%02X]", idx); 500 ctx->ps[idx] = cpu_to_le32(val); 501 break; 502 case ATOM_ARG_WS: 503 idx = U8(*ptr); 504 (*ptr)++; 505 DEBUG("WS[0x%02X]", idx); 506 switch (idx) { 507 case ATOM_WS_QUOTIENT: 508 gctx->divmul[0] = val; 509 break; 510 case ATOM_WS_REMAINDER: 511 gctx->divmul[1] = val; 512 break; 513 case ATOM_WS_DATAPTR: 514 gctx->data_block = val; 515 break; 516 case ATOM_WS_SHIFT: 517 gctx->shift = val; 518 break; 519 case ATOM_WS_OR_MASK: 520 case ATOM_WS_AND_MASK: 521 break; 522 case ATOM_WS_FB_WINDOW: 523 gctx->fb_base = val; 524 break; 525 case ATOM_WS_ATTRIBUTES: 526 gctx->io_attr = val; 527 break; 528 case ATOM_WS_REGPTR: 529 gctx->reg_block = val; 530 break; 531 default: 532 ctx->ws[idx] = val; 533 } 534 break; 535 case ATOM_ARG_FB: 536 idx = U8(*ptr); 537 (*ptr)++; 538 if ((gctx->fb_base + (idx * 4)) > gctx->scratch_size_bytes) { 539 DRM_ERROR("ATOM: fb write beyond scratch region: %d vs. %d\n", 540 gctx->fb_base + (idx * 4), gctx->scratch_size_bytes); 541 } else 542 gctx->scratch[(gctx->fb_base / 4) + idx] = val; 543 DEBUG("FB[0x%02X]", idx); 544 break; 545 case ATOM_ARG_PLL: 546 idx = U8(*ptr); 547 (*ptr)++; 548 DEBUG("PLL[0x%02X]", idx); 549 gctx->card->pll_write(gctx->card, idx, val); 550 break; 551 case ATOM_ARG_MC: 552 idx = U8(*ptr); 553 (*ptr)++; 554 DEBUG("MC[0x%02X]", idx); 555 gctx->card->mc_write(gctx->card, idx, val); 556 return; 557 } 558 switch (align) { 559 case ATOM_SRC_DWORD: 560 DEBUG(".[31:0] <- 0x%08X\n", old_val); 561 break; 562 case ATOM_SRC_WORD0: 563 DEBUG(".[15:0] <- 0x%04X\n", old_val); 564 break; 565 case ATOM_SRC_WORD8: 566 DEBUG(".[23:8] <- 0x%04X\n", old_val); 567 break; 568 case ATOM_SRC_WORD16: 569 DEBUG(".[31:16] <- 0x%04X\n", old_val); 570 break; 571 case ATOM_SRC_BYTE0: 572 DEBUG(".[7:0] <- 0x%02X\n", old_val); 573 break; 574 case ATOM_SRC_BYTE8: 575 DEBUG(".[15:8] <- 0x%02X\n", old_val); 576 break; 577 case ATOM_SRC_BYTE16: 578 DEBUG(".[23:16] <- 0x%02X\n", old_val); 579 break; 580 case ATOM_SRC_BYTE24: 581 DEBUG(".[31:24] <- 0x%02X\n", old_val); 582 break; 583 } 584 } 585 586 static void atom_op_add(atom_exec_context *ctx, int *ptr, int arg) 587 { 588 uint8_t attr = U8((*ptr)++); 589 uint32_t dst, src, saved; 590 int dptr = *ptr; 591 SDEBUG(" dst: "); 592 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 593 SDEBUG(" src: "); 594 src = atom_get_src(ctx, attr, ptr); 595 dst += src; 596 SDEBUG(" dst: "); 597 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 598 } 599 600 static void atom_op_and(atom_exec_context *ctx, int *ptr, int arg) 601 { 602 uint8_t attr = U8((*ptr)++); 603 uint32_t dst, src, saved; 604 int dptr = *ptr; 605 SDEBUG(" dst: "); 606 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 607 SDEBUG(" src: "); 608 src = atom_get_src(ctx, attr, ptr); 609 dst &= src; 610 SDEBUG(" dst: "); 611 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 612 } 613 614 static void atom_op_beep(atom_exec_context *ctx, int *ptr, int arg) 615 { 616 printk("ATOM BIOS beeped!\n"); 617 } 618 619 static void atom_op_calltable(atom_exec_context *ctx, int *ptr, int arg) 620 { 621 int idx = U8((*ptr)++); 622 int r = 0; 623 624 if (idx < ATOM_TABLE_NAMES_CNT) 625 SDEBUG(" table: %d (%s)\n", idx, atom_table_names[idx]); 626 else 627 SDEBUG(" table: %d\n", idx); 628 if (U16(ctx->ctx->cmd_table + 4 + 2 * idx)) 629 r = amdgpu_atom_execute_table_locked(ctx->ctx, idx, ctx->ps + ctx->ps_shift); 630 if (r) { 631 ctx->abort = true; 632 } 633 } 634 635 static void atom_op_clear(atom_exec_context *ctx, int *ptr, int arg) 636 { 637 uint8_t attr = U8((*ptr)++); 638 uint32_t saved; 639 int dptr = *ptr; 640 attr &= 0x38; 641 attr |= atom_def_dst[attr >> 3] << 6; 642 atom_get_dst(ctx, arg, attr, ptr, &saved, 0); 643 SDEBUG(" dst: "); 644 atom_put_dst(ctx, arg, attr, &dptr, 0, saved); 645 } 646 647 static void atom_op_compare(atom_exec_context *ctx, int *ptr, int arg) 648 { 649 uint8_t attr = U8((*ptr)++); 650 uint32_t dst, src; 651 SDEBUG(" src1: "); 652 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1); 653 SDEBUG(" src2: "); 654 src = atom_get_src(ctx, attr, ptr); 655 ctx->ctx->cs_equal = (dst == src); 656 ctx->ctx->cs_above = (dst > src); 657 SDEBUG(" result: %s %s\n", ctx->ctx->cs_equal ? "EQ" : "NE", 658 ctx->ctx->cs_above ? "GT" : "LE"); 659 } 660 661 static void atom_op_delay(atom_exec_context *ctx, int *ptr, int arg) 662 { 663 unsigned count = U8((*ptr)++); 664 SDEBUG(" count: %d\n", count); 665 if (arg == ATOM_UNIT_MICROSEC) 666 udelay(count); 667 else if (!drm_can_sleep()) 668 mdelay(count); 669 else 670 msleep(count); 671 } 672 673 static void atom_op_div(atom_exec_context *ctx, int *ptr, int arg) 674 { 675 uint8_t attr = U8((*ptr)++); 676 uint32_t dst, src; 677 SDEBUG(" src1: "); 678 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1); 679 SDEBUG(" src2: "); 680 src = atom_get_src(ctx, attr, ptr); 681 if (src != 0) { 682 ctx->ctx->divmul[0] = dst / src; 683 ctx->ctx->divmul[1] = dst % src; 684 } else { 685 ctx->ctx->divmul[0] = 0; 686 ctx->ctx->divmul[1] = 0; 687 } 688 } 689 690 static void atom_op_div32(atom_exec_context *ctx, int *ptr, int arg) 691 { 692 uint64_t val64; 693 uint8_t attr = U8((*ptr)++); 694 uint32_t dst, src; 695 SDEBUG(" src1: "); 696 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1); 697 SDEBUG(" src2: "); 698 src = atom_get_src(ctx, attr, ptr); 699 if (src != 0) { 700 val64 = dst; 701 val64 |= ((uint64_t)ctx->ctx->divmul[1]) << 32; 702 do_div(val64, src); 703 ctx->ctx->divmul[0] = lower_32_bits(val64); 704 ctx->ctx->divmul[1] = upper_32_bits(val64); 705 } else { 706 ctx->ctx->divmul[0] = 0; 707 ctx->ctx->divmul[1] = 0; 708 } 709 } 710 711 static void atom_op_eot(atom_exec_context *ctx, int *ptr, int arg) 712 { 713 /* functionally, a nop */ 714 } 715 716 static void atom_op_jump(atom_exec_context *ctx, int *ptr, int arg) 717 { 718 int execute = 0, target = U16(*ptr); 719 unsigned long cjiffies; 720 721 (*ptr) += 2; 722 switch (arg) { 723 case ATOM_COND_ABOVE: 724 execute = ctx->ctx->cs_above; 725 break; 726 case ATOM_COND_ABOVEOREQUAL: 727 execute = ctx->ctx->cs_above || ctx->ctx->cs_equal; 728 break; 729 case ATOM_COND_ALWAYS: 730 execute = 1; 731 break; 732 case ATOM_COND_BELOW: 733 execute = !(ctx->ctx->cs_above || ctx->ctx->cs_equal); 734 break; 735 case ATOM_COND_BELOWOREQUAL: 736 execute = !ctx->ctx->cs_above; 737 break; 738 case ATOM_COND_EQUAL: 739 execute = ctx->ctx->cs_equal; 740 break; 741 case ATOM_COND_NOTEQUAL: 742 execute = !ctx->ctx->cs_equal; 743 break; 744 } 745 if (arg != ATOM_COND_ALWAYS) 746 SDEBUG(" taken: %s\n", execute ? "yes" : "no"); 747 SDEBUG(" target: 0x%04X\n", target); 748 if (execute) { 749 if (ctx->last_jump == (ctx->start + target)) { 750 cjiffies = jiffies; 751 if (time_after(cjiffies, ctx->last_jump_jiffies)) { 752 cjiffies -= ctx->last_jump_jiffies; 753 if ((jiffies_to_msecs(cjiffies) > 5000)) { 754 DRM_ERROR("atombios stuck in loop for more than 5secs aborting\n"); 755 ctx->abort = true; 756 } 757 } else { 758 /* jiffies wrap around we will just wait a little longer */ 759 ctx->last_jump_jiffies = jiffies; 760 } 761 } else { 762 ctx->last_jump = ctx->start + target; 763 ctx->last_jump_jiffies = jiffies; 764 } 765 *ptr = ctx->start + target; 766 } 767 } 768 769 static void atom_op_mask(atom_exec_context *ctx, int *ptr, int arg) 770 { 771 uint8_t attr = U8((*ptr)++); 772 uint32_t dst, mask, src, saved; 773 int dptr = *ptr; 774 SDEBUG(" dst: "); 775 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 776 mask = atom_get_src_direct(ctx, ((attr >> 3) & 7), ptr); 777 SDEBUG(" mask: 0x%08x", mask); 778 SDEBUG(" src: "); 779 src = atom_get_src(ctx, attr, ptr); 780 dst &= mask; 781 dst |= src; 782 SDEBUG(" dst: "); 783 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 784 } 785 786 static void atom_op_move(atom_exec_context *ctx, int *ptr, int arg) 787 { 788 uint8_t attr = U8((*ptr)++); 789 uint32_t src, saved; 790 int dptr = *ptr; 791 if (((attr >> 3) & 7) != ATOM_SRC_DWORD) 792 atom_get_dst(ctx, arg, attr, ptr, &saved, 0); 793 else { 794 atom_skip_dst(ctx, arg, attr, ptr); 795 saved = 0xCDCDCDCD; 796 } 797 SDEBUG(" src: "); 798 src = atom_get_src(ctx, attr, ptr); 799 SDEBUG(" dst: "); 800 atom_put_dst(ctx, arg, attr, &dptr, src, saved); 801 } 802 803 static void atom_op_mul(atom_exec_context *ctx, int *ptr, int arg) 804 { 805 uint8_t attr = U8((*ptr)++); 806 uint32_t dst, src; 807 SDEBUG(" src1: "); 808 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1); 809 SDEBUG(" src2: "); 810 src = atom_get_src(ctx, attr, ptr); 811 ctx->ctx->divmul[0] = dst * src; 812 } 813 814 static void atom_op_mul32(atom_exec_context *ctx, int *ptr, int arg) 815 { 816 uint64_t val64; 817 uint8_t attr = U8((*ptr)++); 818 uint32_t dst, src; 819 SDEBUG(" src1: "); 820 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1); 821 SDEBUG(" src2: "); 822 src = atom_get_src(ctx, attr, ptr); 823 val64 = (uint64_t)dst * (uint64_t)src; 824 ctx->ctx->divmul[0] = lower_32_bits(val64); 825 ctx->ctx->divmul[1] = upper_32_bits(val64); 826 } 827 828 static void atom_op_nop(atom_exec_context *ctx, int *ptr, int arg) 829 { 830 /* nothing */ 831 } 832 833 static void atom_op_or(atom_exec_context *ctx, int *ptr, int arg) 834 { 835 uint8_t attr = U8((*ptr)++); 836 uint32_t dst, src, saved; 837 int dptr = *ptr; 838 SDEBUG(" dst: "); 839 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 840 SDEBUG(" src: "); 841 src = atom_get_src(ctx, attr, ptr); 842 dst |= src; 843 SDEBUG(" dst: "); 844 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 845 } 846 847 static void atom_op_postcard(atom_exec_context *ctx, int *ptr, int arg) 848 { 849 uint8_t val = U8((*ptr)++); 850 SDEBUG("POST card output: 0x%02X\n", val); 851 } 852 853 static void atom_op_repeat(atom_exec_context *ctx, int *ptr, int arg) 854 { 855 pr_info("unimplemented!\n"); 856 } 857 858 static void atom_op_restorereg(atom_exec_context *ctx, int *ptr, int arg) 859 { 860 pr_info("unimplemented!\n"); 861 } 862 863 static void atom_op_savereg(atom_exec_context *ctx, int *ptr, int arg) 864 { 865 pr_info("unimplemented!\n"); 866 } 867 868 static void atom_op_setdatablock(atom_exec_context *ctx, int *ptr, int arg) 869 { 870 int idx = U8(*ptr); 871 (*ptr)++; 872 SDEBUG(" block: %d\n", idx); 873 if (!idx) 874 ctx->ctx->data_block = 0; 875 else if (idx == 255) 876 ctx->ctx->data_block = ctx->start; 877 else 878 ctx->ctx->data_block = U16(ctx->ctx->data_table + 4 + 2 * idx); 879 SDEBUG(" base: 0x%04X\n", ctx->ctx->data_block); 880 } 881 882 static void atom_op_setfbbase(atom_exec_context *ctx, int *ptr, int arg) 883 { 884 uint8_t attr = U8((*ptr)++); 885 SDEBUG(" fb_base: "); 886 ctx->ctx->fb_base = atom_get_src(ctx, attr, ptr); 887 } 888 889 static void atom_op_setport(atom_exec_context *ctx, int *ptr, int arg) 890 { 891 int port; 892 switch (arg) { 893 case ATOM_PORT_ATI: 894 port = U16(*ptr); 895 if (port < ATOM_IO_NAMES_CNT) 896 SDEBUG(" port: %d (%s)\n", port, atom_io_names[port]); 897 else 898 SDEBUG(" port: %d\n", port); 899 if (!port) 900 ctx->ctx->io_mode = ATOM_IO_MM; 901 else 902 ctx->ctx->io_mode = ATOM_IO_IIO | port; 903 (*ptr) += 2; 904 break; 905 case ATOM_PORT_PCI: 906 ctx->ctx->io_mode = ATOM_IO_PCI; 907 (*ptr)++; 908 break; 909 case ATOM_PORT_SYSIO: 910 ctx->ctx->io_mode = ATOM_IO_SYSIO; 911 (*ptr)++; 912 break; 913 } 914 } 915 916 static void atom_op_setregblock(atom_exec_context *ctx, int *ptr, int arg) 917 { 918 ctx->ctx->reg_block = U16(*ptr); 919 (*ptr) += 2; 920 SDEBUG(" base: 0x%04X\n", ctx->ctx->reg_block); 921 } 922 923 static void atom_op_shift_left(atom_exec_context *ctx, int *ptr, int arg) 924 { 925 uint8_t attr = U8((*ptr)++), shift; 926 uint32_t saved, dst; 927 int dptr = *ptr; 928 attr &= 0x38; 929 attr |= atom_def_dst[attr >> 3] << 6; 930 SDEBUG(" dst: "); 931 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 932 shift = atom_get_src_direct(ctx, ATOM_SRC_BYTE0, ptr); 933 SDEBUG(" shift: %d\n", shift); 934 dst <<= shift; 935 SDEBUG(" dst: "); 936 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 937 } 938 939 static void atom_op_shift_right(atom_exec_context *ctx, int *ptr, int arg) 940 { 941 uint8_t attr = U8((*ptr)++), shift; 942 uint32_t saved, dst; 943 int dptr = *ptr; 944 attr &= 0x38; 945 attr |= atom_def_dst[attr >> 3] << 6; 946 SDEBUG(" dst: "); 947 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 948 shift = atom_get_src_direct(ctx, ATOM_SRC_BYTE0, ptr); 949 SDEBUG(" shift: %d\n", shift); 950 dst >>= shift; 951 SDEBUG(" dst: "); 952 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 953 } 954 955 static void atom_op_shl(atom_exec_context *ctx, int *ptr, int arg) 956 { 957 uint8_t attr = U8((*ptr)++), shift; 958 uint32_t saved, dst; 959 int dptr = *ptr; 960 uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3]; 961 SDEBUG(" dst: "); 962 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 963 /* op needs to full dst value */ 964 dst = saved; 965 shift = atom_get_src(ctx, attr, ptr); 966 SDEBUG(" shift: %d\n", shift); 967 dst <<= shift; 968 dst &= atom_arg_mask[dst_align]; 969 dst >>= atom_arg_shift[dst_align]; 970 SDEBUG(" dst: "); 971 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 972 } 973 974 static void atom_op_shr(atom_exec_context *ctx, int *ptr, int arg) 975 { 976 uint8_t attr = U8((*ptr)++), shift; 977 uint32_t saved, dst; 978 int dptr = *ptr; 979 uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3]; 980 SDEBUG(" dst: "); 981 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 982 /* op needs to full dst value */ 983 dst = saved; 984 shift = atom_get_src(ctx, attr, ptr); 985 SDEBUG(" shift: %d\n", shift); 986 dst >>= shift; 987 dst &= atom_arg_mask[dst_align]; 988 dst >>= atom_arg_shift[dst_align]; 989 SDEBUG(" dst: "); 990 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 991 } 992 993 static void atom_op_sub(atom_exec_context *ctx, int *ptr, int arg) 994 { 995 uint8_t attr = U8((*ptr)++); 996 uint32_t dst, src, saved; 997 int dptr = *ptr; 998 SDEBUG(" dst: "); 999 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 1000 SDEBUG(" src: "); 1001 src = atom_get_src(ctx, attr, ptr); 1002 dst -= src; 1003 SDEBUG(" dst: "); 1004 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 1005 } 1006 1007 static void atom_op_switch(atom_exec_context *ctx, int *ptr, int arg) 1008 { 1009 uint8_t attr = U8((*ptr)++); 1010 uint32_t src, val, target; 1011 SDEBUG(" switch: "); 1012 src = atom_get_src(ctx, attr, ptr); 1013 while (U16(*ptr) != ATOM_CASE_END) 1014 if (U8(*ptr) == ATOM_CASE_MAGIC) { 1015 (*ptr)++; 1016 SDEBUG(" case: "); 1017 val = 1018 atom_get_src(ctx, (attr & 0x38) | ATOM_ARG_IMM, 1019 ptr); 1020 target = U16(*ptr); 1021 if (val == src) { 1022 SDEBUG(" target: %04X\n", target); 1023 *ptr = ctx->start + target; 1024 return; 1025 } 1026 (*ptr) += 2; 1027 } else { 1028 pr_info("Bad case\n"); 1029 return; 1030 } 1031 (*ptr) += 2; 1032 } 1033 1034 static void atom_op_test(atom_exec_context *ctx, int *ptr, int arg) 1035 { 1036 uint8_t attr = U8((*ptr)++); 1037 uint32_t dst, src; 1038 SDEBUG(" src1: "); 1039 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1); 1040 SDEBUG(" src2: "); 1041 src = atom_get_src(ctx, attr, ptr); 1042 ctx->ctx->cs_equal = ((dst & src) == 0); 1043 SDEBUG(" result: %s\n", ctx->ctx->cs_equal ? "EQ" : "NE"); 1044 } 1045 1046 static void atom_op_xor(atom_exec_context *ctx, int *ptr, int arg) 1047 { 1048 uint8_t attr = U8((*ptr)++); 1049 uint32_t dst, src, saved; 1050 int dptr = *ptr; 1051 SDEBUG(" dst: "); 1052 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 1053 SDEBUG(" src: "); 1054 src = atom_get_src(ctx, attr, ptr); 1055 dst ^= src; 1056 SDEBUG(" dst: "); 1057 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 1058 } 1059 1060 static void atom_op_debug(atom_exec_context *ctx, int *ptr, int arg) 1061 { 1062 uint8_t val = U8((*ptr)++); 1063 SDEBUG("DEBUG output: 0x%02X\n", val); 1064 } 1065 1066 static void atom_op_processds(atom_exec_context *ctx, int *ptr, int arg) 1067 { 1068 uint16_t val = U16(*ptr); 1069 (*ptr) += val + 2; 1070 SDEBUG("PROCESSDS output: 0x%02X\n", val); 1071 } 1072 1073 static struct { 1074 void (*func) (atom_exec_context *, int *, int); 1075 int arg; 1076 } opcode_table[ATOM_OP_CNT] = { 1077 { 1078 NULL, 0}, { 1079 atom_op_move, ATOM_ARG_REG}, { 1080 atom_op_move, ATOM_ARG_PS}, { 1081 atom_op_move, ATOM_ARG_WS}, { 1082 atom_op_move, ATOM_ARG_FB}, { 1083 atom_op_move, ATOM_ARG_PLL}, { 1084 atom_op_move, ATOM_ARG_MC}, { 1085 atom_op_and, ATOM_ARG_REG}, { 1086 atom_op_and, ATOM_ARG_PS}, { 1087 atom_op_and, ATOM_ARG_WS}, { 1088 atom_op_and, ATOM_ARG_FB}, { 1089 atom_op_and, ATOM_ARG_PLL}, { 1090 atom_op_and, ATOM_ARG_MC}, { 1091 atom_op_or, ATOM_ARG_REG}, { 1092 atom_op_or, ATOM_ARG_PS}, { 1093 atom_op_or, ATOM_ARG_WS}, { 1094 atom_op_or, ATOM_ARG_FB}, { 1095 atom_op_or, ATOM_ARG_PLL}, { 1096 atom_op_or, ATOM_ARG_MC}, { 1097 atom_op_shift_left, ATOM_ARG_REG}, { 1098 atom_op_shift_left, ATOM_ARG_PS}, { 1099 atom_op_shift_left, ATOM_ARG_WS}, { 1100 atom_op_shift_left, ATOM_ARG_FB}, { 1101 atom_op_shift_left, ATOM_ARG_PLL}, { 1102 atom_op_shift_left, ATOM_ARG_MC}, { 1103 atom_op_shift_right, ATOM_ARG_REG}, { 1104 atom_op_shift_right, ATOM_ARG_PS}, { 1105 atom_op_shift_right, ATOM_ARG_WS}, { 1106 atom_op_shift_right, ATOM_ARG_FB}, { 1107 atom_op_shift_right, ATOM_ARG_PLL}, { 1108 atom_op_shift_right, ATOM_ARG_MC}, { 1109 atom_op_mul, ATOM_ARG_REG}, { 1110 atom_op_mul, ATOM_ARG_PS}, { 1111 atom_op_mul, ATOM_ARG_WS}, { 1112 atom_op_mul, ATOM_ARG_FB}, { 1113 atom_op_mul, ATOM_ARG_PLL}, { 1114 atom_op_mul, ATOM_ARG_MC}, { 1115 atom_op_div, ATOM_ARG_REG}, { 1116 atom_op_div, ATOM_ARG_PS}, { 1117 atom_op_div, ATOM_ARG_WS}, { 1118 atom_op_div, ATOM_ARG_FB}, { 1119 atom_op_div, ATOM_ARG_PLL}, { 1120 atom_op_div, ATOM_ARG_MC}, { 1121 atom_op_add, ATOM_ARG_REG}, { 1122 atom_op_add, ATOM_ARG_PS}, { 1123 atom_op_add, ATOM_ARG_WS}, { 1124 atom_op_add, ATOM_ARG_FB}, { 1125 atom_op_add, ATOM_ARG_PLL}, { 1126 atom_op_add, ATOM_ARG_MC}, { 1127 atom_op_sub, ATOM_ARG_REG}, { 1128 atom_op_sub, ATOM_ARG_PS}, { 1129 atom_op_sub, ATOM_ARG_WS}, { 1130 atom_op_sub, ATOM_ARG_FB}, { 1131 atom_op_sub, ATOM_ARG_PLL}, { 1132 atom_op_sub, ATOM_ARG_MC}, { 1133 atom_op_setport, ATOM_PORT_ATI}, { 1134 atom_op_setport, ATOM_PORT_PCI}, { 1135 atom_op_setport, ATOM_PORT_SYSIO}, { 1136 atom_op_setregblock, 0}, { 1137 atom_op_setfbbase, 0}, { 1138 atom_op_compare, ATOM_ARG_REG}, { 1139 atom_op_compare, ATOM_ARG_PS}, { 1140 atom_op_compare, ATOM_ARG_WS}, { 1141 atom_op_compare, ATOM_ARG_FB}, { 1142 atom_op_compare, ATOM_ARG_PLL}, { 1143 atom_op_compare, ATOM_ARG_MC}, { 1144 atom_op_switch, 0}, { 1145 atom_op_jump, ATOM_COND_ALWAYS}, { 1146 atom_op_jump, ATOM_COND_EQUAL}, { 1147 atom_op_jump, ATOM_COND_BELOW}, { 1148 atom_op_jump, ATOM_COND_ABOVE}, { 1149 atom_op_jump, ATOM_COND_BELOWOREQUAL}, { 1150 atom_op_jump, ATOM_COND_ABOVEOREQUAL}, { 1151 atom_op_jump, ATOM_COND_NOTEQUAL}, { 1152 atom_op_test, ATOM_ARG_REG}, { 1153 atom_op_test, ATOM_ARG_PS}, { 1154 atom_op_test, ATOM_ARG_WS}, { 1155 atom_op_test, ATOM_ARG_FB}, { 1156 atom_op_test, ATOM_ARG_PLL}, { 1157 atom_op_test, ATOM_ARG_MC}, { 1158 atom_op_delay, ATOM_UNIT_MILLISEC}, { 1159 atom_op_delay, ATOM_UNIT_MICROSEC}, { 1160 atom_op_calltable, 0}, { 1161 atom_op_repeat, 0}, { 1162 atom_op_clear, ATOM_ARG_REG}, { 1163 atom_op_clear, ATOM_ARG_PS}, { 1164 atom_op_clear, ATOM_ARG_WS}, { 1165 atom_op_clear, ATOM_ARG_FB}, { 1166 atom_op_clear, ATOM_ARG_PLL}, { 1167 atom_op_clear, ATOM_ARG_MC}, { 1168 atom_op_nop, 0}, { 1169 atom_op_eot, 0}, { 1170 atom_op_mask, ATOM_ARG_REG}, { 1171 atom_op_mask, ATOM_ARG_PS}, { 1172 atom_op_mask, ATOM_ARG_WS}, { 1173 atom_op_mask, ATOM_ARG_FB}, { 1174 atom_op_mask, ATOM_ARG_PLL}, { 1175 atom_op_mask, ATOM_ARG_MC}, { 1176 atom_op_postcard, 0}, { 1177 atom_op_beep, 0}, { 1178 atom_op_savereg, 0}, { 1179 atom_op_restorereg, 0}, { 1180 atom_op_setdatablock, 0}, { 1181 atom_op_xor, ATOM_ARG_REG}, { 1182 atom_op_xor, ATOM_ARG_PS}, { 1183 atom_op_xor, ATOM_ARG_WS}, { 1184 atom_op_xor, ATOM_ARG_FB}, { 1185 atom_op_xor, ATOM_ARG_PLL}, { 1186 atom_op_xor, ATOM_ARG_MC}, { 1187 atom_op_shl, ATOM_ARG_REG}, { 1188 atom_op_shl, ATOM_ARG_PS}, { 1189 atom_op_shl, ATOM_ARG_WS}, { 1190 atom_op_shl, ATOM_ARG_FB}, { 1191 atom_op_shl, ATOM_ARG_PLL}, { 1192 atom_op_shl, ATOM_ARG_MC}, { 1193 atom_op_shr, ATOM_ARG_REG}, { 1194 atom_op_shr, ATOM_ARG_PS}, { 1195 atom_op_shr, ATOM_ARG_WS}, { 1196 atom_op_shr, ATOM_ARG_FB}, { 1197 atom_op_shr, ATOM_ARG_PLL}, { 1198 atom_op_shr, ATOM_ARG_MC}, { 1199 atom_op_debug, 0}, { 1200 atom_op_processds, 0}, { 1201 atom_op_mul32, ATOM_ARG_PS}, { 1202 atom_op_mul32, ATOM_ARG_WS}, { 1203 atom_op_div32, ATOM_ARG_PS}, { 1204 atom_op_div32, ATOM_ARG_WS}, 1205 }; 1206 1207 static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params) 1208 { 1209 int base = CU16(ctx->cmd_table + 4 + 2 * index); 1210 int len, ws, ps, ptr; 1211 unsigned char op; 1212 atom_exec_context ectx; 1213 int ret = 0; 1214 1215 if (!base) 1216 return -EINVAL; 1217 1218 len = CU16(base + ATOM_CT_SIZE_PTR); 1219 ws = CU8(base + ATOM_CT_WS_PTR); 1220 ps = CU8(base + ATOM_CT_PS_PTR) & ATOM_CT_PS_MASK; 1221 ptr = base + ATOM_CT_CODE_PTR; 1222 1223 SDEBUG(">> execute %04X (len %d, WS %d, PS %d)\n", base, len, ws, ps); 1224 1225 ectx.ctx = ctx; 1226 ectx.ps_shift = ps / 4; 1227 ectx.start = base; 1228 ectx.ps = params; 1229 ectx.abort = false; 1230 ectx.last_jump = 0; 1231 if (ws) 1232 ectx.ws = kcalloc(4, ws, GFP_KERNEL); 1233 else 1234 ectx.ws = NULL; 1235 1236 debug_depth++; 1237 while (1) { 1238 op = CU8(ptr++); 1239 if (op < ATOM_OP_NAMES_CNT) 1240 SDEBUG("%s @ 0x%04X\n", atom_op_names[op], ptr - 1); 1241 else 1242 SDEBUG("[%d] @ 0x%04X\n", op, ptr - 1); 1243 if (ectx.abort) { 1244 DRM_ERROR("atombios stuck executing %04X (len %d, WS %d, PS %d) @ 0x%04X\n", 1245 base, len, ws, ps, ptr - 1); 1246 ret = -EINVAL; 1247 goto free; 1248 } 1249 1250 if (op < ATOM_OP_CNT && op > 0) 1251 opcode_table[op].func(&ectx, &ptr, 1252 opcode_table[op].arg); 1253 else 1254 break; 1255 1256 if (op == ATOM_OP_EOT) 1257 break; 1258 } 1259 debug_depth--; 1260 SDEBUG("<<\n"); 1261 1262 free: 1263 if (ws) 1264 kfree(ectx.ws); 1265 return ret; 1266 } 1267 1268 int amdgpu_atom_execute_table(struct atom_context *ctx, int index, uint32_t * params) 1269 { 1270 int r; 1271 1272 mutex_lock(&ctx->mutex); 1273 /* reset data block */ 1274 ctx->data_block = 0; 1275 /* reset reg block */ 1276 ctx->reg_block = 0; 1277 /* reset fb window */ 1278 ctx->fb_base = 0; 1279 /* reset io mode */ 1280 ctx->io_mode = ATOM_IO_MM; 1281 /* reset divmul */ 1282 ctx->divmul[0] = 0; 1283 ctx->divmul[1] = 0; 1284 r = amdgpu_atom_execute_table_locked(ctx, index, params); 1285 mutex_unlock(&ctx->mutex); 1286 return r; 1287 } 1288 1289 static int atom_iio_len[] = { 1, 2, 3, 3, 3, 3, 4, 4, 4, 3 }; 1290 1291 static void atom_index_iio(struct atom_context *ctx, int base) 1292 { 1293 ctx->iio = kzalloc(2 * 256, GFP_KERNEL); 1294 if (!ctx->iio) 1295 return; 1296 while (CU8(base) == ATOM_IIO_START) { 1297 ctx->iio[CU8(base + 1)] = base + 2; 1298 base += 2; 1299 while (CU8(base) != ATOM_IIO_END) 1300 base += atom_iio_len[CU8(base)]; 1301 base += 3; 1302 } 1303 } 1304 1305 struct atom_context *amdgpu_atom_parse(struct card_info *card, void *bios) 1306 { 1307 int base; 1308 struct atom_context *ctx = 1309 kzalloc(sizeof(struct atom_context), GFP_KERNEL); 1310 char *str; 1311 u16 idx; 1312 1313 if (!ctx) 1314 return NULL; 1315 1316 ctx->card = card; 1317 ctx->bios = bios; 1318 1319 if (CU16(0) != ATOM_BIOS_MAGIC) { 1320 pr_info("Invalid BIOS magic\n"); 1321 kfree(ctx); 1322 return NULL; 1323 } 1324 if (strncmp 1325 (CSTR(ATOM_ATI_MAGIC_PTR), ATOM_ATI_MAGIC, 1326 strlen(ATOM_ATI_MAGIC))) { 1327 pr_info("Invalid ATI magic\n"); 1328 kfree(ctx); 1329 return NULL; 1330 } 1331 1332 base = CU16(ATOM_ROM_TABLE_PTR); 1333 if (strncmp 1334 (CSTR(base + ATOM_ROM_MAGIC_PTR), ATOM_ROM_MAGIC, 1335 strlen(ATOM_ROM_MAGIC))) { 1336 pr_info("Invalid ATOM magic\n"); 1337 kfree(ctx); 1338 return NULL; 1339 } 1340 1341 ctx->cmd_table = CU16(base + ATOM_ROM_CMD_PTR); 1342 ctx->data_table = CU16(base + ATOM_ROM_DATA_PTR); 1343 atom_index_iio(ctx, CU16(ctx->data_table + ATOM_DATA_IIO_PTR) + 4); 1344 if (!ctx->iio) { 1345 amdgpu_atom_destroy(ctx); 1346 return NULL; 1347 } 1348 1349 idx = CU16(ATOM_ROM_PART_NUMBER_PTR); 1350 if (idx == 0) 1351 idx = 0x80; 1352 1353 str = CSTR(idx); 1354 if (*str != '\0') { 1355 pr_info("ATOM BIOS: %s\n", str); 1356 strlcpy(ctx->vbios_version, str, sizeof(ctx->vbios_version)); 1357 } 1358 1359 1360 return ctx; 1361 } 1362 1363 int amdgpu_atom_asic_init(struct atom_context *ctx) 1364 { 1365 int hwi = CU16(ctx->data_table + ATOM_DATA_FWI_PTR); 1366 uint32_t ps[16]; 1367 int ret; 1368 1369 memset(ps, 0, 64); 1370 1371 ps[0] = cpu_to_le32(CU32(hwi + ATOM_FWI_DEFSCLK_PTR)); 1372 ps[1] = cpu_to_le32(CU32(hwi + ATOM_FWI_DEFMCLK_PTR)); 1373 if (!ps[0] || !ps[1]) 1374 return 1; 1375 1376 if (!CU16(ctx->cmd_table + 4 + 2 * ATOM_CMD_INIT)) 1377 return 1; 1378 ret = amdgpu_atom_execute_table(ctx, ATOM_CMD_INIT, ps); 1379 if (ret) 1380 return ret; 1381 1382 memset(ps, 0, 64); 1383 1384 return ret; 1385 } 1386 1387 void amdgpu_atom_destroy(struct atom_context *ctx) 1388 { 1389 kfree(ctx->iio); 1390 kfree(ctx); 1391 } 1392 1393 bool amdgpu_atom_parse_data_header(struct atom_context *ctx, int index, 1394 uint16_t * size, uint8_t * frev, uint8_t * crev, 1395 uint16_t * data_start) 1396 { 1397 int offset = index * 2 + 4; 1398 int idx = CU16(ctx->data_table + offset); 1399 u16 *mdt = (u16 *)(ctx->bios + ctx->data_table + 4); 1400 1401 if (!mdt[index]) 1402 return false; 1403 1404 if (size) 1405 *size = CU16(idx); 1406 if (frev) 1407 *frev = CU8(idx + 2); 1408 if (crev) 1409 *crev = CU8(idx + 3); 1410 *data_start = idx; 1411 return true; 1412 } 1413 1414 bool amdgpu_atom_parse_cmd_header(struct atom_context *ctx, int index, uint8_t * frev, 1415 uint8_t * crev) 1416 { 1417 int offset = index * 2 + 4; 1418 int idx = CU16(ctx->cmd_table + offset); 1419 u16 *mct = (u16 *)(ctx->bios + ctx->cmd_table + 4); 1420 1421 if (!mct[index]) 1422 return false; 1423 1424 if (frev) 1425 *frev = CU8(idx + 2); 1426 if (crev) 1427 *crev = CU8(idx + 3); 1428 return true; 1429 } 1430 1431
Indexes created Sun Sep 21 20:09:37 GMT 2025