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      1 /*	$NetBSD: amdgpu_df.h,v 1.2 2021/12/18 23:44:58 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright 2020 Advanced Micro Devices, Inc.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     22  * OTHER DEALINGS IN THE SOFTWARE.
     23  *
     24  */
     25 
     26 #ifndef __AMDGPU_DF_H__
     27 #define __AMDGPU_DF_H__
     28 
     29 struct amdgpu_df_hash_status {
     30 	bool hash_64k;
     31 	bool hash_2m;
     32 	bool hash_1g;
     33 };
     34 
     35 struct amdgpu_df_funcs {
     36 	void (*sw_init)(struct amdgpu_device *adev);
     37 	void (*sw_fini)(struct amdgpu_device *adev);
     38 	void (*enable_broadcast_mode)(struct amdgpu_device *adev,
     39 				      bool enable);
     40 	u32 (*get_fb_channel_number)(struct amdgpu_device *adev);
     41 	u32 (*get_hbm_channel_number)(struct amdgpu_device *adev);
     42 	void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
     43 						 bool enable);
     44 	void (*get_clockgating_state)(struct amdgpu_device *adev,
     45 				      u32 *flags);
     46 	void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev,
     47 					    bool enable);
     48 	int (*pmc_start)(struct amdgpu_device *adev, uint64_t config,
     49 					 int is_enable);
     50 	int (*pmc_stop)(struct amdgpu_device *adev, uint64_t config,
     51 					 int is_disable);
     52 	void (*pmc_get_count)(struct amdgpu_device *adev, uint64_t config,
     53 					 uint64_t *count);
     54 	uint64_t (*get_fica)(struct amdgpu_device *adev, uint32_t ficaa_val);
     55 	void (*set_fica)(struct amdgpu_device *adev, uint32_t ficaa_val,
     56 			 uint32_t ficadl_val, uint32_t ficadh_val);
     57 	uint64_t (*get_dram_base_addr)(struct amdgpu_device *adev,
     58 				       uint32_t df_inst);
     59 	uint32_t (*get_df_inst_id)(struct amdgpu_device *adev);
     60 };
     61 
     62 struct amdgpu_df {
     63 	struct amdgpu_df_hash_status	hash_status;
     64 	const struct amdgpu_df_funcs	*funcs;
     65 };
     66 
     67 #endif /* __AMDGPU_DF_H__ */
     68