1 /* $NetBSD: amdgpu.h,v 1.10 2025/05/09 20:18:25 tnn Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 #ifndef __AMDGPU_H__ 31 #define __AMDGPU_H__ 32 33 #ifdef _KERNEL_OPT 34 #include "opt_amdgpu_cik.h" 35 #include "opt_amdgpu_si.h" 36 #endif 37 38 #ifdef AMDGPU_CIK 39 #define CONFIG_DRM_AMDGPU_CIK 1 40 #endif 41 #ifdef AMDGPU_SI 42 #define CONFIG_DRM_AMDGPU_SI 1 43 #endif 44 #include "amdgpu_ctx.h" 45 46 #include <linux/atomic.h> 47 #include <linux/wait.h> 48 #include <linux/list.h> 49 #include <linux/kref.h> 50 #include <linux/rbtree.h> 51 #include <linux/hashtable.h> 52 #include <linux/dma-fence.h> 53 #include <linux/acpi.h> 54 55 #include <drm/ttm/ttm_bo_api.h> 56 #include <drm/ttm/ttm_bo_driver.h> 57 #include <drm/ttm/ttm_placement.h> 58 #include <drm/ttm/ttm_module.h> 59 #include <drm/ttm/ttm_execbuf_util.h> 60 61 #include <drm/amdgpu_drm.h> 62 #include <drm/drm_gem.h> 63 #include <drm/drm_ioctl.h> 64 #include <drm/gpu_scheduler.h> 65 66 #include <kgd_kfd_interface.h> 67 #include "dm_pp_interface.h" 68 #include "kgd_pp_interface.h" 69 70 #include "amd_shared.h" 71 #include "amdgpu_mode.h" 72 #include "amdgpu_ih.h" 73 #include "amdgpu_irq.h" 74 #include "amdgpu_ucode.h" 75 #include "amdgpu_ttm.h" 76 #include "amdgpu_psp.h" 77 #include "amdgpu_gds.h" 78 #include "amdgpu_sync.h" 79 #include "amdgpu_ring.h" 80 #include "amdgpu_vm.h" 81 #include "amdgpu_dpm.h" 82 #include "amdgpu_acp.h" 83 #include "amdgpu_uvd.h" 84 #include "amdgpu_vce.h" 85 #include "amdgpu_vcn.h" 86 #include "amdgpu_jpeg.h" 87 #include "amdgpu_mn.h" 88 #include "amdgpu_gmc.h" 89 #include "amdgpu_gfx.h" 90 #include "amdgpu_sdma.h" 91 #include "amdgpu_nbio.h" 92 #include "amdgpu_dm.h" 93 #include "amdgpu_virt.h" 94 #include "amdgpu_csa.h" 95 #include "amdgpu_gart.h" 96 #include "amdgpu_debugfs.h" 97 #include "amdgpu_job.h" 98 #include "amdgpu_bo_list.h" 99 #include "amdgpu_gem.h" 100 #include "amdgpu_doorbell.h" 101 #include "amdgpu_amdkfd.h" 102 #include "amdgpu_smu.h" 103 #include "amdgpu_discovery.h" 104 #include "amdgpu_mes.h" 105 #include "amdgpu_umc.h" 106 #include "amdgpu_mmhub.h" 107 #include "amdgpu_df.h" 108 109 #define MAX_GPU_INSTANCE 16 110 111 struct amdgpu_gpu_instance 112 { 113 struct amdgpu_device *adev; 114 int mgpu_fan_enabled; 115 }; 116 117 struct amdgpu_mgpu_info 118 { 119 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 120 struct mutex mutex; 121 uint32_t num_gpu; 122 uint32_t num_dgpu; 123 uint32_t num_apu; 124 }; 125 126 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 127 128 /* 129 * Modules parameters. 130 */ 131 extern int amdgpu_modeset; 132 extern int amdgpu_vram_limit; 133 extern int amdgpu_vis_vram_limit; 134 extern int amdgpu_gart_size; 135 extern int amdgpu_gtt_size; 136 extern int amdgpu_moverate; 137 extern int amdgpu_benchmarking; 138 extern int amdgpu_testing; 139 extern int amdgpu_audio; 140 extern int amdgpu_disp_priority; 141 extern int amdgpu_hw_i2c; 142 extern int amdgpu_pcie_gen2; 143 extern int amdgpu_msi; 144 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 145 extern int amdgpu_dpm; 146 extern int amdgpu_fw_load_type; 147 extern int amdgpu_aspm; 148 extern int amdgpu_runtime_pm; 149 extern uint amdgpu_ip_block_mask; 150 extern int amdgpu_bapm; 151 extern int amdgpu_deep_color; 152 extern int amdgpu_vm_size; 153 extern int amdgpu_vm_block_size; 154 extern int amdgpu_vm_fragment_size; 155 extern int amdgpu_vm_fault_stop; 156 extern int amdgpu_vm_debug; 157 extern int amdgpu_vm_update_mode; 158 extern int amdgpu_exp_hw_support; 159 extern int amdgpu_dc; 160 extern int amdgpu_sched_jobs; 161 extern int amdgpu_sched_hw_submission; 162 extern uint amdgpu_pcie_gen_cap; 163 extern uint amdgpu_pcie_lane_cap; 164 extern uint amdgpu_cg_mask; 165 extern uint amdgpu_pg_mask; 166 extern uint amdgpu_sdma_phase_quantum; 167 extern char *amdgpu_disable_cu; 168 extern char *amdgpu_virtual_display; 169 extern uint amdgpu_pp_feature_mask; 170 extern uint amdgpu_force_long_training; 171 extern int amdgpu_job_hang_limit; 172 extern int amdgpu_lbpw; 173 extern int amdgpu_compute_multipipe; 174 extern int amdgpu_gpu_recovery; 175 extern int amdgpu_emu_mode; 176 extern uint amdgpu_smu_memory_pool_size; 177 extern uint amdgpu_dc_feature_mask; 178 extern uint amdgpu_dm_abm_level; 179 extern struct amdgpu_mgpu_info mgpu_info; 180 extern int amdgpu_ras_enable; 181 extern uint amdgpu_ras_mask; 182 extern int amdgpu_async_gfx_ring; 183 extern int amdgpu_mcbp; 184 extern int amdgpu_discovery; 185 extern int amdgpu_mes; 186 extern int amdgpu_noretry; 187 extern int amdgpu_force_asic_type; 188 #ifdef CONFIG_HSA_AMD 189 extern int sched_policy; 190 #else 191 static const int sched_policy = KFD_SCHED_POLICY_HWS; 192 #endif 193 194 #ifdef CONFIG_DRM_AMDGPU_SI 195 extern int amdgpu_si_support; 196 #endif 197 #ifdef CONFIG_DRM_AMDGPU_CIK 198 extern int amdgpu_cik_support; 199 #endif 200 201 #define AMDGPU_VM_MAX_NUM_CTX 4096 202 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 203 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 204 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 205 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 206 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 207 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 208 #define AMDGPU_IB_POOL_SIZE 16 209 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 210 #define AMDGPUFB_CONN_LIMIT 4 211 #define AMDGPU_BIOS_NUM_SCRATCH 16 212 213 /* hard reset data */ 214 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 215 216 /* reset flags */ 217 #define AMDGPU_RESET_GFX (1 << 0) 218 #define AMDGPU_RESET_COMPUTE (1 << 1) 219 #define AMDGPU_RESET_DMA (1 << 2) 220 #define AMDGPU_RESET_CP (1 << 3) 221 #define AMDGPU_RESET_GRBM (1 << 4) 222 #define AMDGPU_RESET_DMA1 (1 << 5) 223 #define AMDGPU_RESET_RLC (1 << 6) 224 #define AMDGPU_RESET_SEM (1 << 7) 225 #define AMDGPU_RESET_IH (1 << 8) 226 #define AMDGPU_RESET_VMC (1 << 9) 227 #define AMDGPU_RESET_MC (1 << 10) 228 #define AMDGPU_RESET_DISPLAY (1 << 11) 229 #define AMDGPU_RESET_UVD (1 << 12) 230 #define AMDGPU_RESET_VCE (1 << 13) 231 #define AMDGPU_RESET_VCE1 (1 << 14) 232 233 /* max cursor sizes (in pixels) */ 234 #define CIK_CURSOR_WIDTH 128 235 #define CIK_CURSOR_HEIGHT 128 236 237 struct amdgpu_device; 238 struct amdgpu_ib; 239 struct amdgpu_cs_parser; 240 struct amdgpu_job; 241 struct amdgpu_irq_src; 242 struct amdgpu_fpriv; 243 struct amdgpu_bo_va_mapping; 244 struct amdgpu_atif; 245 struct kfd_vm_fault_info; 246 247 enum amdgpu_cp_irq { 248 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 249 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 250 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 251 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 252 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 253 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 254 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 255 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 256 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 257 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 258 259 AMDGPU_CP_IRQ_LAST 260 }; 261 262 enum amdgpu_thermal_irq { 263 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 264 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 265 266 AMDGPU_THERMAL_IRQ_LAST 267 }; 268 269 enum amdgpu_kiq_irq { 270 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 271 AMDGPU_CP_KIQ_IRQ_LAST 272 }; 273 274 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 275 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 276 #define MAX_KIQ_REG_TRY 80 /* 20 -> 80 */ 277 278 int amdgpu_device_ip_set_clockgating_state(void *dev, 279 enum amd_ip_block_type block_type, 280 enum amd_clockgating_state state); 281 int amdgpu_device_ip_set_powergating_state(void *dev, 282 enum amd_ip_block_type block_type, 283 enum amd_powergating_state state); 284 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 285 u32 *flags); 286 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 287 enum amd_ip_block_type block_type); 288 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 289 enum amd_ip_block_type block_type); 290 291 #define AMDGPU_MAX_IP_NUM 16 292 293 struct amdgpu_ip_block_status { 294 bool valid; 295 bool sw; 296 bool hw; 297 bool late_initialized; 298 bool hang; 299 }; 300 301 struct amdgpu_ip_block_version { 302 const enum amd_ip_block_type type; 303 const u32 major; 304 const u32 minor; 305 const u32 rev; 306 const struct amd_ip_funcs *funcs; 307 }; 308 309 #define HW_REV(_Major, _Minor, _Rev) \ 310 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev))) 311 312 struct amdgpu_ip_block { 313 struct amdgpu_ip_block_status status; 314 const struct amdgpu_ip_block_version *version; 315 }; 316 317 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 318 enum amd_ip_block_type type, 319 u32 major, u32 minor); 320 321 struct amdgpu_ip_block * 322 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 323 enum amd_ip_block_type type); 324 325 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 326 const struct amdgpu_ip_block_version *ip_block_version); 327 328 /* 329 * BIOS. 330 */ 331 bool amdgpu_get_bios(struct amdgpu_device *adev); 332 bool amdgpu_read_bios(struct amdgpu_device *adev); 333 334 /* 335 * Clocks 336 */ 337 338 #define AMDGPU_MAX_PPLL 3 339 340 struct amdgpu_clock { 341 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 342 struct amdgpu_pll spll; 343 struct amdgpu_pll mpll; 344 /* 10 Khz units */ 345 uint32_t default_mclk; 346 uint32_t default_sclk; 347 uint32_t default_dispclk; 348 uint32_t current_dispclk; 349 uint32_t dp_extclk; 350 uint32_t max_pixel_clock; 351 }; 352 353 /* sub-allocation manager, it has to be protected by another lock. 354 * By conception this is an helper for other part of the driver 355 * like the indirect buffer or semaphore, which both have their 356 * locking. 357 * 358 * Principe is simple, we keep a list of sub allocation in offset 359 * order (first entry has offset == 0, last entry has the highest 360 * offset). 361 * 362 * When allocating new object we first check if there is room at 363 * the end total_size - (last_object_offset + last_object_size) >= 364 * alloc_size. If so we allocate new object there. 365 * 366 * When there is not enough room at the end, we start waiting for 367 * each sub object until we reach object_offset+object_size >= 368 * alloc_size, this object then become the sub object we return. 369 * 370 * Alignment can't be bigger than page size. 371 * 372 * Hole are not considered for allocation to keep things simple. 373 * Assumption is that there won't be hole (all object on same 374 * alignment). 375 */ 376 377 #define AMDGPU_SA_NUM_FENCE_LISTS 32 378 379 struct amdgpu_sa_manager { 380 spinlock_t wq_lock; 381 drm_waitqueue_t wq; 382 struct amdgpu_bo *bo; 383 struct list_head *hole; 384 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 385 struct list_head olist; 386 unsigned size; 387 uint64_t gpu_addr; 388 void *cpu_ptr; 389 uint32_t domain; 390 uint32_t align; 391 }; 392 393 /* sub-allocation buffer */ 394 struct amdgpu_sa_bo { 395 struct list_head olist; 396 struct list_head flist; 397 struct amdgpu_sa_manager *manager; 398 unsigned soffset; 399 unsigned eoffset; 400 struct dma_fence *fence; 401 }; 402 403 int amdgpu_fence_slab_init(void); 404 void amdgpu_fence_slab_fini(void); 405 406 /* 407 * IRQS. 408 */ 409 410 struct amdgpu_flip_work { 411 struct delayed_work flip_work; 412 struct work_struct unpin_work; 413 struct amdgpu_device *adev; 414 int crtc_id; 415 u32 target_vblank; 416 uint64_t base; 417 struct drm_pending_vblank_event *event; 418 struct amdgpu_bo *old_abo; 419 struct dma_fence *excl; 420 unsigned shared_count; 421 struct dma_fence **shared; 422 struct dma_fence_cb cb; 423 bool async; 424 }; 425 426 427 /* 428 * CP & rings. 429 */ 430 431 struct amdgpu_ib { 432 struct amdgpu_sa_bo *sa_bo; 433 uint32_t length_dw; 434 uint64_t gpu_addr; 435 uint32_t *ptr; 436 uint32_t flags; 437 }; 438 439 extern const struct drm_sched_backend_ops amdgpu_sched_ops; 440 441 /* 442 * file private structure 443 */ 444 445 struct amdgpu_fpriv { 446 struct amdgpu_vm vm; 447 struct amdgpu_bo_va *prt_va; 448 struct amdgpu_bo_va *csa_va; 449 struct mutex bo_list_lock; 450 struct idr bo_list_handles; 451 struct amdgpu_ctx_mgr ctx_mgr; 452 }; 453 454 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 455 456 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 457 unsigned size, struct amdgpu_ib *ib); 458 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 459 struct dma_fence *f); 460 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 461 struct amdgpu_ib *ibs, struct amdgpu_job *job, 462 struct dma_fence **f); 463 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 464 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 465 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 466 467 /* 468 * CS. 469 */ 470 struct amdgpu_cs_chunk { 471 uint32_t chunk_id; 472 uint32_t length_dw; 473 void *kdata; 474 }; 475 476 struct amdgpu_cs_post_dep { 477 struct drm_syncobj *syncobj; 478 struct dma_fence_chain *chain; 479 u64 point; 480 }; 481 482 struct amdgpu_cs_parser { 483 struct amdgpu_device *adev; 484 struct drm_file *filp; 485 struct amdgpu_ctx *ctx; 486 487 /* chunks */ 488 unsigned nchunks; 489 struct amdgpu_cs_chunk *chunks; 490 491 /* scheduler job object */ 492 struct amdgpu_job *job; 493 struct drm_sched_entity *entity; 494 495 /* buffer objects */ 496 struct ww_acquire_ctx ticket; 497 struct amdgpu_bo_list *bo_list; 498 struct amdgpu_mn *mn; 499 struct amdgpu_bo_list_entry vm_pd; 500 struct list_head validated; 501 struct dma_fence *fence; 502 uint64_t bytes_moved_threshold; 503 uint64_t bytes_moved_vis_threshold; 504 uint64_t bytes_moved; 505 uint64_t bytes_moved_vis; 506 507 /* user fence */ 508 struct amdgpu_bo_list_entry uf_entry; 509 510 unsigned num_post_deps; 511 struct amdgpu_cs_post_dep *post_deps; 512 }; 513 514 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 515 uint32_t ib_idx, int idx) 516 { 517 return p->job->ibs[ib_idx].ptr[idx]; 518 } 519 520 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 521 uint32_t ib_idx, int idx, 522 uint32_t value) 523 { 524 p->job->ibs[ib_idx].ptr[idx] = value; 525 } 526 527 /* 528 * Writeback 529 */ 530 #define AMDGPU_MAX_WB 128 /* Reserve at most 128 WB slots for amdgpu-owned rings. */ 531 532 struct amdgpu_wb { 533 struct amdgpu_bo *wb_obj; 534 volatile uint32_t *wb; 535 uint64_t gpu_addr; 536 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 537 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, NBBY*sizeof(unsigned long))]; 538 }; 539 540 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 541 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 542 543 /* 544 * Benchmarking 545 */ 546 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 547 548 549 /* 550 * Testing 551 */ 552 void amdgpu_test_moves(struct amdgpu_device *adev); 553 554 /* 555 * ASIC specific register table accessible by UMD 556 */ 557 struct amdgpu_allowed_register_entry { 558 uint32_t reg_offset; 559 bool grbm_indexed; 560 }; 561 562 enum amd_reset_method { 563 AMD_RESET_METHOD_LEGACY = 0, 564 AMD_RESET_METHOD_MODE0, 565 AMD_RESET_METHOD_MODE1, 566 AMD_RESET_METHOD_MODE2, 567 AMD_RESET_METHOD_BACO 568 }; 569 570 /* 571 * ASIC specific functions. 572 */ 573 struct amdgpu_asic_funcs { 574 bool (*read_disabled_bios)(struct amdgpu_device *adev); 575 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 576 u8 *bios, u32 length_bytes); 577 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 578 u32 sh_num, u32 reg_offset, u32 *value); 579 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 580 int (*reset)(struct amdgpu_device *adev); 581 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 582 /* get the reference clock */ 583 u32 (*get_xclk)(struct amdgpu_device *adev); 584 /* MM block clocks */ 585 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 586 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 587 /* static power management */ 588 int (*get_pcie_lanes)(struct amdgpu_device *adev); 589 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 590 /* get config memsize register */ 591 u32 (*get_config_memsize)(struct amdgpu_device *adev); 592 /* flush hdp write queue */ 593 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 594 /* invalidate hdp read cache */ 595 void (*invalidate_hdp)(struct amdgpu_device *adev, 596 struct amdgpu_ring *ring); 597 /* check if the asic needs a full reset of if soft reset will work */ 598 bool (*need_full_reset)(struct amdgpu_device *adev); 599 /* initialize doorbell layout for specific asic*/ 600 void (*init_doorbell_index)(struct amdgpu_device *adev); 601 /* PCIe bandwidth usage */ 602 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 603 uint64_t *count1); 604 /* do we need to reset the asic at init time (e.g., kexec) */ 605 bool (*need_reset_on_init)(struct amdgpu_device *adev); 606 /* PCIe replay counter */ 607 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 608 /* device supports BACO */ 609 bool (*supports_baco)(struct amdgpu_device *adev); 610 }; 611 612 /* 613 * IOCTL. 614 */ 615 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 616 struct drm_file *filp); 617 618 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 619 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 620 struct drm_file *filp); 621 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 622 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 623 struct drm_file *filp); 624 625 /* VRAM scratch page for HDP bug, default vram page */ 626 struct amdgpu_vram_scratch { 627 struct amdgpu_bo *robj; 628 volatile uint32_t *ptr; 629 u64 gpu_addr; 630 }; 631 632 /* 633 * ACPI 634 */ 635 struct amdgpu_atcs_functions { 636 bool get_ext_state; 637 bool pcie_perf_req; 638 bool pcie_dev_rdy; 639 bool pcie_bus_width; 640 }; 641 642 struct amdgpu_atcs { 643 struct amdgpu_atcs_functions functions; 644 }; 645 646 /* 647 * Firmware VRAM reservation 648 */ 649 struct amdgpu_fw_vram_usage { 650 u64 start_offset; 651 u64 size; 652 struct amdgpu_bo *reserved_bo; 653 void *va; 654 655 /* GDDR6 training support flag. 656 */ 657 bool mem_train_support; 658 }; 659 660 /* 661 * CGS 662 */ 663 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 664 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 665 666 /* 667 * Core structure, functions and helpers. 668 */ 669 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 670 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 671 672 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 673 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 674 675 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 676 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 677 678 struct amdgpu_mmio_remap { 679 u32 reg_offset; 680 resource_size_t bus_addr; 681 }; 682 683 /* Define the HW IP blocks will be used in driver , add more if necessary */ 684 enum amd_hw_ip_block_type { 685 GC_HWIP = 1, 686 HDP_HWIP, 687 SDMA0_HWIP, 688 SDMA1_HWIP, 689 SDMA2_HWIP, 690 SDMA3_HWIP, 691 SDMA4_HWIP, 692 SDMA5_HWIP, 693 SDMA6_HWIP, 694 SDMA7_HWIP, 695 MMHUB_HWIP, 696 ATHUB_HWIP, 697 NBIO_HWIP, 698 MP0_HWIP, 699 MP1_HWIP, 700 UVD_HWIP, 701 VCN_HWIP = UVD_HWIP, 702 JPEG_HWIP = VCN_HWIP, 703 VCE_HWIP, 704 DF_HWIP, 705 DCE_HWIP, 706 OSSSYS_HWIP, 707 SMUIO_HWIP, 708 PWR_HWIP, 709 NBIF_HWIP, 710 THM_HWIP, 711 CLK_HWIP, 712 UMC_HWIP, 713 RSMU_HWIP, 714 MAX_HWIP 715 }; 716 717 #define HWIP_MAX_INSTANCE 8 718 719 struct amd_powerplay { 720 void *pp_handle; 721 const struct amd_pm_funcs *pp_funcs; 722 }; 723 724 #define AMDGPU_RESET_MAGIC_NUM 64 725 #define AMDGPU_MAX_DF_PERFMONS 4 726 struct amdgpu_device { 727 struct device *dev; 728 struct drm_device *ddev; 729 struct pci_dev *pdev; 730 731 #ifdef CONFIG_DRM_AMD_ACP 732 struct amdgpu_acp acp; 733 #endif 734 735 /* ASIC */ 736 enum amd_asic_type asic_type; 737 uint32_t family; 738 uint32_t rev_id; 739 uint32_t external_rev_id; 740 unsigned long flags; 741 int usec_timeout; 742 const struct amdgpu_asic_funcs *asic_funcs; 743 bool shutdown; 744 bool need_swiotlb; 745 bool accel_working; 746 struct notifier_block acpi_nb; 747 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 748 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 749 unsigned debugfs_count; 750 #if defined(CONFIG_DEBUG_FS) 751 struct dentry *debugfs_preempt; 752 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 753 #endif 754 struct amdgpu_atif *atif; 755 struct amdgpu_atcs atcs; 756 struct mutex srbm_mutex; 757 /* GRBM index mutex. Protects concurrent access to GRBM index */ 758 struct mutex grbm_idx_mutex; 759 struct dev_pm_domain vga_pm_domain; 760 bool have_disp_power_ref; 761 bool have_atomics_support; 762 763 /* BIOS */ 764 bool is_atom_fw; 765 uint8_t *bios; 766 uint32_t bios_size; 767 struct amdgpu_bo *stolen_vga_memory; 768 struct amdgpu_bo *discovery_memory; 769 uint32_t bios_scratch_reg_offset; 770 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 771 772 /* Register/doorbell mmio */ 773 #ifdef __NetBSD__ 774 bus_space_tag_t rmmiot; 775 bus_space_handle_t rmmioh; 776 bus_addr_t rmmio_base; 777 bus_size_t rmmio_size; 778 #else 779 resource_size_t rmmio_base; 780 resource_size_t rmmio_size; 781 void __iomem *rmmio; 782 #endif 783 /* protects concurrent MM_INDEX/DATA based register access */ 784 spinlock_t mmio_idx_lock; 785 struct amdgpu_mmio_remap rmmio_remap; 786 /* protects concurrent SMC based register access */ 787 spinlock_t smc_idx_lock; 788 amdgpu_rreg_t smc_rreg; 789 amdgpu_wreg_t smc_wreg; 790 /* protects concurrent PCIE register access */ 791 spinlock_t pcie_idx_lock; 792 amdgpu_rreg_t pcie_rreg; 793 amdgpu_wreg_t pcie_wreg; 794 amdgpu_rreg_t pciep_rreg; 795 amdgpu_wreg_t pciep_wreg; 796 amdgpu_rreg64_t pcie_rreg64; 797 amdgpu_wreg64_t pcie_wreg64; 798 /* protects concurrent UVD register access */ 799 spinlock_t uvd_ctx_idx_lock; 800 amdgpu_rreg_t uvd_ctx_rreg; 801 amdgpu_wreg_t uvd_ctx_wreg; 802 /* protects concurrent DIDT register access */ 803 spinlock_t didt_idx_lock; 804 amdgpu_rreg_t didt_rreg; 805 amdgpu_wreg_t didt_wreg; 806 /* protects concurrent gc_cac register access */ 807 spinlock_t gc_cac_idx_lock; 808 amdgpu_rreg_t gc_cac_rreg; 809 amdgpu_wreg_t gc_cac_wreg; 810 /* protects concurrent se_cac register access */ 811 spinlock_t se_cac_idx_lock; 812 amdgpu_rreg_t se_cac_rreg; 813 amdgpu_wreg_t se_cac_wreg; 814 /* protects concurrent ENDPOINT (audio) register access */ 815 spinlock_t audio_endpt_idx_lock; 816 amdgpu_block_rreg_t audio_endpt_rreg; 817 amdgpu_block_wreg_t audio_endpt_wreg; 818 #ifdef __NetBSD__ 819 bus_space_tag_t rio_memt; 820 bus_space_handle_t rio_memh; 821 bus_size_t rio_mem_size; 822 #else 823 void __iomem *rio_mem; 824 resource_size_t rio_mem_size; 825 #endif 826 struct amdgpu_doorbell doorbell; 827 828 /* clock/pll info */ 829 struct amdgpu_clock clock; 830 831 /* MC */ 832 struct amdgpu_gmc gmc; 833 struct amdgpu_gart gart; 834 #ifdef __NetBSD__ 835 bus_dma_segment_t dummy_page_seg; 836 bus_dmamap_t dummy_page_map; 837 #endif 838 dma_addr_t dummy_page_addr; 839 struct amdgpu_vm_manager vm_manager; 840 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 841 unsigned num_vmhubs; 842 843 /* memory management */ 844 struct amdgpu_mman mman; 845 struct amdgpu_vram_scratch vram_scratch; 846 struct amdgpu_wb wb; 847 atomic64_t num_bytes_moved; 848 atomic64_t num_evictions; 849 atomic64_t num_vram_cpu_page_faults; 850 atomic_t gpu_reset_counter; 851 atomic_t vram_lost_counter; 852 853 /* data for buffer migration throttling */ 854 struct { 855 spinlock_t lock; 856 s64 last_update_us; 857 s64 accum_us; /* accumulated microseconds */ 858 s64 accum_us_vis; /* for visible VRAM */ 859 u32 log2_max_MBps; 860 } mm_stats; 861 862 /* display */ 863 bool enable_virtual_display; 864 struct amdgpu_mode_info mode_info; 865 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 866 struct work_struct hotplug_work; 867 struct amdgpu_irq_src crtc_irq; 868 struct amdgpu_irq_src vupdate_irq; 869 struct amdgpu_irq_src pageflip_irq; 870 struct amdgpu_irq_src hpd_irq; 871 872 /* rings */ 873 u64 fence_context; 874 unsigned num_rings; 875 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 876 bool ib_pool_ready; 877 struct amdgpu_sa_manager ring_tmp_bo; 878 879 /* interrupts */ 880 struct amdgpu_irq irq; 881 882 /* powerplay */ 883 struct amd_powerplay powerplay; 884 bool pp_force_state_enabled; 885 886 /* smu */ 887 struct smu_context smu; 888 889 /* dpm */ 890 struct amdgpu_pm pm; 891 u32 cg_flags; 892 u32 pg_flags; 893 894 /* nbio */ 895 struct amdgpu_nbio nbio; 896 897 /* mmhub */ 898 struct amdgpu_mmhub mmhub; 899 900 /* gfx */ 901 struct amdgpu_gfx gfx; 902 903 /* sdma */ 904 struct amdgpu_sdma sdma; 905 906 /* uvd */ 907 struct amdgpu_uvd uvd; 908 909 /* vce */ 910 struct amdgpu_vce vce; 911 912 /* vcn */ 913 struct amdgpu_vcn vcn; 914 915 /* jpeg */ 916 struct amdgpu_jpeg jpeg; 917 918 /* firmwares */ 919 struct amdgpu_firmware firmware; 920 921 /* PSP */ 922 struct psp_context psp; 923 924 /* GDS */ 925 struct amdgpu_gds gds; 926 927 /* KFD */ 928 struct amdgpu_kfd_dev kfd; 929 930 /* UMC */ 931 struct amdgpu_umc umc; 932 933 /* display related functionality */ 934 struct amdgpu_display_manager dm; 935 936 /* discovery */ 937 uint8_t *discovery; 938 939 /* mes */ 940 bool enable_mes; 941 struct amdgpu_mes mes; 942 943 /* df */ 944 struct amdgpu_df df; 945 946 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 947 int num_ip_blocks; 948 struct mutex mn_lock; 949 DECLARE_HASHTABLE(mn_hash, 7); 950 951 /* tracking pinned memory */ 952 atomic64_t vram_pin_size; 953 atomic64_t visible_pin_size; 954 atomic64_t gart_pin_size; 955 956 /* soc15 register offset based on ip, instance and segment */ 957 const uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 958 959 /* delayed work_func for deferring clockgating during resume */ 960 struct delayed_work delayed_init_work; 961 962 struct amdgpu_virt virt; 963 /* firmware VRAM reservation */ 964 struct amdgpu_fw_vram_usage fw_vram_usage; 965 966 /* link all shadow bo */ 967 struct list_head shadow_list; 968 struct mutex shadow_list_lock; 969 /* keep an lru list of rings by HW IP */ 970 struct list_head ring_lru_list; 971 spinlock_t ring_lru_list_lock; 972 973 /* record hw reset is performed */ 974 bool has_hw_reset; 975 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 976 977 /* s3/s4 mask */ 978 bool in_suspend; 979 980 /* record last mm index being written through WREG32*/ 981 unsigned long last_mm_index; 982 bool in_gpu_reset; 983 enum pp_mp1_state mp1_state; 984 struct mutex lock_reset; 985 struct amdgpu_doorbell_index doorbell_index; 986 987 struct mutex notifier_lock; 988 989 int asic_reset_res; 990 struct work_struct xgmi_reset_work; 991 992 long gfx_timeout; 993 long sdma_timeout; 994 long video_timeout; 995 long compute_timeout; 996 997 uint64_t unique_id; 998 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 999 1000 /* device pstate */ 1001 int pstate; 1002 /* enable runtime pm on the device */ 1003 bool runpm; 1004 1005 bool pm_sysfs_en; 1006 bool ucode_sysfs_en; 1007 }; 1008 1009 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) 1010 { 1011 return container_of(bdev, struct amdgpu_device, mman.bdev); 1012 } 1013 1014 int amdgpu_device_init(struct amdgpu_device *adev, 1015 struct drm_device *ddev, 1016 struct pci_dev *pdev, 1017 uint32_t flags); 1018 void amdgpu_device_fini(struct amdgpu_device *adev); 1019 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1020 1021 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1022 uint32_t *buf, size_t size, bool write); 1023 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 1024 uint32_t acc_flags); 1025 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 1026 uint32_t acc_flags); 1027 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1028 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1029 1030 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 1031 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 1032 1033 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1034 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1035 1036 int emu_soc_asic_init(struct amdgpu_device *adev); 1037 1038 /* 1039 * Registers read & write functions. 1040 */ 1041 1042 #define AMDGPU_REGS_IDX (1<<0) 1043 #define AMDGPU_REGS_NO_KIQ (1<<1) 1044 #define AMDGPU_REGS_KIQ (1<<2) 1045 1046 #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1047 #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1048 1049 #define RREG32_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_KIQ) 1050 #define WREG32_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_KIQ) 1051 1052 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1053 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1054 1055 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0) 1056 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX) 1057 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0)) 1058 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0) 1059 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX) 1060 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1061 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1062 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1063 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1064 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1065 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1066 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1067 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1068 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1069 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1070 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1071 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1072 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1073 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1074 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1075 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1076 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1077 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1078 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1079 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1080 #define WREG32_P(reg, val, mask) \ 1081 do { \ 1082 uint32_t tmp_ = RREG32(reg); \ 1083 tmp_ &= (mask); \ 1084 tmp_ |= ((val) & ~(mask)); \ 1085 WREG32(reg, tmp_); \ 1086 } while (0) 1087 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1088 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1089 #define WREG32_PLL_P(reg, val, mask) \ 1090 do { \ 1091 uint32_t tmp_ = RREG32_PLL(reg); \ 1092 tmp_ &= (mask); \ 1093 tmp_ |= ((val) & ~(mask)); \ 1094 WREG32_PLL(reg, tmp_); \ 1095 } while (0) 1096 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 1097 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 1098 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 1099 1100 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1101 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1102 1103 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1104 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1105 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1106 1107 #define REG_GET_FIELD(value, reg, field) \ 1108 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1109 1110 #define WREG32_FIELD(reg, field, val) \ 1111 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1112 1113 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1114 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1115 1116 /* 1117 * BIOS helpers. 1118 */ 1119 #define RBIOS8(i) (adev->bios[i]) 1120 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1121 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1122 1123 /* 1124 * ASICs macro. 1125 */ 1126 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1127 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1128 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1129 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1130 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1131 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1132 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1133 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1134 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1135 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1136 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1137 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1138 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1139 #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r)) 1140 #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r)) 1141 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1142 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1143 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1144 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1145 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1146 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1147 1148 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); 1149 1150 /* Common functions */ 1151 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1152 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1153 struct amdgpu_job* job); 1154 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1155 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1156 1157 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1158 u64 num_vis_bytes); 1159 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1160 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1161 const u32 *registers, 1162 const u32 array_size); 1163 int amdgpu_ttm_init(struct amdgpu_device *adev); 1164 void amdgpu_ttm_fini(struct amdgpu_device *adev); 1165 1166 bool amdgpu_device_supports_boco(struct drm_device *dev); 1167 bool amdgpu_device_supports_baco(struct drm_device *dev); 1168 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1169 struct amdgpu_device *peer_adev); 1170 int amdgpu_device_baco_enter(struct drm_device *dev); 1171 int amdgpu_device_baco_exit(struct drm_device *dev); 1172 1173 /* atpx handler */ 1174 #if defined(CONFIG_VGA_SWITCHEROO) 1175 void amdgpu_register_atpx_handler(void); 1176 void amdgpu_unregister_atpx_handler(void); 1177 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1178 bool amdgpu_is_atpx_hybrid(void); 1179 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1180 bool amdgpu_has_atpx(void); 1181 #else 1182 static inline void amdgpu_register_atpx_handler(void) {} 1183 static inline void amdgpu_unregister_atpx_handler(void) {} 1184 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1185 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1186 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1187 static inline bool amdgpu_has_atpx(void) { return false; } 1188 #endif 1189 1190 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1191 void *amdgpu_atpx_get_dhandle(void); 1192 #else 1193 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1194 #endif 1195 1196 /* 1197 * KMS 1198 */ 1199 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1200 extern const int amdgpu_max_kms_ioctl; 1201 1202 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 1203 void amdgpu_driver_unload_kms(struct drm_device *dev); 1204 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1205 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1206 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1207 struct drm_file *file_priv); 1208 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1209 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1210 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1211 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 1212 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1213 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1214 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 1215 unsigned long arg); 1216 1217 /* 1218 * functions used by amdgpu_encoder.c 1219 */ 1220 struct amdgpu_afmt_acr { 1221 u32 clock; 1222 1223 int n_32khz; 1224 int cts_32khz; 1225 1226 int n_44_1khz; 1227 int cts_44_1khz; 1228 1229 int n_48khz; 1230 int cts_48khz; 1231 1232 }; 1233 1234 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1235 1236 /* amdgpu_acpi.c */ 1237 #if defined(CONFIG_ACPI) 1238 int amdgpu_acpi_init(struct amdgpu_device *adev); 1239 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1240 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1241 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1242 u8 perf_req, bool advertise); 1243 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1244 1245 void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev, 1246 struct amdgpu_dm_backlight_caps *caps); 1247 #else 1248 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1249 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1250 #endif 1251 1252 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 1253 uint64_t addr, struct amdgpu_bo **bo, 1254 struct amdgpu_bo_va_mapping **mapping); 1255 1256 #if defined(CONFIG_DRM_AMD_DC) 1257 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1258 #else 1259 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1260 #endif 1261 1262 1263 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1264 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1265 1266 #include "amdgpu_object.h" 1267 1268 #ifdef __NetBSD__ /* XXX amdgpu sysfs */ 1269 #define AMDGPU_PMU_ATTR(_name, _object) CTASSERT(1) 1270 #else 1271 /* used by df_v3_6.c and amdgpu_pmu.c */ 1272 #define AMDGPU_PMU_ATTR(_name, _object) \ 1273 static ssize_t \ 1274 _name##_show(struct device *dev, \ 1275 struct device_attribute *attr, \ 1276 char *page) \ 1277 { \ 1278 BUILD_BUG_ON(sizeof(_object) >= PAGE_SIZE - 1); \ 1279 return sprintf(page, _object "\n"); \ 1280 } \ 1281 \ 1282 static struct device_attribute pmu_attr_##_name = __ATTR_RO(_name) 1283 #endif 1284 1285 #endif 1286 1287
Indexes created Sun Sep 21 20:09:37 GMT 2025