1 /* $NetBSD: amdgpu_mode.h,v 1.3 2021/12/18 23:44:58 riastradh Exp $ */ 2 3 /* 4 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 5 * VA Linux Systems Inc., Fremont, California. 6 * Copyright 2008 Red Hat Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Original Authors: 27 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane 28 * 29 * Kernel port Author: Dave Airlie 30 */ 31 32 #ifndef AMDGPU_MODE_H 33 #define AMDGPU_MODE_H 34 35 #include <drm/drm_crtc.h> 36 #include <drm/drm_edid.h> 37 #include <drm/drm_encoder.h> 38 #include <drm/drm_dp_helper.h> 39 #include <drm/drm_fixed.h> 40 #include <drm/drm_crtc_helper.h> 41 #include <drm/drm_fb_helper.h> 42 #include <drm/drm_plane_helper.h> 43 #include <drm/drm_probe_helper.h> 44 #include <linux/i2c.h> 45 #include <linux/i2c-algo-bit.h> 46 #include <linux/hrtimer.h> 47 #include "amdgpu_irq.h" 48 49 #include <drm/drm_dp_mst_helper.h> 50 #include "modules/inc/mod_freesync.h" 51 52 struct amdgpu_bo; 53 struct amdgpu_device; 54 struct amdgpu_encoder; 55 struct amdgpu_router; 56 struct amdgpu_hpd; 57 58 #define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base) 59 #define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base) 60 #define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base) 61 #define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base) 62 63 #define to_dm_plane_state(x) container_of(x, struct dm_plane_state, base) 64 65 #define AMDGPU_MAX_HPD_PINS 6 66 #define AMDGPU_MAX_CRTCS 6 67 #define AMDGPU_MAX_PLANES 6 68 #define AMDGPU_MAX_AFMT_BLOCKS 9 69 70 enum amdgpu_rmx_type { 71 RMX_OFF, 72 RMX_FULL, 73 RMX_CENTER, 74 RMX_ASPECT 75 }; 76 77 enum amdgpu_underscan_type { 78 UNDERSCAN_OFF, 79 UNDERSCAN_ON, 80 UNDERSCAN_AUTO, 81 }; 82 83 #define AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS 50 84 #define AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS 10 85 86 enum amdgpu_hpd_id { 87 AMDGPU_HPD_1 = 0, 88 AMDGPU_HPD_2, 89 AMDGPU_HPD_3, 90 AMDGPU_HPD_4, 91 AMDGPU_HPD_5, 92 AMDGPU_HPD_6, 93 AMDGPU_HPD_NONE = 0xff, 94 }; 95 96 enum amdgpu_crtc_irq { 97 AMDGPU_CRTC_IRQ_VBLANK1 = 0, 98 AMDGPU_CRTC_IRQ_VBLANK2, 99 AMDGPU_CRTC_IRQ_VBLANK3, 100 AMDGPU_CRTC_IRQ_VBLANK4, 101 AMDGPU_CRTC_IRQ_VBLANK5, 102 AMDGPU_CRTC_IRQ_VBLANK6, 103 AMDGPU_CRTC_IRQ_VLINE1, 104 AMDGPU_CRTC_IRQ_VLINE2, 105 AMDGPU_CRTC_IRQ_VLINE3, 106 AMDGPU_CRTC_IRQ_VLINE4, 107 AMDGPU_CRTC_IRQ_VLINE5, 108 AMDGPU_CRTC_IRQ_VLINE6, 109 AMDGPU_CRTC_IRQ_NONE = 0xff 110 }; 111 112 enum amdgpu_pageflip_irq { 113 AMDGPU_PAGEFLIP_IRQ_D1 = 0, 114 AMDGPU_PAGEFLIP_IRQ_D2, 115 AMDGPU_PAGEFLIP_IRQ_D3, 116 AMDGPU_PAGEFLIP_IRQ_D4, 117 AMDGPU_PAGEFLIP_IRQ_D5, 118 AMDGPU_PAGEFLIP_IRQ_D6, 119 AMDGPU_PAGEFLIP_IRQ_NONE = 0xff 120 }; 121 122 enum amdgpu_flip_status { 123 AMDGPU_FLIP_NONE, 124 AMDGPU_FLIP_PENDING, 125 AMDGPU_FLIP_SUBMITTED 126 }; 127 128 #define AMDGPU_MAX_I2C_BUS 16 129 130 /* amdgpu gpio-based i2c 131 * 1. "mask" reg and bits 132 * grabs the gpio pins for software use 133 * 0=not held 1=held 134 * 2. "a" reg and bits 135 * output pin value 136 * 0=low 1=high 137 * 3. "en" reg and bits 138 * sets the pin direction 139 * 0=input 1=output 140 * 4. "y" reg and bits 141 * input pin value 142 * 0=low 1=high 143 */ 144 struct amdgpu_i2c_bus_rec { 145 bool valid; 146 /* id used by atom */ 147 uint8_t i2c_id; 148 /* id used by atom */ 149 enum amdgpu_hpd_id hpd; 150 /* can be used with hw i2c engine */ 151 bool hw_capable; 152 /* uses multi-media i2c engine */ 153 bool mm_i2c; 154 /* regs and bits */ 155 uint32_t mask_clk_reg; 156 uint32_t mask_data_reg; 157 uint32_t a_clk_reg; 158 uint32_t a_data_reg; 159 uint32_t en_clk_reg; 160 uint32_t en_data_reg; 161 uint32_t y_clk_reg; 162 uint32_t y_data_reg; 163 uint32_t mask_clk_mask; 164 uint32_t mask_data_mask; 165 uint32_t a_clk_mask; 166 uint32_t a_data_mask; 167 uint32_t en_clk_mask; 168 uint32_t en_data_mask; 169 uint32_t y_clk_mask; 170 uint32_t y_data_mask; 171 }; 172 173 #define AMDGPU_MAX_BIOS_CONNECTOR 16 174 175 /* pll flags */ 176 #define AMDGPU_PLL_USE_BIOS_DIVS (1 << 0) 177 #define AMDGPU_PLL_NO_ODD_POST_DIV (1 << 1) 178 #define AMDGPU_PLL_USE_REF_DIV (1 << 2) 179 #define AMDGPU_PLL_LEGACY (1 << 3) 180 #define AMDGPU_PLL_PREFER_LOW_REF_DIV (1 << 4) 181 #define AMDGPU_PLL_PREFER_HIGH_REF_DIV (1 << 5) 182 #define AMDGPU_PLL_PREFER_LOW_FB_DIV (1 << 6) 183 #define AMDGPU_PLL_PREFER_HIGH_FB_DIV (1 << 7) 184 #define AMDGPU_PLL_PREFER_LOW_POST_DIV (1 << 8) 185 #define AMDGPU_PLL_PREFER_HIGH_POST_DIV (1 << 9) 186 #define AMDGPU_PLL_USE_FRAC_FB_DIV (1 << 10) 187 #define AMDGPU_PLL_PREFER_CLOSEST_LOWER (1 << 11) 188 #define AMDGPU_PLL_USE_POST_DIV (1 << 12) 189 #define AMDGPU_PLL_IS_LCD (1 << 13) 190 #define AMDGPU_PLL_PREFER_MINM_OVER_MAXP (1 << 14) 191 192 struct amdgpu_pll { 193 /* reference frequency */ 194 uint32_t reference_freq; 195 196 /* fixed dividers */ 197 uint32_t reference_div; 198 uint32_t post_div; 199 200 /* pll in/out limits */ 201 uint32_t pll_in_min; 202 uint32_t pll_in_max; 203 uint32_t pll_out_min; 204 uint32_t pll_out_max; 205 uint32_t lcd_pll_out_min; 206 uint32_t lcd_pll_out_max; 207 uint32_t best_vco; 208 209 /* divider limits */ 210 uint32_t min_ref_div; 211 uint32_t max_ref_div; 212 uint32_t min_post_div; 213 uint32_t max_post_div; 214 uint32_t min_feedback_div; 215 uint32_t max_feedback_div; 216 uint32_t min_frac_feedback_div; 217 uint32_t max_frac_feedback_div; 218 219 /* flags for the current clock */ 220 uint32_t flags; 221 222 /* pll id */ 223 uint32_t id; 224 }; 225 226 struct amdgpu_i2c_chan { 227 struct i2c_adapter adapter; 228 struct drm_device *dev; 229 struct i2c_algo_bit_data bit; 230 struct amdgpu_i2c_bus_rec rec; 231 struct drm_dp_aux aux; 232 bool has_aux; 233 struct mutex mutex; 234 }; 235 236 struct amdgpu_fbdev; 237 238 struct amdgpu_afmt { 239 bool enabled; 240 int offset; 241 bool last_buffer_filled_status; 242 int id; 243 struct amdgpu_audio_pin *pin; 244 }; 245 246 /* 247 * Audio 248 */ 249 struct amdgpu_audio_pin { 250 int channels; 251 int rate; 252 int bits_per_sample; 253 u8 status_bits; 254 u8 category_code; 255 u32 offset; 256 bool connected; 257 u32 id; 258 }; 259 260 struct amdgpu_audio { 261 bool enabled; 262 struct amdgpu_audio_pin pin[AMDGPU_MAX_AFMT_BLOCKS]; 263 int num_pins; 264 }; 265 266 struct amdgpu_display_funcs { 267 /* display watermarks */ 268 void (*bandwidth_update)(struct amdgpu_device *adev); 269 /* get frame count */ 270 u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc); 271 /* set backlight level */ 272 void (*backlight_set_level)(struct amdgpu_encoder *amdgpu_encoder, 273 u8 level); 274 /* get backlight level */ 275 u8 (*backlight_get_level)(struct amdgpu_encoder *amdgpu_encoder); 276 /* hotplug detect */ 277 bool (*hpd_sense)(struct amdgpu_device *adev, enum amdgpu_hpd_id hpd); 278 void (*hpd_set_polarity)(struct amdgpu_device *adev, 279 enum amdgpu_hpd_id hpd); 280 u32 (*hpd_get_gpio_reg)(struct amdgpu_device *adev); 281 /* pageflipping */ 282 void (*page_flip)(struct amdgpu_device *adev, 283 int crtc_id, u64 crtc_base, bool async); 284 int (*page_flip_get_scanoutpos)(struct amdgpu_device *adev, int crtc, 285 u32 *vbl, u32 *position); 286 /* display topology setup */ 287 void (*add_encoder)(struct amdgpu_device *adev, 288 uint32_t encoder_enum, 289 uint32_t supported_device, 290 u16 caps); 291 void (*add_connector)(struct amdgpu_device *adev, 292 uint32_t connector_id, 293 uint32_t supported_device, 294 int connector_type, 295 struct amdgpu_i2c_bus_rec *i2c_bus, 296 uint16_t connector_object_id, 297 struct amdgpu_hpd *hpd, 298 struct amdgpu_router *router); 299 300 301 }; 302 303 struct amdgpu_framebuffer { 304 struct drm_framebuffer base; 305 306 /* caching for later use */ 307 uint64_t address; 308 }; 309 310 struct amdgpu_fbdev { 311 struct drm_fb_helper helper; 312 struct amdgpu_framebuffer rfb; 313 struct list_head fbdev_list; 314 struct amdgpu_device *adev; 315 }; 316 317 struct amdgpu_mode_info { 318 struct atom_context *atom_context; 319 struct card_info *atom_card_info; 320 bool mode_config_initialized; 321 struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS]; 322 struct drm_plane *planes[AMDGPU_MAX_PLANES]; 323 struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS]; 324 /* DVI-I properties */ 325 struct drm_property *coherent_mode_property; 326 /* DAC enable load detect */ 327 struct drm_property *load_detect_property; 328 /* underscan */ 329 struct drm_property *underscan_property; 330 struct drm_property *underscan_hborder_property; 331 struct drm_property *underscan_vborder_property; 332 /* audio */ 333 struct drm_property *audio_property; 334 /* FMT dithering */ 335 struct drm_property *dither_property; 336 /* Adaptive Backlight Modulation (power feature) */ 337 struct drm_property *abm_level_property; 338 /* hardcoded DFP edid from BIOS */ 339 struct edid *bios_hardcoded_edid; 340 int bios_hardcoded_edid_size; 341 342 /* pointer to fbdev info structure */ 343 struct amdgpu_fbdev *rfbdev; 344 /* firmware flags */ 345 u16 firmware_flags; 346 /* pointer to backlight encoder */ 347 struct amdgpu_encoder *bl_encoder; 348 u8 bl_level; /* saved backlight level */ 349 struct amdgpu_audio audio; /* audio stuff */ 350 int num_crtc; /* number of crtcs */ 351 int num_hpd; /* number of hpd pins */ 352 int num_dig; /* number of dig blocks */ 353 int disp_priority; 354 const struct amdgpu_display_funcs *funcs; 355 const enum drm_plane_type *plane_type; 356 }; 357 358 #define AMDGPU_MAX_BL_LEVEL 0xFF 359 360 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 361 362 struct amdgpu_backlight_privdata { 363 struct amdgpu_encoder *encoder; 364 uint8_t negative; 365 }; 366 367 #endif 368 369 struct amdgpu_atom_ss { 370 uint16_t percentage; 371 uint16_t percentage_divider; 372 uint8_t type; 373 uint16_t step; 374 uint8_t delay; 375 uint8_t range; 376 uint8_t refdiv; 377 /* asic_ss */ 378 uint16_t rate; 379 uint16_t amount; 380 }; 381 382 struct amdgpu_crtc { 383 struct drm_crtc base; 384 int crtc_id; 385 bool enabled; 386 bool can_tile; 387 uint32_t crtc_offset; 388 struct drm_gem_object *cursor_bo; 389 uint64_t cursor_addr; 390 int cursor_x; 391 int cursor_y; 392 int cursor_hot_x; 393 int cursor_hot_y; 394 int cursor_width; 395 int cursor_height; 396 int max_cursor_width; 397 int max_cursor_height; 398 enum amdgpu_rmx_type rmx_type; 399 u8 h_border; 400 u8 v_border; 401 fixed20_12 vsc; 402 fixed20_12 hsc; 403 struct drm_display_mode native_mode; 404 u32 pll_id; 405 /* page flipping */ 406 struct amdgpu_flip_work *pflip_works; 407 enum amdgpu_flip_status pflip_status; 408 int deferred_flip_completion; 409 u32 last_flip_vblank; 410 /* pll sharing */ 411 struct amdgpu_atom_ss ss; 412 bool ss_enabled; 413 u32 adjusted_clock; 414 int bpc; 415 u32 pll_reference_div; 416 u32 pll_post_div; 417 u32 pll_flags; 418 struct drm_encoder *encoder; 419 struct drm_connector *connector; 420 /* for dpm */ 421 u32 line_time; 422 u32 wm_low; 423 u32 wm_high; 424 u32 lb_vblank_lead_lines; 425 struct drm_display_mode hw_mode; 426 /* for virtual dce */ 427 struct hrtimer vblank_timer; 428 enum amdgpu_interrupt_state vsync_timer_enabled; 429 430 int otg_inst; 431 struct drm_pending_vblank_event *event; 432 }; 433 434 struct amdgpu_encoder_atom_dig { 435 bool linkb; 436 /* atom dig */ 437 bool coherent_mode; 438 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ 439 /* atom lvds/edp */ 440 uint32_t lcd_misc; 441 uint16_t panel_pwr_delay; 442 uint32_t lcd_ss_id; 443 /* panel mode */ 444 struct drm_display_mode native_mode; 445 struct backlight_device *bl_dev; 446 int dpms_mode; 447 uint8_t backlight_level; 448 int panel_mode; 449 struct amdgpu_afmt *afmt; 450 }; 451 452 struct amdgpu_encoder { 453 struct drm_encoder base; 454 uint32_t encoder_enum; 455 uint32_t encoder_id; 456 uint32_t devices; 457 uint32_t active_device; 458 uint32_t flags; 459 uint32_t pixel_clock; 460 enum amdgpu_rmx_type rmx_type; 461 enum amdgpu_underscan_type underscan_type; 462 uint32_t underscan_hborder; 463 uint32_t underscan_vborder; 464 struct drm_display_mode native_mode; 465 void *enc_priv; 466 int audio_polling_active; 467 bool is_ext_encoder; 468 u16 caps; 469 }; 470 471 struct amdgpu_connector_atom_dig { 472 /* displayport */ 473 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 474 u8 dp_sink_type; 475 int dp_clock; 476 int dp_lane_count; 477 bool edp_on; 478 }; 479 480 struct amdgpu_gpio_rec { 481 bool valid; 482 u8 id; 483 u32 reg; 484 u32 mask; 485 u32 shift; 486 }; 487 488 struct amdgpu_hpd { 489 enum amdgpu_hpd_id hpd; 490 u8 plugged_state; 491 struct amdgpu_gpio_rec gpio; 492 }; 493 494 struct amdgpu_router { 495 u32 router_id; 496 struct amdgpu_i2c_bus_rec i2c_info; 497 u8 i2c_addr; 498 /* i2c mux */ 499 bool ddc_valid; 500 u8 ddc_mux_type; 501 u8 ddc_mux_control_pin; 502 u8 ddc_mux_state; 503 /* clock/data mux */ 504 bool cd_valid; 505 u8 cd_mux_type; 506 u8 cd_mux_control_pin; 507 u8 cd_mux_state; 508 }; 509 510 enum amdgpu_connector_audio { 511 AMDGPU_AUDIO_DISABLE = 0, 512 AMDGPU_AUDIO_ENABLE = 1, 513 AMDGPU_AUDIO_AUTO = 2 514 }; 515 516 enum amdgpu_connector_dither { 517 AMDGPU_FMT_DITHER_DISABLE = 0, 518 AMDGPU_FMT_DITHER_ENABLE = 1, 519 }; 520 521 struct amdgpu_dm_dp_aux { 522 struct drm_dp_aux aux; 523 struct ddc_service *ddc_service; 524 }; 525 526 struct amdgpu_i2c_adapter { 527 struct i2c_adapter base; 528 529 struct ddc_service *ddc_service; 530 }; 531 532 #define TO_DM_AUX(x) container_of((x), struct amdgpu_dm_dp_aux, aux) 533 534 struct amdgpu_connector { 535 struct drm_connector base; 536 uint32_t connector_id; 537 uint32_t devices; 538 struct amdgpu_i2c_chan *ddc_bus; 539 /* some systems have an hdmi and vga port with a shared ddc line */ 540 bool shared_ddc; 541 bool use_digital; 542 /* we need to mind the EDID between detect 543 and get modes due to analog/digital/tvencoder */ 544 struct edid *edid; 545 void *con_priv; 546 bool dac_load_detect; 547 bool detected_by_load; /* if the connection status was determined by load */ 548 uint16_t connector_object_id; 549 struct amdgpu_hpd hpd; 550 struct amdgpu_router router; 551 struct amdgpu_i2c_chan *router_bus; 552 enum amdgpu_connector_audio audio; 553 enum amdgpu_connector_dither dither; 554 unsigned pixelclock_for_modeset; 555 }; 556 557 /* TODO: start to use this struct and remove same field from base one */ 558 struct amdgpu_mst_connector { 559 struct amdgpu_connector base; 560 561 struct drm_dp_mst_topology_mgr mst_mgr; 562 struct amdgpu_dm_dp_aux dm_dp_aux; 563 struct drm_dp_mst_port *port; 564 struct amdgpu_connector *mst_port; 565 bool is_mst_connector; 566 struct amdgpu_encoder *mst_encoder; 567 }; 568 569 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ 570 ((em) == ATOM_ENCODER_MODE_DP_MST)) 571 572 /* Driver internal use only flags of amdgpu_display_get_crtc_scanoutpos() */ 573 #define DRM_SCANOUTPOS_VALID (1 << 0) 574 #define DRM_SCANOUTPOS_IN_VBLANK (1 << 1) 575 #define DRM_SCANOUTPOS_ACCURATE (1 << 2) 576 #define USE_REAL_VBLANKSTART (1 << 30) 577 #define GET_DISTANCE_TO_VBLANKSTART (1 << 31) 578 579 void amdgpu_link_encoder_connector(struct drm_device *dev); 580 581 struct drm_connector * 582 amdgpu_get_connector_for_encoder(struct drm_encoder *encoder); 583 struct drm_connector * 584 amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder); 585 bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder, 586 u32 pixel_clock); 587 588 u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); 589 struct drm_encoder *amdgpu_get_external_encoder(struct drm_encoder *encoder); 590 591 bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector, 592 bool use_aux); 593 594 void amdgpu_encoder_set_active_device(struct drm_encoder *encoder); 595 596 int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev, 597 unsigned int pipe, unsigned int flags, int *vpos, 598 int *hpos, ktime_t *stime, ktime_t *etime, 599 const struct drm_display_mode *mode); 600 601 int amdgpu_display_framebuffer_init(struct drm_device *dev, 602 struct amdgpu_framebuffer *rfb, 603 const struct drm_mode_fb_cmd2 *mode_cmd, 604 struct drm_gem_object *obj); 605 606 int amdgpufb_remove(struct drm_device *dev, struct drm_framebuffer *fb); 607 608 void amdgpu_enc_destroy(struct drm_encoder *encoder); 609 void amdgpu_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 610 bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 611 const struct drm_display_mode *mode, 612 struct drm_display_mode *adjusted_mode); 613 void amdgpu_panel_mode_fixup(struct drm_encoder *encoder, 614 struct drm_display_mode *adjusted_mode); 615 int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc); 616 617 /* fbdev layer */ 618 int amdgpu_fbdev_init(struct amdgpu_device *adev); 619 void amdgpu_fbdev_fini(struct amdgpu_device *adev); 620 void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state); 621 int amdgpu_fbdev_total_size(struct amdgpu_device *adev); 622 bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj); 623 624 int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled); 625 626 /* amdgpu_display.c */ 627 void amdgpu_display_print_display_setup(struct drm_device *dev); 628 int amdgpu_display_modeset_create_props(struct amdgpu_device *adev); 629 int amdgpu_display_crtc_set_config(struct drm_mode_set *set, 630 struct drm_modeset_acquire_ctx *ctx); 631 int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, 632 struct drm_framebuffer *fb, 633 struct drm_pending_vblank_event *event, 634 uint32_t page_flip_flags, uint32_t target, 635 struct drm_modeset_acquire_ctx *ctx); 636 extern const struct drm_mode_config_funcs amdgpu_mode_funcs; 637 638 #endif 639
Indexes created Sun Sep 21 20:09:37 GMT 2025