1 /* $NetBSD: amdgpu_ucode.c,v 1.8 2021/12/19 12:21:29 riastradh Exp $ */ 2 3 /* 4 * Copyright 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #include <sys/cdefs.h> 27 __KERNEL_RCSID(0, "$NetBSD: amdgpu_ucode.c,v 1.8 2021/12/19 12:21:29 riastradh Exp $"); 28 29 #include <linux/firmware.h> 30 #include <linux/slab.h> 31 #include <linux/module.h> 32 33 #include "amdgpu.h" 34 #include "amdgpu_ucode.h" 35 36 #include <linux/nbsd-namespace.h> 37 38 static void amdgpu_ucode_print_common_hdr(const struct common_firmware_header *hdr) 39 { 40 DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes)); 41 DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes)); 42 DRM_DEBUG("header_version_major: %u\n", le16_to_cpu(hdr->header_version_major)); 43 DRM_DEBUG("header_version_minor: %u\n", le16_to_cpu(hdr->header_version_minor)); 44 DRM_DEBUG("ip_version_major: %u\n", le16_to_cpu(hdr->ip_version_major)); 45 DRM_DEBUG("ip_version_minor: %u\n", le16_to_cpu(hdr->ip_version_minor)); 46 DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version)); 47 DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes)); 48 DRM_DEBUG("ucode_array_offset_bytes: %u\n", 49 le32_to_cpu(hdr->ucode_array_offset_bytes)); 50 DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32)); 51 } 52 53 void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr) 54 { 55 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 56 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 57 58 DRM_DEBUG("MC\n"); 59 amdgpu_ucode_print_common_hdr(hdr); 60 61 if (version_major == 1) { 62 const struct mc_firmware_header_v1_0 *mc_hdr = 63 const_container_of(hdr, struct mc_firmware_header_v1_0, header); 64 65 DRM_DEBUG("io_debug_size_bytes: %u\n", 66 le32_to_cpu(mc_hdr->io_debug_size_bytes)); 67 DRM_DEBUG("io_debug_array_offset_bytes: %u\n", 68 le32_to_cpu(mc_hdr->io_debug_array_offset_bytes)); 69 } else { 70 DRM_ERROR("Unknown MC ucode version: %u.%u\n", version_major, version_minor); 71 } 72 } 73 74 void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr) 75 { 76 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 77 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 78 79 DRM_DEBUG("SMC\n"); 80 amdgpu_ucode_print_common_hdr(hdr); 81 82 if (version_major == 1) { 83 const struct smc_firmware_header_v1_0 *smc_hdr = 84 const_container_of(hdr, struct smc_firmware_header_v1_0, header); 85 86 DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(smc_hdr->ucode_start_addr)); 87 } else if (version_major == 2) { 88 const struct smc_firmware_header_v1_0 *v1_hdr = 89 const_container_of(hdr, struct smc_firmware_header_v1_0, header); 90 const struct smc_firmware_header_v2_0 *v2_hdr = 91 const_container_of(v1_hdr, struct smc_firmware_header_v2_0, v1_0); 92 93 DRM_DEBUG("ppt_offset_bytes: %u\n", le32_to_cpu(v2_hdr->ppt_offset_bytes)); 94 DRM_DEBUG("ppt_size_bytes: %u\n", le32_to_cpu(v2_hdr->ppt_size_bytes)); 95 } else { 96 DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major, version_minor); 97 } 98 } 99 100 void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr) 101 { 102 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 103 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 104 105 DRM_DEBUG("GFX\n"); 106 amdgpu_ucode_print_common_hdr(hdr); 107 108 if (version_major == 1) { 109 const struct gfx_firmware_header_v1_0 *gfx_hdr = 110 const_container_of(hdr, struct gfx_firmware_header_v1_0, header); 111 112 DRM_DEBUG("ucode_feature_version: %u\n", 113 le32_to_cpu(gfx_hdr->ucode_feature_version)); 114 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset)); 115 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(gfx_hdr->jt_size)); 116 } else { 117 DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor); 118 } 119 } 120 121 void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr) 122 { 123 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 124 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 125 126 DRM_DEBUG("RLC\n"); 127 amdgpu_ucode_print_common_hdr(hdr); 128 129 if (version_major == 1) { 130 const struct rlc_firmware_header_v1_0 *rlc_hdr = 131 const_container_of(hdr, struct rlc_firmware_header_v1_0, header); 132 133 DRM_DEBUG("ucode_feature_version: %u\n", 134 le32_to_cpu(rlc_hdr->ucode_feature_version)); 135 DRM_DEBUG("save_and_restore_offset: %u\n", 136 le32_to_cpu(rlc_hdr->save_and_restore_offset)); 137 DRM_DEBUG("clear_state_descriptor_offset: %u\n", 138 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset)); 139 DRM_DEBUG("avail_scratch_ram_locations: %u\n", 140 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations)); 141 DRM_DEBUG("master_pkt_description_offset: %u\n", 142 le32_to_cpu(rlc_hdr->master_pkt_description_offset)); 143 } else if (version_major == 2) { 144 const struct rlc_firmware_header_v2_0 *rlc_hdr = 145 const_container_of(hdr, struct rlc_firmware_header_v2_0, header); 146 147 DRM_DEBUG("ucode_feature_version: %u\n", 148 le32_to_cpu(rlc_hdr->ucode_feature_version)); 149 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset)); 150 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(rlc_hdr->jt_size)); 151 DRM_DEBUG("save_and_restore_offset: %u\n", 152 le32_to_cpu(rlc_hdr->save_and_restore_offset)); 153 DRM_DEBUG("clear_state_descriptor_offset: %u\n", 154 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset)); 155 DRM_DEBUG("avail_scratch_ram_locations: %u\n", 156 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations)); 157 DRM_DEBUG("reg_restore_list_size: %u\n", 158 le32_to_cpu(rlc_hdr->reg_restore_list_size)); 159 DRM_DEBUG("reg_list_format_start: %u\n", 160 le32_to_cpu(rlc_hdr->reg_list_format_start)); 161 DRM_DEBUG("reg_list_format_separate_start: %u\n", 162 le32_to_cpu(rlc_hdr->reg_list_format_separate_start)); 163 DRM_DEBUG("starting_offsets_start: %u\n", 164 le32_to_cpu(rlc_hdr->starting_offsets_start)); 165 DRM_DEBUG("reg_list_format_size_bytes: %u\n", 166 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes)); 167 DRM_DEBUG("reg_list_format_array_offset_bytes: %u\n", 168 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 169 DRM_DEBUG("reg_list_size_bytes: %u\n", 170 le32_to_cpu(rlc_hdr->reg_list_size_bytes)); 171 DRM_DEBUG("reg_list_array_offset_bytes: %u\n", 172 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 173 DRM_DEBUG("reg_list_format_separate_size_bytes: %u\n", 174 le32_to_cpu(rlc_hdr->reg_list_format_separate_size_bytes)); 175 DRM_DEBUG("reg_list_format_separate_array_offset_bytes: %u\n", 176 le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes)); 177 DRM_DEBUG("reg_list_separate_size_bytes: %u\n", 178 le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes)); 179 DRM_DEBUG("reg_list_separate_array_offset_bytes: %u\n", 180 le32_to_cpu(rlc_hdr->reg_list_separate_array_offset_bytes)); 181 if (version_minor == 1) { 182 const struct rlc_firmware_header_v2_1 *v2_1 = 183 const_container_of(rlc_hdr, struct rlc_firmware_header_v2_1, v2_0); 184 DRM_DEBUG("reg_list_format_direct_reg_list_length: %u\n", 185 le32_to_cpu(v2_1->reg_list_format_direct_reg_list_length)); 186 DRM_DEBUG("save_restore_list_cntl_ucode_ver: %u\n", 187 le32_to_cpu(v2_1->save_restore_list_cntl_ucode_ver)); 188 DRM_DEBUG("save_restore_list_cntl_feature_ver: %u\n", 189 le32_to_cpu(v2_1->save_restore_list_cntl_feature_ver)); 190 DRM_DEBUG("save_restore_list_cntl_size_bytes %u\n", 191 le32_to_cpu(v2_1->save_restore_list_cntl_size_bytes)); 192 DRM_DEBUG("save_restore_list_cntl_offset_bytes: %u\n", 193 le32_to_cpu(v2_1->save_restore_list_cntl_offset_bytes)); 194 DRM_DEBUG("save_restore_list_gpm_ucode_ver: %u\n", 195 le32_to_cpu(v2_1->save_restore_list_gpm_ucode_ver)); 196 DRM_DEBUG("save_restore_list_gpm_feature_ver: %u\n", 197 le32_to_cpu(v2_1->save_restore_list_gpm_feature_ver)); 198 DRM_DEBUG("save_restore_list_gpm_size_bytes %u\n", 199 le32_to_cpu(v2_1->save_restore_list_gpm_size_bytes)); 200 DRM_DEBUG("save_restore_list_gpm_offset_bytes: %u\n", 201 le32_to_cpu(v2_1->save_restore_list_gpm_offset_bytes)); 202 DRM_DEBUG("save_restore_list_srm_ucode_ver: %u\n", 203 le32_to_cpu(v2_1->save_restore_list_srm_ucode_ver)); 204 DRM_DEBUG("save_restore_list_srm_feature_ver: %u\n", 205 le32_to_cpu(v2_1->save_restore_list_srm_feature_ver)); 206 DRM_DEBUG("save_restore_list_srm_size_bytes %u\n", 207 le32_to_cpu(v2_1->save_restore_list_srm_size_bytes)); 208 DRM_DEBUG("save_restore_list_srm_offset_bytes: %u\n", 209 le32_to_cpu(v2_1->save_restore_list_srm_offset_bytes)); 210 } 211 } else { 212 DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor); 213 } 214 } 215 216 void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr) 217 { 218 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 219 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 220 221 DRM_DEBUG("SDMA\n"); 222 amdgpu_ucode_print_common_hdr(hdr); 223 224 if (version_major == 1) { 225 const struct sdma_firmware_header_v1_0 *sdma_hdr = 226 const_container_of(hdr, struct sdma_firmware_header_v1_0, header); 227 228 DRM_DEBUG("ucode_feature_version: %u\n", 229 le32_to_cpu(sdma_hdr->ucode_feature_version)); 230 DRM_DEBUG("ucode_change_version: %u\n", 231 le32_to_cpu(sdma_hdr->ucode_change_version)); 232 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset)); 233 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(sdma_hdr->jt_size)); 234 if (version_minor >= 1) { 235 const struct sdma_firmware_header_v1_1 *sdma_v1_1_hdr = 236 const_container_of(sdma_hdr, struct sdma_firmware_header_v1_1, v1_0); 237 DRM_DEBUG("digest_size: %u\n", le32_to_cpu(sdma_v1_1_hdr->digest_size)); 238 } 239 } else { 240 DRM_ERROR("Unknown SDMA ucode version: %u.%u\n", 241 version_major, version_minor); 242 } 243 } 244 245 void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr) 246 { 247 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 248 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 249 250 DRM_DEBUG("PSP\n"); 251 amdgpu_ucode_print_common_hdr(hdr); 252 253 if (version_major == 1) { 254 const struct psp_firmware_header_v1_0 *psp_hdr = 255 const_container_of(hdr, struct psp_firmware_header_v1_0, header); 256 257 DRM_DEBUG("ucode_feature_version: %u\n", 258 le32_to_cpu(psp_hdr->ucode_feature_version)); 259 DRM_DEBUG("sos_offset_bytes: %u\n", 260 le32_to_cpu(psp_hdr->sos_offset_bytes)); 261 DRM_DEBUG("sos_size_bytes: %u\n", 262 le32_to_cpu(psp_hdr->sos_size_bytes)); 263 if (version_minor == 1) { 264 const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 = 265 const_container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0); 266 DRM_DEBUG("toc_header_version: %u\n", 267 le32_to_cpu(psp_hdr_v1_1->toc_header_version)); 268 DRM_DEBUG("toc_offset_bytes: %u\n", 269 le32_to_cpu(psp_hdr_v1_1->toc_offset_bytes)); 270 DRM_DEBUG("toc_size_bytes: %u\n", 271 le32_to_cpu(psp_hdr_v1_1->toc_size_bytes)); 272 DRM_DEBUG("kdb_header_version: %u\n", 273 le32_to_cpu(psp_hdr_v1_1->kdb_header_version)); 274 DRM_DEBUG("kdb_offset_bytes: %u\n", 275 le32_to_cpu(psp_hdr_v1_1->kdb_offset_bytes)); 276 DRM_DEBUG("kdb_size_bytes: %u\n", 277 le32_to_cpu(psp_hdr_v1_1->kdb_size_bytes)); 278 } 279 if (version_minor == 2) { 280 const struct psp_firmware_header_v1_2 *psp_hdr_v1_2 = 281 const_container_of(psp_hdr, struct psp_firmware_header_v1_2, v1_0); 282 DRM_DEBUG("kdb_header_version: %u\n", 283 le32_to_cpu(psp_hdr_v1_2->kdb_header_version)); 284 DRM_DEBUG("kdb_offset_bytes: %u\n", 285 le32_to_cpu(psp_hdr_v1_2->kdb_offset_bytes)); 286 DRM_DEBUG("kdb_size_bytes: %u\n", 287 le32_to_cpu(psp_hdr_v1_2->kdb_size_bytes)); 288 } 289 } else { 290 DRM_ERROR("Unknown PSP ucode version: %u.%u\n", 291 version_major, version_minor); 292 } 293 } 294 295 void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr) 296 { 297 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 298 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 299 300 DRM_DEBUG("GPU_INFO\n"); 301 amdgpu_ucode_print_common_hdr(hdr); 302 303 if (version_major == 1) { 304 const struct gpu_info_firmware_header_v1_0 *gpu_info_hdr = 305 const_container_of(hdr, struct gpu_info_firmware_header_v1_0, header); 306 307 DRM_DEBUG("version_major: %u\n", 308 le16_to_cpu(gpu_info_hdr->version_major)); 309 DRM_DEBUG("version_minor: %u\n", 310 le16_to_cpu(gpu_info_hdr->version_minor)); 311 } else { 312 DRM_ERROR("Unknown gpu_info ucode version: %u.%u\n", version_major, version_minor); 313 } 314 } 315 316 int amdgpu_ucode_validate(const struct firmware *fw) 317 { 318 const struct common_firmware_header *hdr = 319 (const struct common_firmware_header *)fw->data; 320 321 if (fw->size == le32_to_cpu(hdr->size_bytes)) 322 return 0; 323 324 return -EINVAL; 325 } 326 327 bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr, 328 uint16_t hdr_major, uint16_t hdr_minor) 329 { 330 if ((hdr->common.header_version_major == hdr_major) && 331 (hdr->common.header_version_minor == hdr_minor)) 332 return false; 333 return true; 334 } 335 336 enum amdgpu_firmware_load_type 337 amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type) 338 { 339 switch (adev->asic_type) { 340 #ifdef CONFIG_DRM_AMDGPU_SI 341 case CHIP_TAHITI: 342 case CHIP_PITCAIRN: 343 case CHIP_VERDE: 344 case CHIP_OLAND: 345 case CHIP_HAINAN: 346 return AMDGPU_FW_LOAD_DIRECT; 347 #endif 348 #ifdef CONFIG_DRM_AMDGPU_CIK 349 case CHIP_BONAIRE: 350 case CHIP_KAVERI: 351 case CHIP_KABINI: 352 case CHIP_HAWAII: 353 case CHIP_MULLINS: 354 return AMDGPU_FW_LOAD_DIRECT; 355 #endif 356 case CHIP_TOPAZ: 357 case CHIP_TONGA: 358 case CHIP_FIJI: 359 case CHIP_CARRIZO: 360 case CHIP_STONEY: 361 case CHIP_POLARIS10: 362 case CHIP_POLARIS11: 363 case CHIP_POLARIS12: 364 case CHIP_VEGAM: 365 return AMDGPU_FW_LOAD_SMU; 366 case CHIP_VEGA10: 367 case CHIP_RAVEN: 368 case CHIP_VEGA12: 369 case CHIP_VEGA20: 370 case CHIP_ARCTURUS: 371 case CHIP_RENOIR: 372 case CHIP_NAVI10: 373 case CHIP_NAVI14: 374 case CHIP_NAVI12: 375 if (!load_type) 376 return AMDGPU_FW_LOAD_DIRECT; 377 else 378 return AMDGPU_FW_LOAD_PSP; 379 380 default: 381 DRM_ERROR("Unknown firmware load type\n"); 382 } 383 384 return AMDGPU_FW_LOAD_DIRECT; 385 } 386 387 #ifndef __NetBSD__ /* XXX amdgpu sysfs */ 388 389 #define FW_VERSION_ATTR(name, mode, field) \ 390 static ssize_t show_##name(struct device *dev, \ 391 struct device_attribute *attr, \ 392 char *buf) \ 393 { \ 394 struct drm_device *ddev = dev_get_drvdata(dev); \ 395 struct amdgpu_device *adev = ddev->dev_private; \ 396 \ 397 return snprintf(buf, PAGE_SIZE, "0x%08x\n", adev->field); \ 398 } \ 399 static DEVICE_ATTR(name, mode, show_##name, NULL) 400 401 FW_VERSION_ATTR(vce_fw_version, 0444, vce.fw_version); 402 FW_VERSION_ATTR(uvd_fw_version, 0444, uvd.fw_version); 403 FW_VERSION_ATTR(mc_fw_version, 0444, gmc.fw_version); 404 FW_VERSION_ATTR(me_fw_version, 0444, gfx.me_fw_version); 405 FW_VERSION_ATTR(pfp_fw_version, 0444, gfx.pfp_fw_version); 406 FW_VERSION_ATTR(ce_fw_version, 0444, gfx.ce_fw_version); 407 FW_VERSION_ATTR(rlc_fw_version, 0444, gfx.rlc_fw_version); 408 FW_VERSION_ATTR(rlc_srlc_fw_version, 0444, gfx.rlc_srlc_fw_version); 409 FW_VERSION_ATTR(rlc_srlg_fw_version, 0444, gfx.rlc_srlg_fw_version); 410 FW_VERSION_ATTR(rlc_srls_fw_version, 0444, gfx.rlc_srls_fw_version); 411 FW_VERSION_ATTR(mec_fw_version, 0444, gfx.mec_fw_version); 412 FW_VERSION_ATTR(mec2_fw_version, 0444, gfx.mec2_fw_version); 413 FW_VERSION_ATTR(sos_fw_version, 0444, psp.sos_fw_version); 414 FW_VERSION_ATTR(asd_fw_version, 0444, psp.asd_fw_version); 415 FW_VERSION_ATTR(ta_ras_fw_version, 0444, psp.ta_fw_version); 416 FW_VERSION_ATTR(ta_xgmi_fw_version, 0444, psp.ta_fw_version); 417 FW_VERSION_ATTR(smc_fw_version, 0444, pm.fw_version); 418 FW_VERSION_ATTR(sdma_fw_version, 0444, sdma.instance[0].fw_version); 419 FW_VERSION_ATTR(sdma2_fw_version, 0444, sdma.instance[1].fw_version); 420 FW_VERSION_ATTR(vcn_fw_version, 0444, vcn.fw_version); 421 FW_VERSION_ATTR(dmcu_fw_version, 0444, dm.dmcu_fw_version); 422 423 static struct attribute *fw_attrs[] = { 424 &dev_attr_vce_fw_version.attr, &dev_attr_uvd_fw_version.attr, 425 &dev_attr_mc_fw_version.attr, &dev_attr_me_fw_version.attr, 426 &dev_attr_pfp_fw_version.attr, &dev_attr_ce_fw_version.attr, 427 &dev_attr_rlc_fw_version.attr, &dev_attr_rlc_srlc_fw_version.attr, 428 &dev_attr_rlc_srlg_fw_version.attr, &dev_attr_rlc_srls_fw_version.attr, 429 &dev_attr_mec_fw_version.attr, &dev_attr_mec2_fw_version.attr, 430 &dev_attr_sos_fw_version.attr, &dev_attr_asd_fw_version.attr, 431 &dev_attr_ta_ras_fw_version.attr, &dev_attr_ta_xgmi_fw_version.attr, 432 &dev_attr_smc_fw_version.attr, &dev_attr_sdma_fw_version.attr, 433 &dev_attr_sdma2_fw_version.attr, &dev_attr_vcn_fw_version.attr, 434 &dev_attr_dmcu_fw_version.attr, NULL 435 }; 436 437 static const struct attribute_group fw_attr_group = { 438 .name = "fw_version", 439 .attrs = fw_attrs 440 }; 441 442 #endif /* __NetBSD__ */ 443 444 int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev) 445 { 446 #ifdef __NetBSD__ 447 return 0; 448 #else 449 return sysfs_create_group(&adev->dev->kobj, &fw_attr_group); 450 #endif 451 } 452 453 void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev) 454 { 455 #ifndef __NetBSD__ 456 sysfs_remove_group(&adev->dev->kobj, &fw_attr_group); 457 #endif 458 } 459 460 static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev, 461 struct amdgpu_firmware_info *ucode, 462 uint64_t mc_addr, void *kptr) 463 { 464 const struct common_firmware_header *header = NULL; 465 const struct gfx_firmware_header_v1_0 *cp_hdr = NULL; 466 const struct dmcu_firmware_header_v1_0 *dmcu_hdr = NULL; 467 const struct dmcub_firmware_header_v1_0 *dmcub_hdr = NULL; 468 469 if (NULL == ucode->fw) 470 return 0; 471 472 ucode->mc_addr = mc_addr; 473 ucode->kaddr = kptr; 474 475 if (ucode->ucode_id == AMDGPU_UCODE_ID_STORAGE) 476 return 0; 477 478 header = (const struct common_firmware_header *)ucode->fw->data; 479 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; 480 dmcu_hdr = (const struct dmcu_firmware_header_v1_0 *)ucode->fw->data; 481 dmcub_hdr = (const struct dmcub_firmware_header_v1_0 *)ucode->fw->data; 482 483 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP || 484 (ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1 && 485 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2 && 486 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1_JT && 487 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2_JT && 488 ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL && 489 ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM && 490 ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM && 491 ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_ERAM && 492 ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_INTV && 493 ucode->ucode_id != AMDGPU_UCODE_ID_DMCUB)) { 494 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes); 495 496 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data + 497 le32_to_cpu(header->ucode_array_offset_bytes)), 498 ucode->ucode_size); 499 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1 || 500 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2) { 501 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) - 502 le32_to_cpu(cp_hdr->jt_size) * 4; 503 504 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data + 505 le32_to_cpu(header->ucode_array_offset_bytes)), 506 ucode->ucode_size); 507 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 508 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT) { 509 ucode->ucode_size = le32_to_cpu(cp_hdr->jt_size) * 4; 510 511 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data + 512 le32_to_cpu(header->ucode_array_offset_bytes) + 513 le32_to_cpu(cp_hdr->jt_offset) * 4), 514 ucode->ucode_size); 515 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCU_ERAM) { 516 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) - 517 le32_to_cpu(dmcu_hdr->intv_size_bytes); 518 519 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data + 520 le32_to_cpu(header->ucode_array_offset_bytes)), 521 ucode->ucode_size); 522 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCU_INTV) { 523 ucode->ucode_size = le32_to_cpu(dmcu_hdr->intv_size_bytes); 524 525 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data + 526 le32_to_cpu(header->ucode_array_offset_bytes) + 527 le32_to_cpu(dmcu_hdr->intv_offset_bytes)), 528 ucode->ucode_size); 529 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCUB) { 530 ucode->ucode_size = le32_to_cpu(dmcub_hdr->inst_const_bytes); 531 memcpy(ucode->kaddr, 532 (void *)((uint8_t *)ucode->fw->data + 533 le32_to_cpu(header->ucode_array_offset_bytes)), 534 ucode->ucode_size); 535 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL) { 536 ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes; 537 memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_cntl, 538 ucode->ucode_size); 539 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM) { 540 ucode->ucode_size = adev->gfx.rlc.save_restore_list_gpm_size_bytes; 541 memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_gpm, 542 ucode->ucode_size); 543 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM) { 544 ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes; 545 memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_srm, 546 ucode->ucode_size); 547 } 548 549 return 0; 550 } 551 552 static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode, 553 uint64_t mc_addr, void *kptr) 554 { 555 const struct gfx_firmware_header_v1_0 *header = NULL; 556 const struct common_firmware_header *comm_hdr = NULL; 557 uint8_t* src_addr = NULL; 558 uint8_t* dst_addr = NULL; 559 560 if (NULL == ucode->fw) 561 return 0; 562 563 comm_hdr = (const struct common_firmware_header *)ucode->fw->data; 564 header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; 565 dst_addr = ucode->kaddr + 566 ALIGN(le32_to_cpu(comm_hdr->ucode_size_bytes), 567 PAGE_SIZE); 568 src_addr = (uint8_t *)ucode->fw->data + 569 le32_to_cpu(comm_hdr->ucode_array_offset_bytes) + 570 (le32_to_cpu(header->jt_offset) * 4); 571 memcpy(dst_addr, src_addr, le32_to_cpu(header->jt_size) * 4); 572 573 return 0; 574 } 575 576 int amdgpu_ucode_create_bo(struct amdgpu_device *adev) 577 { 578 if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT) { 579 amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE, 580 amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 581 &adev->firmware.fw_buf, 582 &adev->firmware.fw_buf_mc, 583 &adev->firmware.fw_buf_ptr); 584 if (!adev->firmware.fw_buf) { 585 dev_err(adev->dev, "failed to create kernel buffer for firmware.fw_buf\n"); 586 return -ENOMEM; 587 } else if (amdgpu_sriov_vf(adev)) { 588 memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size); 589 } 590 } 591 return 0; 592 } 593 594 void amdgpu_ucode_free_bo(struct amdgpu_device *adev) 595 { 596 if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT) 597 amdgpu_bo_free_kernel(&adev->firmware.fw_buf, 598 &adev->firmware.fw_buf_mc, 599 &adev->firmware.fw_buf_ptr); 600 } 601 602 int amdgpu_ucode_init_bo(struct amdgpu_device *adev) 603 { 604 uint64_t fw_offset = 0; 605 int i; 606 struct amdgpu_firmware_info *ucode = NULL; 607 608 /* for baremetal, the ucode is allocated in gtt, so don't need to fill the bo when reset/suspend */ 609 if (!amdgpu_sriov_vf(adev) && (adev->in_gpu_reset || adev->in_suspend)) 610 return 0; 611 /* 612 * if SMU loaded firmware, it needn't add SMC, UVD, and VCE 613 * ucode info here 614 */ 615 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 616 if (amdgpu_sriov_vf(adev)) 617 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 3; 618 else 619 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 4; 620 } else { 621 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM; 622 } 623 624 for (i = 0; i < adev->firmware.max_ucodes; i++) { 625 ucode = &adev->firmware.ucode[i]; 626 if (ucode->fw) { 627 amdgpu_ucode_init_single_fw(adev, ucode, adev->firmware.fw_buf_mc + fw_offset, 628 adev->firmware.fw_buf_ptr + fw_offset); 629 if (i == AMDGPU_UCODE_ID_CP_MEC1 && 630 adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 631 const struct gfx_firmware_header_v1_0 *cp_hdr; 632 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; 633 amdgpu_ucode_patch_jt(ucode, adev->firmware.fw_buf_mc + fw_offset, 634 adev->firmware.fw_buf_ptr + fw_offset); 635 fw_offset += ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE); 636 } 637 fw_offset += ALIGN(ucode->ucode_size, PAGE_SIZE); 638 } 639 } 640 return 0; 641 } 642
Indexes created Sun Sep 21 20:09:37 GMT 2025