1 /* $NetBSD: atomfirmware.h,v 1.2 2021/12/18 23:45:08 riastradh Exp $ */ 2 3 /****************************************************************************\ 4 * 5 * File Name atomfirmware.h 6 * Project This is an interface header file between atombios and OS GPU drivers for SoC15 products 7 * 8 * Description header file of general definitions for OS nd pre-OS video drivers 9 * 10 * Copyright 2014 Advanced Micro Devices, Inc. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software 13 * and associated documentation files (the "Software"), to deal in the Software without restriction, 14 * including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, 15 * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, 16 * subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice shall be included in all copies or substantial 19 * portions of the Software. 20 * 21 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 22 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 23 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 24 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 25 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 26 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 27 * OTHER DEALINGS IN THE SOFTWARE. 28 * 29 \****************************************************************************/ 30 31 /*IMPORTANT NOTES 32 * If a change in VBIOS/Driver/Tool's interface is only needed for SoC15 and forward products, then the change is only needed in this atomfirmware.h header file. 33 * If a change in VBIOS/Driver/Tool's interface is only needed for pre-SoC15 products, then the change is only needed in atombios.h header file. 34 * If a change is needed for both pre and post SoC15 products, then the change has to be made separately and might be differently in both atomfirmware.h and atombios.h. 35 */ 36 37 #ifndef _ATOMFIRMWARE_H_ 38 #define _ATOMFIRMWARE_H_ 39 40 enum atom_bios_header_version_def{ 41 ATOM_MAJOR_VERSION =0x0003, 42 ATOM_MINOR_VERSION =0x0003, 43 }; 44 45 #ifdef _H2INC 46 #ifndef uint32_t 47 typedef unsigned long uint32_t; 48 #endif 49 50 #ifndef uint16_t 51 typedef unsigned short uint16_t; 52 #endif 53 54 #ifndef uint8_t 55 typedef unsigned char uint8_t; 56 #endif 57 #endif 58 59 enum atom_crtc_def{ 60 ATOM_CRTC1 =0, 61 ATOM_CRTC2 =1, 62 ATOM_CRTC3 =2, 63 ATOM_CRTC4 =3, 64 ATOM_CRTC5 =4, 65 ATOM_CRTC6 =5, 66 ATOM_CRTC_INVALID =0xff, 67 }; 68 69 enum atom_ppll_def{ 70 ATOM_PPLL0 =2, 71 ATOM_GCK_DFS =8, 72 ATOM_FCH_CLK =9, 73 ATOM_DP_DTO =11, 74 ATOM_COMBOPHY_PLL0 =20, 75 ATOM_COMBOPHY_PLL1 =21, 76 ATOM_COMBOPHY_PLL2 =22, 77 ATOM_COMBOPHY_PLL3 =23, 78 ATOM_COMBOPHY_PLL4 =24, 79 ATOM_COMBOPHY_PLL5 =25, 80 ATOM_PPLL_INVALID =0xff, 81 }; 82 83 // define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSel 84 enum atom_dig_def{ 85 ASIC_INT_DIG1_ENCODER_ID =0x03, 86 ASIC_INT_DIG2_ENCODER_ID =0x09, 87 ASIC_INT_DIG3_ENCODER_ID =0x0a, 88 ASIC_INT_DIG4_ENCODER_ID =0x0b, 89 ASIC_INT_DIG5_ENCODER_ID =0x0c, 90 ASIC_INT_DIG6_ENCODER_ID =0x0d, 91 ASIC_INT_DIG7_ENCODER_ID =0x0e, 92 }; 93 94 //ucEncoderMode 95 enum atom_encode_mode_def 96 { 97 ATOM_ENCODER_MODE_DP =0, 98 ATOM_ENCODER_MODE_DP_SST =0, 99 ATOM_ENCODER_MODE_LVDS =1, 100 ATOM_ENCODER_MODE_DVI =2, 101 ATOM_ENCODER_MODE_HDMI =3, 102 ATOM_ENCODER_MODE_DP_AUDIO =5, 103 ATOM_ENCODER_MODE_DP_MST =5, 104 ATOM_ENCODER_MODE_CRT =15, 105 ATOM_ENCODER_MODE_DVO =16, 106 }; 107 108 enum atom_encoder_refclk_src_def{ 109 ENCODER_REFCLK_SRC_P1PLL =0, 110 ENCODER_REFCLK_SRC_P2PLL =1, 111 ENCODER_REFCLK_SRC_P3PLL =2, 112 ENCODER_REFCLK_SRC_EXTCLK =3, 113 ENCODER_REFCLK_SRC_INVALID =0xff, 114 }; 115 116 enum atom_scaler_def{ 117 ATOM_SCALER_DISABLE =0, /*scaler bypass mode, auto-center & no replication*/ 118 ATOM_SCALER_CENTER =1, //For Fudo, it's bypass and auto-center & auto replication 119 ATOM_SCALER_EXPANSION =2, /*scaler expansion by 2 tap alpha blending mode*/ 120 }; 121 122 enum atom_operation_def{ 123 ATOM_DISABLE = 0, 124 ATOM_ENABLE = 1, 125 ATOM_INIT = 7, 126 ATOM_GET_STATUS = 8, 127 }; 128 129 enum atom_embedded_display_op_def{ 130 ATOM_LCD_BL_OFF = 2, 131 ATOM_LCD_BL_OM = 3, 132 ATOM_LCD_BL_BRIGHTNESS_CONTROL = 4, 133 ATOM_LCD_SELFTEST_START = 5, 134 ATOM_LCD_SELFTEST_STOP = 6, 135 }; 136 137 enum atom_spread_spectrum_mode{ 138 ATOM_SS_CENTER_OR_DOWN_MODE_MASK = 0x01, 139 ATOM_SS_DOWN_SPREAD_MODE = 0x00, 140 ATOM_SS_CENTRE_SPREAD_MODE = 0x01, 141 ATOM_INT_OR_EXT_SS_MASK = 0x02, 142 ATOM_INTERNAL_SS_MASK = 0x00, 143 ATOM_EXTERNAL_SS_MASK = 0x02, 144 }; 145 146 /* define panel bit per color */ 147 enum atom_panel_bit_per_color{ 148 PANEL_BPC_UNDEFINE =0x00, 149 PANEL_6BIT_PER_COLOR =0x01, 150 PANEL_8BIT_PER_COLOR =0x02, 151 PANEL_10BIT_PER_COLOR =0x03, 152 PANEL_12BIT_PER_COLOR =0x04, 153 PANEL_16BIT_PER_COLOR =0x05, 154 }; 155 156 //ucVoltageType 157 enum atom_voltage_type 158 { 159 VOLTAGE_TYPE_VDDC = 1, 160 VOLTAGE_TYPE_MVDDC = 2, 161 VOLTAGE_TYPE_MVDDQ = 3, 162 VOLTAGE_TYPE_VDDCI = 4, 163 VOLTAGE_TYPE_VDDGFX = 5, 164 VOLTAGE_TYPE_PCC = 6, 165 VOLTAGE_TYPE_MVPP = 7, 166 VOLTAGE_TYPE_LEDDPM = 8, 167 VOLTAGE_TYPE_PCC_MVDD = 9, 168 VOLTAGE_TYPE_PCIE_VDDC = 10, 169 VOLTAGE_TYPE_PCIE_VDDR = 11, 170 VOLTAGE_TYPE_GENERIC_I2C_1 = 0x11, 171 VOLTAGE_TYPE_GENERIC_I2C_2 = 0x12, 172 VOLTAGE_TYPE_GENERIC_I2C_3 = 0x13, 173 VOLTAGE_TYPE_GENERIC_I2C_4 = 0x14, 174 VOLTAGE_TYPE_GENERIC_I2C_5 = 0x15, 175 VOLTAGE_TYPE_GENERIC_I2C_6 = 0x16, 176 VOLTAGE_TYPE_GENERIC_I2C_7 = 0x17, 177 VOLTAGE_TYPE_GENERIC_I2C_8 = 0x18, 178 VOLTAGE_TYPE_GENERIC_I2C_9 = 0x19, 179 VOLTAGE_TYPE_GENERIC_I2C_10 = 0x1A, 180 }; 181 182 enum atom_dgpu_vram_type { 183 ATOM_DGPU_VRAM_TYPE_GDDR5 = 0x50, 184 ATOM_DGPU_VRAM_TYPE_HBM2 = 0x60, 185 ATOM_DGPU_VRAM_TYPE_GDDR6 = 0x70, 186 }; 187 188 enum atom_dp_vs_preemph_def{ 189 DP_VS_LEVEL0_PREEMPH_LEVEL0 = 0x00, 190 DP_VS_LEVEL1_PREEMPH_LEVEL0 = 0x01, 191 DP_VS_LEVEL2_PREEMPH_LEVEL0 = 0x02, 192 DP_VS_LEVEL3_PREEMPH_LEVEL0 = 0x03, 193 DP_VS_LEVEL0_PREEMPH_LEVEL1 = 0x08, 194 DP_VS_LEVEL1_PREEMPH_LEVEL1 = 0x09, 195 DP_VS_LEVEL2_PREEMPH_LEVEL1 = 0x0a, 196 DP_VS_LEVEL0_PREEMPH_LEVEL2 = 0x10, 197 DP_VS_LEVEL1_PREEMPH_LEVEL2 = 0x11, 198 DP_VS_LEVEL0_PREEMPH_LEVEL3 = 0x18, 199 }; 200 201 202 /* 203 enum atom_string_def{ 204 asic_bus_type_pcie_string = "PCI_EXPRESS", 205 atom_fire_gl_string = "FGL", 206 atom_bios_string = "ATOM" 207 }; 208 */ 209 210 #pragma pack(1) /* BIOS data must use byte aligment*/ 211 212 enum atombios_image_offset{ 213 OFFSET_TO_ATOM_ROM_HEADER_POINTER =0x00000048, 214 OFFSET_TO_ATOM_ROM_IMAGE_SIZE =0x00000002, 215 OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE =0x94, 216 MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE =20, /*including the terminator 0x0!*/ 217 OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS =0x2f, 218 OFFSET_TO_GET_ATOMBIOS_STRING_START =0x6e, 219 }; 220 221 /**************************************************************************** 222 * Common header for all tables (Data table, Command function). 223 * Every table pointed in _ATOM_MASTER_DATA_TABLE has this common header. 224 * And the pointer actually points to this header. 225 ****************************************************************************/ 226 227 struct atom_common_table_header 228 { 229 uint16_t structuresize; 230 uint8_t format_revision; //mainly used for a hw function, when the parser is not backward compatible 231 uint8_t content_revision; //change it when a data table has a structure change, or a hw function has a input/output parameter change 232 }; 233 234 /**************************************************************************** 235 * Structure stores the ROM header. 236 ****************************************************************************/ 237 struct atom_rom_header_v2_2 238 { 239 struct atom_common_table_header table_header; 240 uint8_t atom_bios_string[4]; //enum atom_string_def atom_bios_string; //Signature to distinguish between Atombios and non-atombios, 241 uint16_t bios_segment_address; 242 uint16_t protectedmodeoffset; 243 uint16_t configfilenameoffset; 244 uint16_t crc_block_offset; 245 uint16_t vbios_bootupmessageoffset; 246 uint16_t int10_offset; 247 uint16_t pcibusdevinitcode; 248 uint16_t iobaseaddress; 249 uint16_t subsystem_vendor_id; 250 uint16_t subsystem_id; 251 uint16_t pci_info_offset; 252 uint16_t masterhwfunction_offset; //Offest for SW to get all command function offsets, Don't change the position 253 uint16_t masterdatatable_offset; //Offest for SW to get all data table offsets, Don't change the position 254 uint16_t reserved; 255 uint32_t pspdirtableoffset; 256 }; 257 258 /*==============================hw function portion======================================================================*/ 259 260 261 /**************************************************************************** 262 * Structures used in Command.mtb, each function name is not given here since those function could change from time to time 263 * The real functionality of each function is associated with the parameter structure version when defined 264 * For all internal cmd function definitions, please reference to atomstruct.h 265 ****************************************************************************/ 266 struct atom_master_list_of_command_functions_v2_1{ 267 uint16_t asic_init; //Function 268 uint16_t cmd_function1; //used as an internal one 269 uint16_t cmd_function2; //used as an internal one 270 uint16_t cmd_function3; //used as an internal one 271 uint16_t digxencodercontrol; //Function 272 uint16_t cmd_function5; //used as an internal one 273 uint16_t cmd_function6; //used as an internal one 274 uint16_t cmd_function7; //used as an internal one 275 uint16_t cmd_function8; //used as an internal one 276 uint16_t cmd_function9; //used as an internal one 277 uint16_t setengineclock; //Function 278 uint16_t setmemoryclock; //Function 279 uint16_t setpixelclock; //Function 280 uint16_t enabledisppowergating; //Function 281 uint16_t cmd_function14; //used as an internal one 282 uint16_t cmd_function15; //used as an internal one 283 uint16_t cmd_function16; //used as an internal one 284 uint16_t cmd_function17; //used as an internal one 285 uint16_t cmd_function18; //used as an internal one 286 uint16_t cmd_function19; //used as an internal one 287 uint16_t cmd_function20; //used as an internal one 288 uint16_t cmd_function21; //used as an internal one 289 uint16_t cmd_function22; //used as an internal one 290 uint16_t cmd_function23; //used as an internal one 291 uint16_t cmd_function24; //used as an internal one 292 uint16_t cmd_function25; //used as an internal one 293 uint16_t cmd_function26; //used as an internal one 294 uint16_t cmd_function27; //used as an internal one 295 uint16_t cmd_function28; //used as an internal one 296 uint16_t cmd_function29; //used as an internal one 297 uint16_t cmd_function30; //used as an internal one 298 uint16_t cmd_function31; //used as an internal one 299 uint16_t cmd_function32; //used as an internal one 300 uint16_t cmd_function33; //used as an internal one 301 uint16_t blankcrtc; //Function 302 uint16_t enablecrtc; //Function 303 uint16_t cmd_function36; //used as an internal one 304 uint16_t cmd_function37; //used as an internal one 305 uint16_t cmd_function38; //used as an internal one 306 uint16_t cmd_function39; //used as an internal one 307 uint16_t cmd_function40; //used as an internal one 308 uint16_t getsmuclockinfo; //Function 309 uint16_t selectcrtc_source; //Function 310 uint16_t cmd_function43; //used as an internal one 311 uint16_t cmd_function44; //used as an internal one 312 uint16_t cmd_function45; //used as an internal one 313 uint16_t setdceclock; //Function 314 uint16_t getmemoryclock; //Function 315 uint16_t getengineclock; //Function 316 uint16_t setcrtc_usingdtdtiming; //Function 317 uint16_t externalencodercontrol; //Function 318 uint16_t cmd_function51; //used as an internal one 319 uint16_t cmd_function52; //used as an internal one 320 uint16_t cmd_function53; //used as an internal one 321 uint16_t processi2cchanneltransaction;//Function 322 uint16_t cmd_function55; //used as an internal one 323 uint16_t cmd_function56; //used as an internal one 324 uint16_t cmd_function57; //used as an internal one 325 uint16_t cmd_function58; //used as an internal one 326 uint16_t cmd_function59; //used as an internal one 327 uint16_t computegpuclockparam; //Function 328 uint16_t cmd_function61; //used as an internal one 329 uint16_t cmd_function62; //used as an internal one 330 uint16_t dynamicmemorysettings; //Function function 331 uint16_t memorytraining; //Function function 332 uint16_t cmd_function65; //used as an internal one 333 uint16_t cmd_function66; //used as an internal one 334 uint16_t setvoltage; //Function 335 uint16_t cmd_function68; //used as an internal one 336 uint16_t readefusevalue; //Function 337 uint16_t cmd_function70; //used as an internal one 338 uint16_t cmd_function71; //used as an internal one 339 uint16_t cmd_function72; //used as an internal one 340 uint16_t cmd_function73; //used as an internal one 341 uint16_t cmd_function74; //used as an internal one 342 uint16_t cmd_function75; //used as an internal one 343 uint16_t dig1transmittercontrol; //Function 344 uint16_t cmd_function77; //used as an internal one 345 uint16_t processauxchanneltransaction;//Function 346 uint16_t cmd_function79; //used as an internal one 347 uint16_t getvoltageinfo; //Function 348 }; 349 350 struct atom_master_command_function_v2_1 351 { 352 struct atom_common_table_header table_header; 353 struct atom_master_list_of_command_functions_v2_1 listofcmdfunctions; 354 }; 355 356 /**************************************************************************** 357 * Structures used in every command function 358 ****************************************************************************/ 359 struct atom_function_attribute 360 { 361 uint16_t ws_in_bytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), 362 uint16_t ps_in_bytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), 363 uint16_t updated_by_util:1; //[15]=flag to indicate the function is updated by util 364 }; 365 366 367 /**************************************************************************** 368 * Common header for all hw functions. 369 * Every function pointed by _master_list_of_hw_function has this common header. 370 * And the pointer actually points to this header. 371 ****************************************************************************/ 372 struct atom_rom_hw_function_header 373 { 374 struct atom_common_table_header func_header; 375 struct atom_function_attribute func_attrib; 376 }; 377 378 379 /*==============================sw data table portion======================================================================*/ 380 /**************************************************************************** 381 * Structures used in data.mtb, each data table name is not given here since those data table could change from time to time 382 * The real name of each table is given when its data structure version is defined 383 ****************************************************************************/ 384 struct atom_master_list_of_data_tables_v2_1{ 385 uint16_t utilitypipeline; /* Offest for the utility to get parser info,Don't change this position!*/ 386 uint16_t multimedia_info; 387 uint16_t smc_dpm_info; 388 uint16_t sw_datatable3; 389 uint16_t firmwareinfo; /* Shared by various SW components */ 390 uint16_t sw_datatable5; 391 uint16_t lcd_info; /* Shared by various SW components */ 392 uint16_t sw_datatable7; 393 uint16_t smu_info; 394 uint16_t sw_datatable9; 395 uint16_t sw_datatable10; 396 uint16_t vram_usagebyfirmware; /* Shared by various SW components */ 397 uint16_t gpio_pin_lut; /* Shared by various SW components */ 398 uint16_t sw_datatable13; 399 uint16_t gfx_info; 400 uint16_t powerplayinfo; /* Shared by various SW components */ 401 uint16_t sw_datatable16; 402 uint16_t sw_datatable17; 403 uint16_t sw_datatable18; 404 uint16_t sw_datatable19; 405 uint16_t sw_datatable20; 406 uint16_t sw_datatable21; 407 uint16_t displayobjectinfo; /* Shared by various SW components */ 408 uint16_t indirectioaccess; /* used as an internal one */ 409 uint16_t umc_info; /* Shared by various SW components */ 410 uint16_t sw_datatable25; 411 uint16_t sw_datatable26; 412 uint16_t dce_info; /* Shared by various SW components */ 413 uint16_t vram_info; /* Shared by various SW components */ 414 uint16_t sw_datatable29; 415 uint16_t integratedsysteminfo; /* Shared by various SW components */ 416 uint16_t asic_profiling_info; /* Shared by various SW components */ 417 uint16_t voltageobject_info; /* shared by various SW components */ 418 uint16_t sw_datatable33; 419 uint16_t sw_datatable34; 420 }; 421 422 423 struct atom_master_data_table_v2_1 424 { 425 struct atom_common_table_header table_header; 426 struct atom_master_list_of_data_tables_v2_1 listOfdatatables; 427 }; 428 429 430 struct atom_dtd_format 431 { 432 uint16_t pixclk; 433 uint16_t h_active; 434 uint16_t h_blanking_time; 435 uint16_t v_active; 436 uint16_t v_blanking_time; 437 uint16_t h_sync_offset; 438 uint16_t h_sync_width; 439 uint16_t v_sync_offset; 440 uint16_t v_syncwidth; 441 uint16_t reserved; 442 uint16_t reserved0; 443 uint8_t h_border; 444 uint8_t v_border; 445 uint16_t miscinfo; 446 uint8_t atom_mode_id; 447 uint8_t refreshrate; 448 }; 449 450 /* atom_dtd_format.modemiscinfo defintion */ 451 enum atom_dtd_format_modemiscinfo{ 452 ATOM_HSYNC_POLARITY = 0x0002, 453 ATOM_VSYNC_POLARITY = 0x0004, 454 ATOM_H_REPLICATIONBY2 = 0x0010, 455 ATOM_V_REPLICATIONBY2 = 0x0020, 456 ATOM_INTERLACE = 0x0080, 457 ATOM_COMPOSITESYNC = 0x0040, 458 }; 459 460 461 /* utilitypipeline 462 * when format_revision==1 && content_revision==1, then this an info table for atomworks to use during debug session, no structure is associated with it. 463 * the location of it can't change 464 */ 465 466 467 /* 468 *************************************************************************** 469 Data Table firmwareinfo structure 470 *************************************************************************** 471 */ 472 473 struct atom_firmware_info_v3_1 474 { 475 struct atom_common_table_header table_header; 476 uint32_t firmware_revision; 477 uint32_t bootup_sclk_in10khz; 478 uint32_t bootup_mclk_in10khz; 479 uint32_t firmware_capability; // enum atombios_firmware_capability 480 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ 481 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address 482 uint16_t bootup_vddc_mv; 483 uint16_t bootup_vddci_mv; 484 uint16_t bootup_mvddc_mv; 485 uint16_t bootup_vddgfx_mv; 486 uint8_t mem_module_id; 487 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ 488 uint8_t reserved1[2]; 489 uint32_t mc_baseaddr_high; 490 uint32_t mc_baseaddr_low; 491 uint32_t reserved2[6]; 492 }; 493 494 /* Total 32bit cap indication */ 495 enum atombios_firmware_capability 496 { 497 ATOM_FIRMWARE_CAP_FIRMWARE_POSTED = 0x00000001, 498 ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION = 0x00000002, 499 ATOM_FIRMWARE_CAP_WMI_SUPPORT = 0x00000040, 500 ATOM_FIRMWARE_CAP_HWEMU_ENABLE = 0x00000080, 501 ATOM_FIRMWARE_CAP_HWEMU_UMC_CFG = 0x00000100, 502 ATOM_FIRMWARE_CAP_SRAM_ECC = 0x00000200, 503 ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING = 0x00000400, 504 }; 505 506 enum atom_cooling_solution_id{ 507 AIR_COOLING = 0x00, 508 LIQUID_COOLING = 0x01 509 }; 510 511 struct atom_firmware_info_v3_2 { 512 struct atom_common_table_header table_header; 513 uint32_t firmware_revision; 514 uint32_t bootup_sclk_in10khz; 515 uint32_t bootup_mclk_in10khz; 516 uint32_t firmware_capability; // enum atombios_firmware_capability 517 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ 518 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address 519 uint16_t bootup_vddc_mv; 520 uint16_t bootup_vddci_mv; 521 uint16_t bootup_mvddc_mv; 522 uint16_t bootup_vddgfx_mv; 523 uint8_t mem_module_id; 524 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ 525 uint8_t reserved1[2]; 526 uint32_t mc_baseaddr_high; 527 uint32_t mc_baseaddr_low; 528 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def 529 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id 530 uint8_t board_i2c_feature_slave_addr; 531 uint8_t reserved3; 532 uint16_t bootup_mvddq_mv; 533 uint16_t bootup_mvpp_mv; 534 uint32_t zfbstartaddrin16mb; 535 uint32_t reserved2[3]; 536 }; 537 538 struct atom_firmware_info_v3_3 539 { 540 struct atom_common_table_header table_header; 541 uint32_t firmware_revision; 542 uint32_t bootup_sclk_in10khz; 543 uint32_t bootup_mclk_in10khz; 544 uint32_t firmware_capability; // enum atombios_firmware_capability 545 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ 546 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address 547 uint16_t bootup_vddc_mv; 548 uint16_t bootup_vddci_mv; 549 uint16_t bootup_mvddc_mv; 550 uint16_t bootup_vddgfx_mv; 551 uint8_t mem_module_id; 552 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ 553 uint8_t reserved1[2]; 554 uint32_t mc_baseaddr_high; 555 uint32_t mc_baseaddr_low; 556 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def 557 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id 558 uint8_t board_i2c_feature_slave_addr; 559 uint8_t reserved3; 560 uint16_t bootup_mvddq_mv; 561 uint16_t bootup_mvpp_mv; 562 uint32_t zfbstartaddrin16mb; 563 uint32_t pplib_pptable_id; // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS 564 uint32_t reserved2[2]; 565 }; 566 567 /* 568 *************************************************************************** 569 Data Table lcd_info structure 570 *************************************************************************** 571 */ 572 573 struct lcd_info_v2_1 574 { 575 struct atom_common_table_header table_header; 576 struct atom_dtd_format lcd_timing; 577 uint16_t backlight_pwm; 578 uint16_t special_handle_cap; 579 uint16_t panel_misc; 580 uint16_t lvds_max_slink_pclk; 581 uint16_t lvds_ss_percentage; 582 uint16_t lvds_ss_rate_10hz; 583 uint8_t pwr_on_digon_to_de; /*all pwr sequence numbers below are in uint of 4ms*/ 584 uint8_t pwr_on_de_to_vary_bl; 585 uint8_t pwr_down_vary_bloff_to_de; 586 uint8_t pwr_down_de_to_digoff; 587 uint8_t pwr_off_delay; 588 uint8_t pwr_on_vary_bl_to_blon; 589 uint8_t pwr_down_bloff_to_vary_bloff; 590 uint8_t panel_bpc; 591 uint8_t dpcd_edp_config_cap; 592 uint8_t dpcd_max_link_rate; 593 uint8_t dpcd_max_lane_count; 594 uint8_t dpcd_max_downspread; 595 uint8_t min_allowed_bl_level; 596 uint8_t max_allowed_bl_level; 597 uint8_t bootup_bl_level; 598 uint8_t dplvdsrxid; 599 uint32_t reserved1[8]; 600 }; 601 602 /* lcd_info_v2_1.panel_misc defintion */ 603 enum atom_lcd_info_panel_misc{ 604 ATOM_PANEL_MISC_FPDI =0x0002, 605 }; 606 607 //uceDPToLVDSRxId 608 enum atom_lcd_info_dptolvds_rx_id 609 { 610 eDP_TO_LVDS_RX_DISABLE = 0x00, // no eDP->LVDS translator chip 611 eDP_TO_LVDS_COMMON_ID = 0x01, // common eDP->LVDS translator chip without AMD SW init 612 eDP_TO_LVDS_REALTEK_ID = 0x02, // Realtek tansaltor which require AMD SW init 613 }; 614 615 616 /* 617 *************************************************************************** 618 Data Table gpio_pin_lut structure 619 *************************************************************************** 620 */ 621 622 struct atom_gpio_pin_assignment 623 { 624 uint32_t data_a_reg_index; 625 uint8_t gpio_bitshift; 626 uint8_t gpio_mask_bitshift; 627 uint8_t gpio_id; 628 uint8_t reserved; 629 }; 630 631 /* atom_gpio_pin_assignment.gpio_id definition */ 632 enum atom_gpio_pin_assignment_gpio_id { 633 I2C_HW_LANE_MUX =0x0f, /* only valid when bit7=1 */ 634 I2C_HW_ENGINE_ID_MASK =0x70, /* only valid when bit7=1 */ 635 I2C_HW_CAP =0x80, /*only when the I2C_HW_CAP is set, the pin ID is assigned to an I2C pin pair, otherwise, it's an generic GPIO pin */ 636 637 /* gpio_id pre-define id for multiple usage */ 638 /* GPIO use to control PCIE_VDDC in certain SLT board */ 639 PCIE_VDDC_CONTROL_GPIO_PINID = 56, 640 /* if PP_AC_DC_SWITCH_GPIO_PINID in Gpio_Pin_LutTable, AC/DC swithing feature is enable */ 641 PP_AC_DC_SWITCH_GPIO_PINID = 60, 642 /* VDDC_REGULATOR_VRHOT_GPIO_PINID in Gpio_Pin_LutTable, VRHot feature is enable */ 643 VDDC_VRHOT_GPIO_PINID = 61, 644 /*if VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled */ 645 VDDC_PCC_GPIO_PINID = 62, 646 /* Only used on certain SLT/PA board to allow utility to cut Efuse. */ 647 EFUSE_CUT_ENABLE_GPIO_PINID = 63, 648 /* ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses for memory self refresh (ucGPIO=0, DRAM self-refresh; ucGPIO= */ 649 DRAM_SELF_REFRESH_GPIO_PINID = 64, 650 /* Thermal interrupt output->system thermal chip GPIO pin */ 651 THERMAL_INT_OUTPUT_GPIO_PINID =65, 652 }; 653 654 655 struct atom_gpio_pin_lut_v2_1 656 { 657 struct atom_common_table_header table_header; 658 /*the real number of this included in the structure is calcualted by using the (whole structure size - the header size)/size of atom_gpio_pin_lut */ 659 struct atom_gpio_pin_assignment gpio_pin[8]; 660 }; 661 662 663 /* 664 *************************************************************************** 665 Data Table vram_usagebyfirmware structure 666 *************************************************************************** 667 */ 668 669 struct vram_usagebyfirmware_v2_1 670 { 671 struct atom_common_table_header table_header; 672 uint32_t start_address_in_kb; 673 uint16_t used_by_firmware_in_kb; 674 uint16_t used_by_driver_in_kb; 675 }; 676 677 678 /* 679 *************************************************************************** 680 Data Table displayobjectinfo structure 681 *************************************************************************** 682 */ 683 684 enum atom_object_record_type_id 685 { 686 ATOM_I2C_RECORD_TYPE =1, 687 ATOM_HPD_INT_RECORD_TYPE =2, 688 ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE =9, 689 ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE =16, 690 ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE =17, 691 ATOM_ENCODER_CAP_RECORD_TYPE=20, 692 ATOM_BRACKET_LAYOUT_RECORD_TYPE=21, 693 ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE=22, 694 ATOM_RECORD_END_TYPE =0xFF, 695 }; 696 697 struct atom_common_record_header 698 { 699 uint8_t record_type; //An emun to indicate the record type 700 uint8_t record_size; //The size of the whole record in byte 701 }; 702 703 struct atom_i2c_record 704 { 705 struct atom_common_record_header record_header; //record_type = ATOM_I2C_RECORD_TYPE 706 uint8_t i2c_id; 707 uint8_t i2c_slave_addr; //The slave address, it's 0 when the record is attached to connector for DDC 708 }; 709 710 struct atom_hpd_int_record 711 { 712 struct atom_common_record_header record_header; //record_type = ATOM_HPD_INT_RECORD_TYPE 713 uint8_t pin_id; //Corresponding block in GPIO_PIN_INFO table gives the pin info 714 uint8_t plugin_pin_state; 715 }; 716 717 // Bit maps for ATOM_ENCODER_CAP_RECORD.usEncoderCap 718 enum atom_encoder_caps_def 719 { 720 ATOM_ENCODER_CAP_RECORD_HBR2 =0x01, // DP1.2 HBR2 is supported by HW encoder, it is retired in NI. the real meaning from SI is MST_EN 721 ATOM_ENCODER_CAP_RECORD_MST_EN =0x01, // from SI, this bit means DP MST is enable or not. 722 ATOM_ENCODER_CAP_RECORD_HBR2_EN =0x02, // DP1.2 HBR2 setting is qualified and HBR2 can be enabled 723 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN =0x04, // HDMI2.0 6Gbps enable or not. 724 ATOM_ENCODER_CAP_RECORD_HBR3_EN =0x08, // DP1.3 HBR3 is supported by board. 725 ATOM_ENCODER_CAP_RECORD_USB_C_TYPE =0x100, // the DP connector is a USB-C type. 726 }; 727 728 struct atom_encoder_caps_record 729 { 730 struct atom_common_record_header record_header; //record_type = ATOM_ENCODER_CAP_RECORD_TYPE 731 uint32_t encodercaps; 732 }; 733 734 enum atom_connector_caps_def 735 { 736 ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY = 0x01, //a cap bit to indicate that this non-embedded display connector is an internal display 737 ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL = 0x02, //a cap bit to indicate that this internal display requires BL control from GPU, refers to lcd_info for BL PWM freq 738 }; 739 740 struct atom_disp_connector_caps_record 741 { 742 struct atom_common_record_header record_header; 743 uint32_t connectcaps; 744 }; 745 746 //The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually 747 struct atom_gpio_pin_control_pair 748 { 749 uint8_t gpio_id; // GPIO_ID, find the corresponding ID in GPIO_LUT table 750 uint8_t gpio_pinstate; // Pin state showing how to set-up the pin 751 }; 752 753 struct atom_object_gpio_cntl_record 754 { 755 struct atom_common_record_header record_header; 756 uint8_t flag; // Future expnadibility 757 uint8_t number_of_pins; // Number of GPIO pins used to control the object 758 struct atom_gpio_pin_control_pair gpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins 759 }; 760 761 //Definitions for GPIO pin state 762 enum atom_gpio_pin_control_pinstate_def 763 { 764 GPIO_PIN_TYPE_INPUT = 0x00, 765 GPIO_PIN_TYPE_OUTPUT = 0x10, 766 GPIO_PIN_TYPE_HW_CONTROL = 0x20, 767 768 //For GPIO_PIN_TYPE_OUTPUT the following is defined 769 GPIO_PIN_OUTPUT_STATE_MASK = 0x01, 770 GPIO_PIN_OUTPUT_STATE_SHIFT = 0, 771 GPIO_PIN_STATE_ACTIVE_LOW = 0x0, 772 GPIO_PIN_STATE_ACTIVE_HIGH = 0x1, 773 }; 774 775 // Indexes to GPIO array in GLSync record 776 // GLSync record is for Frame Lock/Gen Lock feature. 777 enum atom_glsync_record_gpio_index_def 778 { 779 ATOM_GPIO_INDEX_GLSYNC_REFCLK = 0, 780 ATOM_GPIO_INDEX_GLSYNC_HSYNC = 1, 781 ATOM_GPIO_INDEX_GLSYNC_VSYNC = 2, 782 ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ = 3, 783 ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT = 4, 784 ATOM_GPIO_INDEX_GLSYNC_INTERRUPT = 5, 785 ATOM_GPIO_INDEX_GLSYNC_V_RESET = 6, 786 ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL = 7, 787 ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL = 8, 788 ATOM_GPIO_INDEX_GLSYNC_MAX = 9, 789 }; 790 791 792 struct atom_connector_hpdpin_lut_record //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 793 { 794 struct atom_common_record_header record_header; 795 uint8_t hpd_pin_map[8]; 796 }; 797 798 struct atom_connector_auxddc_lut_record //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 799 { 800 struct atom_common_record_header record_header; 801 uint8_t aux_ddc_map[8]; 802 }; 803 804 struct atom_connector_forced_tmds_cap_record 805 { 806 struct atom_common_record_header record_header; 807 // override TMDS capability on this connector when it operate in TMDS mode. usMaxTmdsClkRate = max TMDS Clock in Mhz/2.5 808 uint8_t maxtmdsclkrate_in2_5mhz; 809 uint8_t reserved; 810 }; 811 812 struct atom_connector_layout_info 813 { 814 uint16_t connectorobjid; 815 uint8_t connector_type; 816 uint8_t position; 817 }; 818 819 // define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector size 820 enum atom_connector_layout_info_connector_type_def 821 { 822 CONNECTOR_TYPE_DVI_D = 1, 823 824 CONNECTOR_TYPE_HDMI = 4, 825 CONNECTOR_TYPE_DISPLAY_PORT = 5, 826 CONNECTOR_TYPE_MINI_DISPLAY_PORT = 6, 827 }; 828 829 struct atom_bracket_layout_record 830 { 831 struct atom_common_record_header record_header; 832 uint8_t bracketlen; 833 uint8_t bracketwidth; 834 uint8_t conn_num; 835 uint8_t reserved; 836 struct atom_connector_layout_info conn_info[1]; 837 }; 838 839 enum atom_display_device_tag_def{ 840 ATOM_DISPLAY_LCD1_SUPPORT = 0x0002, //an embedded display is either an LVDS or eDP signal type of display 841 ATOM_DISPLAY_DFP1_SUPPORT = 0x0008, 842 ATOM_DISPLAY_DFP2_SUPPORT = 0x0080, 843 ATOM_DISPLAY_DFP3_SUPPORT = 0x0200, 844 ATOM_DISPLAY_DFP4_SUPPORT = 0x0400, 845 ATOM_DISPLAY_DFP5_SUPPORT = 0x0800, 846 ATOM_DISPLAY_DFP6_SUPPORT = 0x0040, 847 ATOM_DISPLAY_DFPx_SUPPORT = 0x0ec8, 848 }; 849 850 struct atom_display_object_path_v2 851 { 852 uint16_t display_objid; //Connector Object ID or Misc Object ID 853 uint16_t disp_recordoffset; 854 uint16_t encoderobjid; //first encoder closer to the connector, could be either an external or intenal encoder 855 uint16_t extencoderobjid; //2nd encoder after the first encoder, from the connector point of view; 856 uint16_t encoder_recordoffset; 857 uint16_t extencoder_recordoffset; 858 uint16_t device_tag; //a supported device vector, each display path starts with this.the paths are enumerated in the way of priority, a path appears first 859 uint8_t priority_id; 860 uint8_t reserved; 861 }; 862 863 struct display_object_info_table_v1_4 864 { 865 struct atom_common_table_header table_header; 866 uint16_t supporteddevices; 867 uint8_t number_of_path; 868 uint8_t reserved; 869 struct atom_display_object_path_v2 display_path[8]; //the real number of this included in the structure is calculated by using the (whole structure size - the header size- number_of_path)/size of atom_display_object_path 870 }; 871 872 873 /* 874 *************************************************************************** 875 Data Table dce_info structure 876 *************************************************************************** 877 */ 878 struct atom_display_controller_info_v4_1 879 { 880 struct atom_common_table_header table_header; 881 uint32_t display_caps; 882 uint32_t bootup_dispclk_10khz; 883 uint16_t dce_refclk_10khz; 884 uint16_t i2c_engine_refclk_10khz; 885 uint16_t dvi_ss_percentage; // in unit of 0.001% 886 uint16_t dvi_ss_rate_10hz; 887 uint16_t hdmi_ss_percentage; // in unit of 0.001% 888 uint16_t hdmi_ss_rate_10hz; 889 uint16_t dp_ss_percentage; // in unit of 0.001% 890 uint16_t dp_ss_rate_10hz; 891 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode 892 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode 893 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode 894 uint8_t ss_reserved; 895 uint8_t hardcode_mode_num; // a hardcode mode number defined in StandardVESA_TimingTable when a CRT or DFP EDID is not available 896 uint8_t reserved1[3]; 897 uint16_t dpphy_refclk_10khz; 898 uint16_t reserved2; 899 uint8_t dceip_min_ver; 900 uint8_t dceip_max_ver; 901 uint8_t max_disp_pipe_num; 902 uint8_t max_vbios_active_disp_pipe_num; 903 uint8_t max_ppll_num; 904 uint8_t max_disp_phy_num; 905 uint8_t max_aux_pairs; 906 uint8_t remotedisplayconfig; 907 uint8_t reserved3[8]; 908 }; 909 910 911 struct atom_display_controller_info_v4_2 912 { 913 struct atom_common_table_header table_header; 914 uint32_t display_caps; 915 uint32_t bootup_dispclk_10khz; 916 uint16_t dce_refclk_10khz; 917 uint16_t i2c_engine_refclk_10khz; 918 uint16_t dvi_ss_percentage; // in unit of 0.001% 919 uint16_t dvi_ss_rate_10hz; 920 uint16_t hdmi_ss_percentage; // in unit of 0.001% 921 uint16_t hdmi_ss_rate_10hz; 922 uint16_t dp_ss_percentage; // in unit of 0.001% 923 uint16_t dp_ss_rate_10hz; 924 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode 925 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode 926 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode 927 uint8_t ss_reserved; 928 uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available 929 uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available 930 uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 931 uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 932 uint16_t dpphy_refclk_10khz; 933 uint16_t reserved2; 934 uint8_t dcnip_min_ver; 935 uint8_t dcnip_max_ver; 936 uint8_t max_disp_pipe_num; 937 uint8_t max_vbios_active_disp_pipe_num; 938 uint8_t max_ppll_num; 939 uint8_t max_disp_phy_num; 940 uint8_t max_aux_pairs; 941 uint8_t remotedisplayconfig; 942 uint8_t reserved3[8]; 943 }; 944 945 946 enum dce_info_caps_def 947 { 948 // only for VBIOS 949 DCE_INFO_CAPS_FORCE_DISPDEV_CONNECTED =0x02, 950 // only for VBIOS 951 DCE_INFO_CAPS_DISABLE_DFP_DP_HBR2 =0x04, 952 // only for VBIOS 953 DCE_INFO_CAPS_ENABLE_INTERLAC_TIMING =0x08, 954 955 }; 956 957 /* 958 *************************************************************************** 959 Data Table ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO structure 960 *************************************************************************** 961 */ 962 struct atom_ext_display_path 963 { 964 uint16_t device_tag; //A bit vector to show what devices are supported 965 uint16_t device_acpi_enum; //16bit device ACPI id. 966 uint16_t connectorobjid; //A physical connector for displays to plug in, using object connector definitions 967 uint8_t auxddclut_index; //An index into external AUX/DDC channel LUT 968 uint8_t hpdlut_index; //An index into external HPD pin LUT 969 uint16_t ext_encoder_objid; //external encoder object id 970 uint8_t channelmapping; // if ucChannelMapping=0, using default one to one mapping 971 uint8_t chpninvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted 972 uint16_t caps; 973 uint16_t reserved; 974 }; 975 976 //usCaps 977 enum ext_display_path_cap_def 978 { 979 EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE =0x0001, 980 EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN =0x0002, 981 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK =0x007C, 982 }; 983 984 struct atom_external_display_connection_info 985 { 986 struct atom_common_table_header table_header; 987 uint8_t guid[16]; // a GUID is a 16 byte long string 988 struct atom_ext_display_path path[7]; // total of fixed 7 entries. 989 uint8_t checksum; // a simple Checksum of the sum of whole structure equal to 0x0. 990 uint8_t stereopinid; // use for eDP panel 991 uint8_t remotedisplayconfig; 992 uint8_t edptolvdsrxid; 993 uint8_t fixdpvoltageswing; // usCaps[1]=1, this indicate DP_LANE_SET value 994 uint8_t reserved[3]; // for potential expansion 995 }; 996 997 /* 998 *************************************************************************** 999 Data Table integratedsysteminfo structure 1000 *************************************************************************** 1001 */ 1002 1003 struct atom_camera_dphy_timing_param 1004 { 1005 uint8_t profile_id; // SENSOR_PROFILES 1006 uint32_t param; 1007 }; 1008 1009 struct atom_camera_dphy_elec_param 1010 { 1011 uint16_t param[3]; 1012 }; 1013 1014 struct atom_camera_module_info 1015 { 1016 uint8_t module_id; // 0: Rear, 1: Front right of user, 2: Front left of user 1017 uint8_t module_name[8]; 1018 struct atom_camera_dphy_timing_param timingparam[6]; // Exact number is under estimation and confirmation from sensor vendor 1019 }; 1020 1021 struct atom_camera_flashlight_info 1022 { 1023 uint8_t flashlight_id; // 0: Rear, 1: Front 1024 uint8_t name[8]; 1025 }; 1026 1027 struct atom_camera_data 1028 { 1029 uint32_t versionCode; 1030 struct atom_camera_module_info cameraInfo[3]; // Assuming 3 camera sensors max 1031 struct atom_camera_flashlight_info flashInfo; // Assuming 1 flashlight max 1032 struct atom_camera_dphy_elec_param dphy_param; 1033 uint32_t crc_val; // CRC 1034 }; 1035 1036 1037 struct atom_14nm_dpphy_dvihdmi_tuningset 1038 { 1039 uint32_t max_symclk_in10khz; 1040 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode 1041 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 1042 uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom 1043 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4 1044 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset 1045 uint8_t tx_driver_fifty_ohms; //COMMON_ZCALCODE_CTRL[21].tx_driver_fifty_ohms 1046 uint8_t deemph_sel; //MARGIN_DEEMPH_LANE0.DEEMPH_SEL 1047 }; 1048 1049 struct atom_14nm_dpphy_dp_setting{ 1050 uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def 1051 uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom 1052 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4 1053 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset 1054 }; 1055 1056 struct atom_14nm_dpphy_dp_tuningset{ 1057 uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 1058 uint8_t version; 1059 uint16_t table_size; // size of atom_14nm_dpphy_dp_tuningset 1060 uint16_t reserved; 1061 struct atom_14nm_dpphy_dp_setting dptuning[10]; 1062 }; 1063 1064 struct atom_14nm_dig_transmitter_info_header_v4_0{ 1065 struct atom_common_table_header table_header; 1066 uint16_t pcie_phy_tmds_hdmi_macro_settings_offset; // offset of PCIEPhyTMDSHDMIMacroSettingsTbl 1067 uint16_t uniphy_vs_emph_lookup_table_offset; // offset of UniphyVSEmphLookUpTbl 1068 uint16_t uniphy_xbar_settings_table_offset; // offset of UniphyXbarSettingsTbl 1069 }; 1070 1071 struct atom_14nm_combphy_tmds_vs_set 1072 { 1073 uint8_t sym_clk; 1074 uint8_t dig_mode; 1075 uint8_t phy_sel; 1076 uint16_t common_mar_deemph_nom__margin_deemph_val; 1077 uint8_t common_seldeemph60__deemph_6db_4_val; 1078 uint8_t cmd_bus_global_for_tx_lane0__boostadj_val ; 1079 uint8_t common_zcalcode_ctrl__tx_driver_fifty_ohms_val; 1080 uint8_t margin_deemph_lane0__deemph_sel_val; 1081 }; 1082 1083 struct atom_i2c_reg_info { 1084 uint8_t ucI2cRegIndex; 1085 uint8_t ucI2cRegVal; 1086 }; 1087 1088 struct atom_hdmi_retimer_redriver_set { 1089 uint8_t HdmiSlvAddr; 1090 uint8_t HdmiRegNum; 1091 uint8_t Hdmi6GRegNum; 1092 struct atom_i2c_reg_info HdmiRegSetting[9]; //For non 6G Hz use 1093 struct atom_i2c_reg_info Hdmi6GhzRegSetting[3]; //For 6G Hz use. 1094 }; 1095 1096 struct atom_integrated_system_info_v1_11 1097 { 1098 struct atom_common_table_header table_header; 1099 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def 1100 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def 1101 uint32_t system_config; 1102 uint32_t cpucapinfo; 1103 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1% 1104 uint16_t gpuclk_ss_type; 1105 uint16_t lvds_ss_percentage; //unit of 0.001%, 1000 mean 1% 1106 uint16_t lvds_ss_rate_10hz; 1107 uint16_t hdmi_ss_percentage; //unit of 0.001%, 1000 mean 1% 1108 uint16_t hdmi_ss_rate_10hz; 1109 uint16_t dvi_ss_percentage; //unit of 0.001%, 1000 mean 1% 1110 uint16_t dvi_ss_rate_10hz; 1111 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def 1112 uint16_t lvds_misc; // enum of atom_sys_info_lvds_misc_def 1113 uint16_t backlight_pwm_hz; // pwm frequency in hz 1114 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication. 1115 uint8_t umachannelnumber; // number of memory channels 1116 uint8_t pwr_on_digon_to_de; /* all pwr sequence numbers below are in uint of 4ms */ 1117 uint8_t pwr_on_de_to_vary_bl; 1118 uint8_t pwr_down_vary_bloff_to_de; 1119 uint8_t pwr_down_de_to_digoff; 1120 uint8_t pwr_off_delay; 1121 uint8_t pwr_on_vary_bl_to_blon; 1122 uint8_t pwr_down_bloff_to_vary_bloff; 1123 uint8_t min_allowed_bl_level; 1124 uint8_t htc_hyst_limit; 1125 uint8_t htc_tmp_limit; 1126 uint8_t reserved1; 1127 uint8_t reserved2; 1128 struct atom_external_display_connection_info extdispconninfo; 1129 struct atom_14nm_dpphy_dvihdmi_tuningset dvi_tuningset; 1130 struct atom_14nm_dpphy_dvihdmi_tuningset hdmi_tuningset; 1131 struct atom_14nm_dpphy_dvihdmi_tuningset hdmi6g_tuningset; 1132 struct atom_14nm_dpphy_dp_tuningset dp_tuningset; // rbr 1.62G dp tuning set 1133 struct atom_14nm_dpphy_dp_tuningset dp_hbr3_tuningset; // HBR3 dp tuning set 1134 struct atom_camera_data camera_info; 1135 struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0 1136 struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1 1137 struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2 1138 struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3 1139 struct atom_14nm_dpphy_dp_tuningset dp_hbr_tuningset; //hbr 2.7G dp tuning set 1140 struct atom_14nm_dpphy_dp_tuningset dp_hbr2_tuningset; //hbr2 5.4G dp turnig set 1141 struct atom_14nm_dpphy_dp_tuningset edp_tuningset; //edp tuning set 1142 uint32_t reserved[66]; 1143 }; 1144 1145 1146 // system_config 1147 enum atom_system_vbiosmisc_def{ 1148 INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT = 0x01, 1149 }; 1150 1151 1152 // gpucapinfo 1153 enum atom_system_gpucapinf_def{ 1154 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS = 0x10, 1155 }; 1156 1157 //dpphy_override 1158 enum atom_sysinfo_dpphy_override_def{ 1159 ATOM_ENABLE_DVI_TUNINGSET = 0x01, 1160 ATOM_ENABLE_HDMI_TUNINGSET = 0x02, 1161 ATOM_ENABLE_HDMI6G_TUNINGSET = 0x04, 1162 ATOM_ENABLE_DP_TUNINGSET = 0x08, 1163 ATOM_ENABLE_DP_HBR3_TUNINGSET = 0x10, 1164 }; 1165 1166 //lvds_misc 1167 enum atom_sys_info_lvds_misc_def 1168 { 1169 SYS_INFO_LVDS_MISC_888_FPDI_MODE =0x01, 1170 SYS_INFO_LVDS_MISC_888_BPC_MODE =0x04, 1171 SYS_INFO_LVDS_MISC_OVERRIDE_EN =0x08, 1172 }; 1173 1174 1175 //memorytype DMI Type 17 offset 12h - Memory Type 1176 enum atom_dmi_t17_mem_type_def{ 1177 OtherMemType = 0x01, ///< Assign 01 to Other 1178 UnknownMemType, ///< Assign 02 to Unknown 1179 DramMemType, ///< Assign 03 to DRAM 1180 EdramMemType, ///< Assign 04 to EDRAM 1181 VramMemType, ///< Assign 05 to VRAM 1182 SramMemType, ///< Assign 06 to SRAM 1183 RamMemType, ///< Assign 07 to RAM 1184 RomMemType, ///< Assign 08 to ROM 1185 FlashMemType, ///< Assign 09 to Flash 1186 EepromMemType, ///< Assign 10 to EEPROM 1187 FepromMemType, ///< Assign 11 to FEPROM 1188 EpromMemType, ///< Assign 12 to EPROM 1189 CdramMemType, ///< Assign 13 to CDRAM 1190 ThreeDramMemType, ///< Assign 14 to 3DRAM 1191 SdramMemType, ///< Assign 15 to SDRAM 1192 SgramMemType, ///< Assign 16 to SGRAM 1193 RdramMemType, ///< Assign 17 to RDRAM 1194 DdrMemType, ///< Assign 18 to DDR 1195 Ddr2MemType, ///< Assign 19 to DDR2 1196 Ddr2FbdimmMemType, ///< Assign 20 to DDR2 FB-DIMM 1197 Ddr3MemType = 0x18, ///< Assign 24 to DDR3 1198 Fbd2MemType, ///< Assign 25 to FBD2 1199 Ddr4MemType, ///< Assign 26 to DDR4 1200 LpDdrMemType, ///< Assign 27 to LPDDR 1201 LpDdr2MemType, ///< Assign 28 to LPDDR2 1202 LpDdr3MemType, ///< Assign 29 to LPDDR3 1203 LpDdr4MemType, ///< Assign 30 to LPDDR4 1204 }; 1205 1206 1207 // this Table is used starting from NL/AM, used by SBIOS and pass the IntegratedSystemInfoTable/PowerPlayInfoTable/SystemCameraInfoTable 1208 struct atom_fusion_system_info_v4 1209 { 1210 struct atom_integrated_system_info_v1_11 sysinfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition 1211 uint32_t powerplayinfo[256]; // Reserve 1024 bytes space for PowerPlayInfoTable 1212 }; 1213 1214 1215 /* 1216 *************************************************************************** 1217 Data Table gfx_info structure 1218 *************************************************************************** 1219 */ 1220 1221 struct atom_gfx_info_v2_2 1222 { 1223 struct atom_common_table_header table_header; 1224 uint8_t gfxip_min_ver; 1225 uint8_t gfxip_max_ver; 1226 uint8_t max_shader_engines; 1227 uint8_t max_tile_pipes; 1228 uint8_t max_cu_per_sh; 1229 uint8_t max_sh_per_se; 1230 uint8_t max_backends_per_se; 1231 uint8_t max_texture_channel_caches; 1232 uint32_t regaddr_cp_dma_src_addr; 1233 uint32_t regaddr_cp_dma_src_addr_hi; 1234 uint32_t regaddr_cp_dma_dst_addr; 1235 uint32_t regaddr_cp_dma_dst_addr_hi; 1236 uint32_t regaddr_cp_dma_command; 1237 uint32_t regaddr_cp_status; 1238 uint32_t regaddr_rlc_gpu_clock_32; 1239 uint32_t rlc_gpu_timer_refclk; 1240 }; 1241 1242 struct atom_gfx_info_v2_3 { 1243 struct atom_common_table_header table_header; 1244 uint8_t gfxip_min_ver; 1245 uint8_t gfxip_max_ver; 1246 uint8_t max_shader_engines; 1247 uint8_t max_tile_pipes; 1248 uint8_t max_cu_per_sh; 1249 uint8_t max_sh_per_se; 1250 uint8_t max_backends_per_se; 1251 uint8_t max_texture_channel_caches; 1252 uint32_t regaddr_cp_dma_src_addr; 1253 uint32_t regaddr_cp_dma_src_addr_hi; 1254 uint32_t regaddr_cp_dma_dst_addr; 1255 uint32_t regaddr_cp_dma_dst_addr_hi; 1256 uint32_t regaddr_cp_dma_command; 1257 uint32_t regaddr_cp_status; 1258 uint32_t regaddr_rlc_gpu_clock_32; 1259 uint32_t rlc_gpu_timer_refclk; 1260 uint8_t active_cu_per_sh; 1261 uint8_t active_rb_per_se; 1262 uint16_t gcgoldenoffset; 1263 uint32_t rm21_sram_vmin_value; 1264 }; 1265 1266 struct atom_gfx_info_v2_4 1267 { 1268 struct atom_common_table_header table_header; 1269 uint8_t gfxip_min_ver; 1270 uint8_t gfxip_max_ver; 1271 uint8_t max_shader_engines; 1272 uint8_t reserved; 1273 uint8_t max_cu_per_sh; 1274 uint8_t max_sh_per_se; 1275 uint8_t max_backends_per_se; 1276 uint8_t max_texture_channel_caches; 1277 uint32_t regaddr_cp_dma_src_addr; 1278 uint32_t regaddr_cp_dma_src_addr_hi; 1279 uint32_t regaddr_cp_dma_dst_addr; 1280 uint32_t regaddr_cp_dma_dst_addr_hi; 1281 uint32_t regaddr_cp_dma_command; 1282 uint32_t regaddr_cp_status; 1283 uint32_t regaddr_rlc_gpu_clock_32; 1284 uint32_t rlc_gpu_timer_refclk; 1285 uint8_t active_cu_per_sh; 1286 uint8_t active_rb_per_se; 1287 uint16_t gcgoldenoffset; 1288 uint16_t gc_num_gprs; 1289 uint16_t gc_gsprim_buff_depth; 1290 uint16_t gc_parameter_cache_depth; 1291 uint16_t gc_wave_size; 1292 uint16_t gc_max_waves_per_simd; 1293 uint16_t gc_lds_size; 1294 uint8_t gc_num_max_gs_thds; 1295 uint8_t gc_gs_table_depth; 1296 uint8_t gc_double_offchip_lds_buffer; 1297 uint8_t gc_max_scratch_slots_per_cu; 1298 uint32_t sram_rm_fuses_val; 1299 uint32_t sram_custom_rm_fuses_val; 1300 }; 1301 1302 /* 1303 *************************************************************************** 1304 Data Table smu_info structure 1305 *************************************************************************** 1306 */ 1307 struct atom_smu_info_v3_1 1308 { 1309 struct atom_common_table_header table_header; 1310 uint8_t smuip_min_ver; 1311 uint8_t smuip_max_ver; 1312 uint8_t smu_rsd1; 1313 uint8_t gpuclk_ss_mode; // enum of atom_spread_spectrum_mode 1314 uint16_t sclk_ss_percentage; 1315 uint16_t sclk_ss_rate_10hz; 1316 uint16_t gpuclk_ss_percentage; // in unit of 0.001% 1317 uint16_t gpuclk_ss_rate_10hz; 1318 uint32_t core_refclk_10khz; 1319 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid 1320 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching 1321 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid 1322 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event 1323 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid 1324 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event 1325 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid 1326 uint8_t fw_ctf_polarity; // GPIO polarity for CTF 1327 }; 1328 1329 struct atom_smu_info_v3_2 { 1330 struct atom_common_table_header table_header; 1331 uint8_t smuip_min_ver; 1332 uint8_t smuip_max_ver; 1333 uint8_t smu_rsd1; 1334 uint8_t gpuclk_ss_mode; 1335 uint16_t sclk_ss_percentage; 1336 uint16_t sclk_ss_rate_10hz; 1337 uint16_t gpuclk_ss_percentage; // in unit of 0.001% 1338 uint16_t gpuclk_ss_rate_10hz; 1339 uint32_t core_refclk_10khz; 1340 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid 1341 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching 1342 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid 1343 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event 1344 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid 1345 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event 1346 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid 1347 uint8_t fw_ctf_polarity; // GPIO polarity for CTF 1348 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid 1349 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF 1350 uint16_t smugoldenoffset; 1351 uint32_t gpupll_vco_freq_10khz; 1352 uint32_t bootup_smnclk_10khz; 1353 uint32_t bootup_socclk_10khz; 1354 uint32_t bootup_mp0clk_10khz; 1355 uint32_t bootup_mp1clk_10khz; 1356 uint32_t bootup_lclk_10khz; 1357 uint32_t bootup_dcefclk_10khz; 1358 uint32_t ctf_threshold_override_value; 1359 uint32_t reserved[5]; 1360 }; 1361 1362 struct atom_smu_info_v3_3 { 1363 struct atom_common_table_header table_header; 1364 uint8_t smuip_min_ver; 1365 uint8_t smuip_max_ver; 1366 uint8_t waflclk_ss_mode; 1367 uint8_t gpuclk_ss_mode; 1368 uint16_t sclk_ss_percentage; 1369 uint16_t sclk_ss_rate_10hz; 1370 uint16_t gpuclk_ss_percentage; // in unit of 0.001% 1371 uint16_t gpuclk_ss_rate_10hz; 1372 uint32_t core_refclk_10khz; 1373 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid 1374 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching 1375 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid 1376 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event 1377 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid 1378 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event 1379 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid 1380 uint8_t fw_ctf_polarity; // GPIO polarity for CTF 1381 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid 1382 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF 1383 uint16_t smugoldenoffset; 1384 uint32_t gpupll_vco_freq_10khz; 1385 uint32_t bootup_smnclk_10khz; 1386 uint32_t bootup_socclk_10khz; 1387 uint32_t bootup_mp0clk_10khz; 1388 uint32_t bootup_mp1clk_10khz; 1389 uint32_t bootup_lclk_10khz; 1390 uint32_t bootup_dcefclk_10khz; 1391 uint32_t ctf_threshold_override_value; 1392 uint32_t syspll3_0_vco_freq_10khz; 1393 uint32_t syspll3_1_vco_freq_10khz; 1394 uint32_t bootup_fclk_10khz; 1395 uint32_t bootup_waflclk_10khz; 1396 uint32_t smu_info_caps; 1397 uint16_t waflclk_ss_percentage; // in unit of 0.001% 1398 uint16_t smuinitoffset; 1399 uint32_t reserved; 1400 }; 1401 1402 /* 1403 *************************************************************************** 1404 Data Table smc_dpm_info structure 1405 *************************************************************************** 1406 */ 1407 struct atom_smc_dpm_info_v4_1 1408 { 1409 struct atom_common_table_header table_header; 1410 uint8_t liquid1_i2c_address; 1411 uint8_t liquid2_i2c_address; 1412 uint8_t vr_i2c_address; 1413 uint8_t plx_i2c_address; 1414 1415 uint8_t liquid_i2c_linescl; 1416 uint8_t liquid_i2c_linesda; 1417 uint8_t vr_i2c_linescl; 1418 uint8_t vr_i2c_linesda; 1419 1420 uint8_t plx_i2c_linescl; 1421 uint8_t plx_i2c_linesda; 1422 uint8_t vrsensorpresent; 1423 uint8_t liquidsensorpresent; 1424 1425 uint16_t maxvoltagestepgfx; 1426 uint16_t maxvoltagestepsoc; 1427 1428 uint8_t vddgfxvrmapping; 1429 uint8_t vddsocvrmapping; 1430 uint8_t vddmem0vrmapping; 1431 uint8_t vddmem1vrmapping; 1432 1433 uint8_t gfxulvphasesheddingmask; 1434 uint8_t soculvphasesheddingmask; 1435 uint8_t padding8_v[2]; 1436 1437 uint16_t gfxmaxcurrent; 1438 uint8_t gfxoffset; 1439 uint8_t padding_telemetrygfx; 1440 1441 uint16_t socmaxcurrent; 1442 uint8_t socoffset; 1443 uint8_t padding_telemetrysoc; 1444 1445 uint16_t mem0maxcurrent; 1446 uint8_t mem0offset; 1447 uint8_t padding_telemetrymem0; 1448 1449 uint16_t mem1maxcurrent; 1450 uint8_t mem1offset; 1451 uint8_t padding_telemetrymem1; 1452 1453 uint8_t acdcgpio; 1454 uint8_t acdcpolarity; 1455 uint8_t vr0hotgpio; 1456 uint8_t vr0hotpolarity; 1457 1458 uint8_t vr1hotgpio; 1459 uint8_t vr1hotpolarity; 1460 uint8_t padding1; 1461 uint8_t padding2; 1462 1463 uint8_t ledpin0; 1464 uint8_t ledpin1; 1465 uint8_t ledpin2; 1466 uint8_t padding8_4; 1467 1468 uint8_t pllgfxclkspreadenabled; 1469 uint8_t pllgfxclkspreadpercent; 1470 uint16_t pllgfxclkspreadfreq; 1471 1472 uint8_t uclkspreadenabled; 1473 uint8_t uclkspreadpercent; 1474 uint16_t uclkspreadfreq; 1475 1476 uint8_t socclkspreadenabled; 1477 uint8_t socclkspreadpercent; 1478 uint16_t socclkspreadfreq; 1479 1480 uint8_t acggfxclkspreadenabled; 1481 uint8_t acggfxclkspreadpercent; 1482 uint16_t acggfxclkspreadfreq; 1483 1484 uint8_t Vr2_I2C_address; 1485 uint8_t padding_vr2[3]; 1486 1487 uint32_t boardreserved[9]; 1488 }; 1489 1490 /* 1491 *************************************************************************** 1492 Data Table smc_dpm_info structure 1493 *************************************************************************** 1494 */ 1495 struct atom_smc_dpm_info_v4_3 1496 { 1497 struct atom_common_table_header table_header; 1498 uint8_t liquid1_i2c_address; 1499 uint8_t liquid2_i2c_address; 1500 uint8_t vr_i2c_address; 1501 uint8_t plx_i2c_address; 1502 1503 uint8_t liquid_i2c_linescl; 1504 uint8_t liquid_i2c_linesda; 1505 uint8_t vr_i2c_linescl; 1506 uint8_t vr_i2c_linesda; 1507 1508 uint8_t plx_i2c_linescl; 1509 uint8_t plx_i2c_linesda; 1510 uint8_t vrsensorpresent; 1511 uint8_t liquidsensorpresent; 1512 1513 uint16_t maxvoltagestepgfx; 1514 uint16_t maxvoltagestepsoc; 1515 1516 uint8_t vddgfxvrmapping; 1517 uint8_t vddsocvrmapping; 1518 uint8_t vddmem0vrmapping; 1519 uint8_t vddmem1vrmapping; 1520 1521 uint8_t gfxulvphasesheddingmask; 1522 uint8_t soculvphasesheddingmask; 1523 uint8_t externalsensorpresent; 1524 uint8_t padding8_v; 1525 1526 uint16_t gfxmaxcurrent; 1527 uint8_t gfxoffset; 1528 uint8_t padding_telemetrygfx; 1529 1530 uint16_t socmaxcurrent; 1531 uint8_t socoffset; 1532 uint8_t padding_telemetrysoc; 1533 1534 uint16_t mem0maxcurrent; 1535 uint8_t mem0offset; 1536 uint8_t padding_telemetrymem0; 1537 1538 uint16_t mem1maxcurrent; 1539 uint8_t mem1offset; 1540 uint8_t padding_telemetrymem1; 1541 1542 uint8_t acdcgpio; 1543 uint8_t acdcpolarity; 1544 uint8_t vr0hotgpio; 1545 uint8_t vr0hotpolarity; 1546 1547 uint8_t vr1hotgpio; 1548 uint8_t vr1hotpolarity; 1549 uint8_t padding1; 1550 uint8_t padding2; 1551 1552 uint8_t ledpin0; 1553 uint8_t ledpin1; 1554 uint8_t ledpin2; 1555 uint8_t padding8_4; 1556 1557 uint8_t pllgfxclkspreadenabled; 1558 uint8_t pllgfxclkspreadpercent; 1559 uint16_t pllgfxclkspreadfreq; 1560 1561 uint8_t uclkspreadenabled; 1562 uint8_t uclkspreadpercent; 1563 uint16_t uclkspreadfreq; 1564 1565 uint8_t fclkspreadenabled; 1566 uint8_t fclkspreadpercent; 1567 uint16_t fclkspreadfreq; 1568 1569 uint8_t fllgfxclkspreadenabled; 1570 uint8_t fllgfxclkspreadpercent; 1571 uint16_t fllgfxclkspreadfreq; 1572 1573 uint32_t boardreserved[10]; 1574 }; 1575 1576 struct smudpm_i2ccontrollerconfig_t { 1577 uint32_t enabled; 1578 uint32_t slaveaddress; 1579 uint32_t controllerport; 1580 uint32_t controllername; 1581 uint32_t thermalthrottler; 1582 uint32_t i2cprotocol; 1583 uint32_t i2cspeed; 1584 }; 1585 1586 struct atom_smc_dpm_info_v4_4 1587 { 1588 struct atom_common_table_header table_header; 1589 uint32_t i2c_padding[3]; 1590 1591 uint16_t maxvoltagestepgfx; 1592 uint16_t maxvoltagestepsoc; 1593 1594 uint8_t vddgfxvrmapping; 1595 uint8_t vddsocvrmapping; 1596 uint8_t vddmem0vrmapping; 1597 uint8_t vddmem1vrmapping; 1598 1599 uint8_t gfxulvphasesheddingmask; 1600 uint8_t soculvphasesheddingmask; 1601 uint8_t externalsensorpresent; 1602 uint8_t padding8_v; 1603 1604 uint16_t gfxmaxcurrent; 1605 uint8_t gfxoffset; 1606 uint8_t padding_telemetrygfx; 1607 1608 uint16_t socmaxcurrent; 1609 uint8_t socoffset; 1610 uint8_t padding_telemetrysoc; 1611 1612 uint16_t mem0maxcurrent; 1613 uint8_t mem0offset; 1614 uint8_t padding_telemetrymem0; 1615 1616 uint16_t mem1maxcurrent; 1617 uint8_t mem1offset; 1618 uint8_t padding_telemetrymem1; 1619 1620 1621 uint8_t acdcgpio; 1622 uint8_t acdcpolarity; 1623 uint8_t vr0hotgpio; 1624 uint8_t vr0hotpolarity; 1625 1626 uint8_t vr1hotgpio; 1627 uint8_t vr1hotpolarity; 1628 uint8_t padding1; 1629 uint8_t padding2; 1630 1631 1632 uint8_t ledpin0; 1633 uint8_t ledpin1; 1634 uint8_t ledpin2; 1635 uint8_t padding8_4; 1636 1637 1638 uint8_t pllgfxclkspreadenabled; 1639 uint8_t pllgfxclkspreadpercent; 1640 uint16_t pllgfxclkspreadfreq; 1641 1642 1643 uint8_t uclkspreadenabled; 1644 uint8_t uclkspreadpercent; 1645 uint16_t uclkspreadfreq; 1646 1647 1648 uint8_t fclkspreadenabled; 1649 uint8_t fclkspreadpercent; 1650 uint16_t fclkspreadfreq; 1651 1652 1653 uint8_t fllgfxclkspreadenabled; 1654 uint8_t fllgfxclkspreadpercent; 1655 uint16_t fllgfxclkspreadfreq; 1656 1657 1658 struct smudpm_i2ccontrollerconfig_t i2ccontrollers[7]; 1659 1660 1661 uint32_t boardreserved[10]; 1662 }; 1663 1664 enum smudpm_v4_5_i2ccontrollername_e{ 1665 SMC_V4_5_I2C_CONTROLLER_NAME_VR_GFX = 0, 1666 SMC_V4_5_I2C_CONTROLLER_NAME_VR_SOC, 1667 SMC_V4_5_I2C_CONTROLLER_NAME_VR_VDDCI, 1668 SMC_V4_5_I2C_CONTROLLER_NAME_VR_MVDD, 1669 SMC_V4_5_I2C_CONTROLLER_NAME_LIQUID0, 1670 SMC_V4_5_I2C_CONTROLLER_NAME_LIQUID1, 1671 SMC_V4_5_I2C_CONTROLLER_NAME_PLX, 1672 SMC_V4_5_I2C_CONTROLLER_NAME_SPARE, 1673 SMC_V4_5_I2C_CONTROLLER_NAME_COUNT, 1674 }; 1675 1676 enum smudpm_v4_5_i2ccontrollerthrottler_e{ 1677 SMC_V4_5_I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0, 1678 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_GFX, 1679 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_SOC, 1680 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_VDDCI, 1681 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_MVDD, 1682 SMC_V4_5_I2C_CONTROLLER_THROTTLER_LIQUID0, 1683 SMC_V4_5_I2C_CONTROLLER_THROTTLER_LIQUID1, 1684 SMC_V4_5_I2C_CONTROLLER_THROTTLER_PLX, 1685 SMC_V4_5_I2C_CONTROLLER_THROTTLER_COUNT, 1686 }; 1687 1688 enum smudpm_v4_5_i2ccontrollerprotocol_e{ 1689 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_VR_0, 1690 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_VR_1, 1691 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_TMP_0, 1692 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_TMP_1, 1693 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_SPARE_0, 1694 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_SPARE_1, 1695 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_COUNT, 1696 }; 1697 1698 struct smudpm_i2c_controller_config_v2 1699 { 1700 uint8_t Enabled; 1701 uint8_t Speed; 1702 uint8_t Padding[2]; 1703 uint32_t SlaveAddress; 1704 uint8_t ControllerPort; 1705 uint8_t ControllerName; 1706 uint8_t ThermalThrotter; 1707 uint8_t I2cProtocol; 1708 }; 1709 1710 struct atom_smc_dpm_info_v4_5 1711 { 1712 struct atom_common_table_header table_header; 1713 // SECTION: BOARD PARAMETERS 1714 // I2C Control 1715 struct smudpm_i2c_controller_config_v2 I2cControllers[8]; 1716 1717 // SVI2 Board Parameters 1718 uint16_t MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 1719 uint16_t MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 1720 1721 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 1722 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 1723 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 1724 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 1725 1726 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1727 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1728 uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN) 1729 uint8_t Padding8_V; 1730 1731 // Telemetry Settings 1732 uint16_t GfxMaxCurrent; // in Amps 1733 uint8_t GfxOffset; // in Amps 1734 uint8_t Padding_TelemetryGfx; 1735 uint16_t SocMaxCurrent; // in Amps 1736 uint8_t SocOffset; // in Amps 1737 uint8_t Padding_TelemetrySoc; 1738 1739 uint16_t Mem0MaxCurrent; // in Amps 1740 uint8_t Mem0Offset; // in Amps 1741 uint8_t Padding_TelemetryMem0; 1742 1743 uint16_t Mem1MaxCurrent; // in Amps 1744 uint8_t Mem1Offset; // in Amps 1745 uint8_t Padding_TelemetryMem1; 1746 1747 // GPIO Settings 1748 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 1749 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 1750 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 1751 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 1752 1753 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 1754 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 1755 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 1756 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 1757 1758 // LED Display Settings 1759 uint8_t LedPin0; // GPIO number for LedPin[0] 1760 uint8_t LedPin1; // GPIO number for LedPin[1] 1761 uint8_t LedPin2; // GPIO number for LedPin[2] 1762 uint8_t padding8_4; 1763 1764 // GFXCLK PLL Spread Spectrum 1765 uint8_t PllGfxclkSpreadEnabled; // on or off 1766 uint8_t PllGfxclkSpreadPercent; // Q4.4 1767 uint16_t PllGfxclkSpreadFreq; // kHz 1768 1769 // GFXCLK DFLL Spread Spectrum 1770 uint8_t DfllGfxclkSpreadEnabled; // on or off 1771 uint8_t DfllGfxclkSpreadPercent; // Q4.4 1772 uint16_t DfllGfxclkSpreadFreq; // kHz 1773 1774 // UCLK Spread Spectrum 1775 uint8_t UclkSpreadEnabled; // on or off 1776 uint8_t UclkSpreadPercent; // Q4.4 1777 uint16_t UclkSpreadFreq; // kHz 1778 1779 // SOCCLK Spread Spectrum 1780 uint8_t SoclkSpreadEnabled; // on or off 1781 uint8_t SocclkSpreadPercent; // Q4.4 1782 uint16_t SocclkSpreadFreq; // kHz 1783 1784 // Total board power 1785 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power 1786 uint16_t BoardPadding; 1787 1788 // Mvdd Svi2 Div Ratio Setting 1789 uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16) 1790 1791 uint32_t BoardReserved[9]; 1792 1793 }; 1794 1795 struct atom_smc_dpm_info_v4_6 1796 { 1797 struct atom_common_table_header table_header; 1798 // section: board parameters 1799 uint32_t i2c_padding[3]; // old i2c control are moved to new area 1800 1801 uint16_t maxvoltagestepgfx; // in mv(q2) max voltage step that smu will request. multiple steps are taken if voltage change exceeds this value. 1802 uint16_t maxvoltagestepsoc; // in mv(q2) max voltage step that smu will request. multiple steps are taken if voltage change exceeds this value. 1803 1804 uint8_t vddgfxvrmapping; // use vr_mapping* bitfields 1805 uint8_t vddsocvrmapping; // use vr_mapping* bitfields 1806 uint8_t vddmemvrmapping; // use vr_mapping* bitfields 1807 uint8_t boardvrmapping; // use vr_mapping* bitfields 1808 1809 uint8_t gfxulvphasesheddingmask; // set this to 1 to set psi0/1 to 1 in ulv mode 1810 uint8_t externalsensorpresent; // external rdi connected to tmon (aka temp in) 1811 uint8_t padding8_v[2]; 1812 1813 // telemetry settings 1814 uint16_t gfxmaxcurrent; // in amps 1815 uint8_t gfxoffset; // in amps 1816 uint8_t padding_telemetrygfx; 1817 1818 uint16_t socmaxcurrent; // in amps 1819 uint8_t socoffset; // in amps 1820 uint8_t padding_telemetrysoc; 1821 1822 uint16_t memmaxcurrent; // in amps 1823 uint8_t memoffset; // in amps 1824 uint8_t padding_telemetrymem; 1825 1826 uint16_t boardmaxcurrent; // in amps 1827 uint8_t boardoffset; // in amps 1828 uint8_t padding_telemetryboardinput; 1829 1830 // gpio settings 1831 uint8_t vr0hotgpio; // gpio pin configured for vr0 hot event 1832 uint8_t vr0hotpolarity; // gpio polarity for vr0 hot event 1833 uint8_t vr1hotgpio; // gpio pin configured for vr1 hot event 1834 uint8_t vr1hotpolarity; // gpio polarity for vr1 hot event 1835 1836 // gfxclk pll spread spectrum 1837 uint8_t pllgfxclkspreadenabled; // on or off 1838 uint8_t pllgfxclkspreadpercent; // q4.4 1839 uint16_t pllgfxclkspreadfreq; // khz 1840 1841 // uclk spread spectrum 1842 uint8_t uclkspreadenabled; // on or off 1843 uint8_t uclkspreadpercent; // q4.4 1844 uint16_t uclkspreadfreq; // khz 1845 1846 // fclk spread spectrum 1847 uint8_t fclkspreadenabled; // on or off 1848 uint8_t fclkspreadpercent; // q4.4 1849 uint16_t fclkspreadfreq; // khz 1850 1851 1852 // gfxclk fll spread spectrum 1853 uint8_t fllgfxclkspreadenabled; // on or off 1854 uint8_t fllgfxclkspreadpercent; // q4.4 1855 uint16_t fllgfxclkspreadfreq; // khz 1856 1857 // i2c controller structure 1858 struct smudpm_i2c_controller_config_v2 i2ccontrollers[8]; 1859 1860 // memory section 1861 uint32_t memorychannelenabled; // for dram use only, max 32 channels enabled bit mask. 1862 1863 uint8_t drambitwidth; // for dram use only. see dram bit width type defines 1864 uint8_t paddingmem[3]; 1865 1866 // total board power 1867 uint16_t totalboardpower; //only needed for tcp estimated case, where tcp = tgp+total board power 1868 uint16_t boardpadding; 1869 1870 // section: xgmi training 1871 uint8_t xgmilinkspeed[4]; 1872 uint8_t xgmilinkwidth[4]; 1873 1874 uint16_t xgmifclkfreq[4]; 1875 uint16_t xgmisocvoltage[4]; 1876 1877 // reserved 1878 uint32_t boardreserved[10]; 1879 }; 1880 1881 /* 1882 *************************************************************************** 1883 Data Table asic_profiling_info structure 1884 *************************************************************************** 1885 */ 1886 struct atom_asic_profiling_info_v4_1 1887 { 1888 struct atom_common_table_header table_header; 1889 uint32_t maxvddc; 1890 uint32_t minvddc; 1891 uint32_t avfs_meannsigma_acontant0; 1892 uint32_t avfs_meannsigma_acontant1; 1893 uint32_t avfs_meannsigma_acontant2; 1894 uint16_t avfs_meannsigma_dc_tol_sigma; 1895 uint16_t avfs_meannsigma_platform_mean; 1896 uint16_t avfs_meannsigma_platform_sigma; 1897 uint32_t gb_vdroop_table_cksoff_a0; 1898 uint32_t gb_vdroop_table_cksoff_a1; 1899 uint32_t gb_vdroop_table_cksoff_a2; 1900 uint32_t gb_vdroop_table_ckson_a0; 1901 uint32_t gb_vdroop_table_ckson_a1; 1902 uint32_t gb_vdroop_table_ckson_a2; 1903 uint32_t avfsgb_fuse_table_cksoff_m1; 1904 uint32_t avfsgb_fuse_table_cksoff_m2; 1905 uint32_t avfsgb_fuse_table_cksoff_b; 1906 uint32_t avfsgb_fuse_table_ckson_m1; 1907 uint32_t avfsgb_fuse_table_ckson_m2; 1908 uint32_t avfsgb_fuse_table_ckson_b; 1909 uint16_t max_voltage_0_25mv; 1910 uint8_t enable_gb_vdroop_table_cksoff; 1911 uint8_t enable_gb_vdroop_table_ckson; 1912 uint8_t enable_gb_fuse_table_cksoff; 1913 uint8_t enable_gb_fuse_table_ckson; 1914 uint16_t psm_age_comfactor; 1915 uint8_t enable_apply_avfs_cksoff_voltage; 1916 uint8_t reserved; 1917 uint32_t dispclk2gfxclk_a; 1918 uint32_t dispclk2gfxclk_b; 1919 uint32_t dispclk2gfxclk_c; 1920 uint32_t pixclk2gfxclk_a; 1921 uint32_t pixclk2gfxclk_b; 1922 uint32_t pixclk2gfxclk_c; 1923 uint32_t dcefclk2gfxclk_a; 1924 uint32_t dcefclk2gfxclk_b; 1925 uint32_t dcefclk2gfxclk_c; 1926 uint32_t phyclk2gfxclk_a; 1927 uint32_t phyclk2gfxclk_b; 1928 uint32_t phyclk2gfxclk_c; 1929 }; 1930 1931 struct atom_asic_profiling_info_v4_2 { 1932 struct atom_common_table_header table_header; 1933 uint32_t maxvddc; 1934 uint32_t minvddc; 1935 uint32_t avfs_meannsigma_acontant0; 1936 uint32_t avfs_meannsigma_acontant1; 1937 uint32_t avfs_meannsigma_acontant2; 1938 uint16_t avfs_meannsigma_dc_tol_sigma; 1939 uint16_t avfs_meannsigma_platform_mean; 1940 uint16_t avfs_meannsigma_platform_sigma; 1941 uint32_t gb_vdroop_table_cksoff_a0; 1942 uint32_t gb_vdroop_table_cksoff_a1; 1943 uint32_t gb_vdroop_table_cksoff_a2; 1944 uint32_t gb_vdroop_table_ckson_a0; 1945 uint32_t gb_vdroop_table_ckson_a1; 1946 uint32_t gb_vdroop_table_ckson_a2; 1947 uint32_t avfsgb_fuse_table_cksoff_m1; 1948 uint32_t avfsgb_fuse_table_cksoff_m2; 1949 uint32_t avfsgb_fuse_table_cksoff_b; 1950 uint32_t avfsgb_fuse_table_ckson_m1; 1951 uint32_t avfsgb_fuse_table_ckson_m2; 1952 uint32_t avfsgb_fuse_table_ckson_b; 1953 uint16_t max_voltage_0_25mv; 1954 uint8_t enable_gb_vdroop_table_cksoff; 1955 uint8_t enable_gb_vdroop_table_ckson; 1956 uint8_t enable_gb_fuse_table_cksoff; 1957 uint8_t enable_gb_fuse_table_ckson; 1958 uint16_t psm_age_comfactor; 1959 uint8_t enable_apply_avfs_cksoff_voltage; 1960 uint8_t reserved; 1961 uint32_t dispclk2gfxclk_a; 1962 uint32_t dispclk2gfxclk_b; 1963 uint32_t dispclk2gfxclk_c; 1964 uint32_t pixclk2gfxclk_a; 1965 uint32_t pixclk2gfxclk_b; 1966 uint32_t pixclk2gfxclk_c; 1967 uint32_t dcefclk2gfxclk_a; 1968 uint32_t dcefclk2gfxclk_b; 1969 uint32_t dcefclk2gfxclk_c; 1970 uint32_t phyclk2gfxclk_a; 1971 uint32_t phyclk2gfxclk_b; 1972 uint32_t phyclk2gfxclk_c; 1973 uint32_t acg_gb_vdroop_table_a0; 1974 uint32_t acg_gb_vdroop_table_a1; 1975 uint32_t acg_gb_vdroop_table_a2; 1976 uint32_t acg_avfsgb_fuse_table_m1; 1977 uint32_t acg_avfsgb_fuse_table_m2; 1978 uint32_t acg_avfsgb_fuse_table_b; 1979 uint8_t enable_acg_gb_vdroop_table; 1980 uint8_t enable_acg_gb_fuse_table; 1981 uint32_t acg_dispclk2gfxclk_a; 1982 uint32_t acg_dispclk2gfxclk_b; 1983 uint32_t acg_dispclk2gfxclk_c; 1984 uint32_t acg_pixclk2gfxclk_a; 1985 uint32_t acg_pixclk2gfxclk_b; 1986 uint32_t acg_pixclk2gfxclk_c; 1987 uint32_t acg_dcefclk2gfxclk_a; 1988 uint32_t acg_dcefclk2gfxclk_b; 1989 uint32_t acg_dcefclk2gfxclk_c; 1990 uint32_t acg_phyclk2gfxclk_a; 1991 uint32_t acg_phyclk2gfxclk_b; 1992 uint32_t acg_phyclk2gfxclk_c; 1993 }; 1994 1995 /* 1996 *************************************************************************** 1997 Data Table multimedia_info structure 1998 *************************************************************************** 1999 */ 2000 struct atom_multimedia_info_v2_1 2001 { 2002 struct atom_common_table_header table_header; 2003 uint8_t uvdip_min_ver; 2004 uint8_t uvdip_max_ver; 2005 uint8_t vceip_min_ver; 2006 uint8_t vceip_max_ver; 2007 uint16_t uvd_enc_max_input_width_pixels; 2008 uint16_t uvd_enc_max_input_height_pixels; 2009 uint16_t vce_enc_max_input_width_pixels; 2010 uint16_t vce_enc_max_input_height_pixels; 2011 uint32_t uvd_enc_max_bandwidth; // 16x16 pixels/sec, codec independent 2012 uint32_t vce_enc_max_bandwidth; // 16x16 pixels/sec, codec independent 2013 }; 2014 2015 2016 /* 2017 *************************************************************************** 2018 Data Table umc_info structure 2019 *************************************************************************** 2020 */ 2021 struct atom_umc_info_v3_1 2022 { 2023 struct atom_common_table_header table_header; 2024 uint32_t ucode_version; 2025 uint32_t ucode_rom_startaddr; 2026 uint32_t ucode_length; 2027 uint16_t umc_reg_init_offset; 2028 uint16_t customer_ucode_name_offset; 2029 uint16_t mclk_ss_percentage; 2030 uint16_t mclk_ss_rate_10hz; 2031 uint8_t umcip_min_ver; 2032 uint8_t umcip_max_ver; 2033 uint8_t vram_type; //enum of atom_dgpu_vram_type 2034 uint8_t umc_config; 2035 uint32_t mem_refclk_10khz; 2036 }; 2037 2038 // umc_info.umc_config 2039 enum atom_umc_config_def { 2040 UMC_CONFIG__ENABLE_1KB_INTERLEAVE_MODE = 0x00000001, 2041 UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE = 0x00000002, 2042 UMC_CONFIG__ENABLE_HBM_LANE_REPAIR = 0x00000004, 2043 UMC_CONFIG__ENABLE_BANK_HARVESTING = 0x00000008, 2044 UMC_CONFIG__ENABLE_PHY_REINIT = 0x00000010, 2045 UMC_CONFIG__DISABLE_UCODE_CHKSTATUS = 0x00000020, 2046 }; 2047 2048 struct atom_umc_info_v3_2 2049 { 2050 struct atom_common_table_header table_header; 2051 uint32_t ucode_version; 2052 uint32_t ucode_rom_startaddr; 2053 uint32_t ucode_length; 2054 uint16_t umc_reg_init_offset; 2055 uint16_t customer_ucode_name_offset; 2056 uint16_t mclk_ss_percentage; 2057 uint16_t mclk_ss_rate_10hz; 2058 uint8_t umcip_min_ver; 2059 uint8_t umcip_max_ver; 2060 uint8_t vram_type; //enum of atom_dgpu_vram_type 2061 uint8_t umc_config; 2062 uint32_t mem_refclk_10khz; 2063 uint32_t pstate_uclk_10khz[4]; 2064 uint16_t umcgoldenoffset; 2065 uint16_t densitygoldenoffset; 2066 }; 2067 2068 struct atom_umc_info_v3_3 2069 { 2070 struct atom_common_table_header table_header; 2071 uint32_t ucode_reserved; 2072 uint32_t ucode_rom_startaddr; 2073 uint32_t ucode_length; 2074 uint16_t umc_reg_init_offset; 2075 uint16_t customer_ucode_name_offset; 2076 uint16_t mclk_ss_percentage; 2077 uint16_t mclk_ss_rate_10hz; 2078 uint8_t umcip_min_ver; 2079 uint8_t umcip_max_ver; 2080 uint8_t vram_type; //enum of atom_dgpu_vram_type 2081 uint8_t umc_config; 2082 uint32_t mem_refclk_10khz; 2083 uint32_t pstate_uclk_10khz[4]; 2084 uint16_t umcgoldenoffset; 2085 uint16_t densitygoldenoffset; 2086 uint32_t reserved[4]; 2087 }; 2088 2089 /* 2090 *************************************************************************** 2091 Data Table vram_info structure 2092 *************************************************************************** 2093 */ 2094 struct atom_vram_module_v9 { 2095 // Design Specific Values 2096 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros 2097 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not 2098 uint32_t max_mem_clk; // max memory clock of this memory in unit of 10kHz, =0 means it is not defined 2099 uint16_t reserved[3]; 2100 uint16_t mem_voltage; // mem_voltage 2101 uint16_t vram_module_size; // Size of atom_vram_module_v9 2102 uint8_t ext_memory_id; // Current memory module ID 2103 uint8_t memory_type; // enum of atom_dgpu_vram_type 2104 uint8_t channel_num; // Number of mem. channels supported in this module 2105 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 2106 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 2107 uint8_t tunningset_id; // MC phy registers set per. 2108 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code 2109 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 2110 uint8_t hbm_ven_rev_id; // hbm_ven_rev_id 2111 uint8_t vram_rsd2; // reserved 2112 char dram_pnstring[20]; // part number end with '0'. 2113 }; 2114 2115 struct atom_vram_info_header_v2_3 { 2116 struct atom_common_table_header table_header; 2117 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting 2118 uint16_t mem_clk_patch_tbloffset; // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting 2119 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings 2120 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set 2121 uint16_t dram_data_remap_tbloffset; // reserved for now 2122 uint16_t tmrs_seq_offset; // offset of HBM tmrs 2123 uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init 2124 uint16_t vram_rsd2; 2125 uint8_t vram_module_num; // indicate number of VRAM module 2126 uint8_t umcip_min_ver; 2127 uint8_t umcip_max_ver; 2128 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset 2129 struct atom_vram_module_v9 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 2130 }; 2131 2132 struct atom_umc_register_addr_info{ 2133 uint32_t umc_register_addr:24; 2134 uint32_t umc_reg_type_ind:1; 2135 uint32_t umc_reg_rsvd:7; 2136 }; 2137 2138 //atom_umc_register_addr_info. 2139 enum atom_umc_register_addr_info_flag{ 2140 b3ATOM_UMC_REG_ADD_INFO_INDIRECT_ACCESS =0x01, 2141 }; 2142 2143 union atom_umc_register_addr_info_access 2144 { 2145 struct atom_umc_register_addr_info umc_reg_addr; 2146 uint32_t u32umc_reg_addr; 2147 }; 2148 2149 struct atom_umc_reg_setting_id_config{ 2150 uint32_t memclockrange:24; 2151 uint32_t mem_blk_id:8; 2152 }; 2153 2154 union atom_umc_reg_setting_id_config_access 2155 { 2156 struct atom_umc_reg_setting_id_config umc_id_access; 2157 uint32_t u32umc_id_access; 2158 }; 2159 2160 struct atom_umc_reg_setting_data_block{ 2161 union atom_umc_reg_setting_id_config_access block_id; 2162 uint32_t u32umc_reg_data[1]; 2163 }; 2164 2165 struct atom_umc_init_reg_block{ 2166 uint16_t umc_reg_num; 2167 uint16_t reserved; 2168 union atom_umc_register_addr_info_access umc_reg_list[1]; //for allocation purpose, the real number come from umc_reg_num; 2169 struct atom_umc_reg_setting_data_block umc_reg_setting_list[1]; 2170 }; 2171 2172 struct atom_vram_module_v10 { 2173 // Design Specific Values 2174 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros 2175 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not 2176 uint32_t max_mem_clk; // max memory clock of this memory in unit of 10kHz, =0 means it is not defined 2177 uint16_t reserved[3]; 2178 uint16_t mem_voltage; // mem_voltage 2179 uint16_t vram_module_size; // Size of atom_vram_module_v9 2180 uint8_t ext_memory_id; // Current memory module ID 2181 uint8_t memory_type; // enum of atom_dgpu_vram_type 2182 uint8_t channel_num; // Number of mem. channels supported in this module 2183 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 2184 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 2185 uint8_t tunningset_id; // MC phy registers set per 2186 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code 2187 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 2188 uint8_t vram_flags; // bit0= bankgroup enable 2189 uint8_t vram_rsd2; // reserved 2190 uint16_t gddr6_mr10; // gddr6 mode register10 value 2191 uint16_t gddr6_mr1; // gddr6 mode register1 value 2192 uint16_t gddr6_mr2; // gddr6 mode register2 value 2193 uint16_t gddr6_mr7; // gddr6 mode register7 value 2194 char dram_pnstring[20]; // part number end with '0' 2195 }; 2196 2197 struct atom_vram_info_header_v2_4 { 2198 struct atom_common_table_header table_header; 2199 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting 2200 uint16_t mem_clk_patch_tbloffset; // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting 2201 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings 2202 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set 2203 uint16_t dram_data_remap_tbloffset; // reserved for now 2204 uint16_t reserved; // offset of reserved 2205 uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init 2206 uint16_t vram_rsd2; 2207 uint8_t vram_module_num; // indicate number of VRAM module 2208 uint8_t umcip_min_ver; 2209 uint8_t umcip_max_ver; 2210 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset 2211 struct atom_vram_module_v10 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 2212 }; 2213 2214 /* 2215 *************************************************************************** 2216 Data Table voltageobject_info structure 2217 *************************************************************************** 2218 */ 2219 struct atom_i2c_data_entry 2220 { 2221 uint16_t i2c_reg_index; // i2c register address, can be up to 16bit 2222 uint16_t i2c_reg_data; // i2c register data, can be up to 16bit 2223 }; 2224 2225 struct atom_voltage_object_header_v4{ 2226 uint8_t voltage_type; //enum atom_voltage_type 2227 uint8_t voltage_mode; //enum atom_voltage_object_mode 2228 uint16_t object_size; //Size of Object 2229 }; 2230 2231 // atom_voltage_object_header_v4.voltage_mode 2232 enum atom_voltage_object_mode 2233 { 2234 VOLTAGE_OBJ_GPIO_LUT = 0, //VOLTAGE and GPIO Lookup table ->atom_gpio_voltage_object_v4 2235 VOLTAGE_OBJ_VR_I2C_INIT_SEQ = 3, //VOLTAGE REGULATOR INIT sequece through I2C -> atom_i2c_voltage_object_v4 2236 VOLTAGE_OBJ_PHASE_LUT = 4, //Set Vregulator Phase lookup table ->atom_gpio_voltage_object_v4 2237 VOLTAGE_OBJ_SVID2 = 7, //Indicate voltage control by SVID2 ->atom_svid2_voltage_object_v4 2238 VOLTAGE_OBJ_EVV = 8, 2239 VOLTAGE_OBJ_MERGED_POWER = 9, 2240 }; 2241 2242 struct atom_i2c_voltage_object_v4 2243 { 2244 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_VR_I2C_INIT_SEQ 2245 uint8_t regulator_id; //Indicate Voltage Regulator Id 2246 uint8_t i2c_id; 2247 uint8_t i2c_slave_addr; 2248 uint8_t i2c_control_offset; 2249 uint8_t i2c_flag; // Bit0: 0 - One byte data; 1 - Two byte data 2250 uint8_t i2c_speed; // =0, use default i2c speed, otherwise use it in unit of kHz. 2251 uint8_t reserved[2]; 2252 struct atom_i2c_data_entry i2cdatalut[1]; // end with 0xff 2253 }; 2254 2255 // ATOM_I2C_VOLTAGE_OBJECT_V3.ucVoltageControlFlag 2256 enum atom_i2c_voltage_control_flag 2257 { 2258 VOLTAGE_DATA_ONE_BYTE = 0, 2259 VOLTAGE_DATA_TWO_BYTE = 1, 2260 }; 2261 2262 2263 struct atom_voltage_gpio_map_lut 2264 { 2265 uint32_t voltage_gpio_reg_val; // The Voltage ID which is used to program GPIO register 2266 uint16_t voltage_level_mv; // The corresponding Voltage Value, in mV 2267 }; 2268 2269 struct atom_gpio_voltage_object_v4 2270 { 2271 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT 2272 uint8_t gpio_control_id; // default is 0 which indicate control through CG VID mode 2273 uint8_t gpio_entry_num; // indiate the entry numbers of Votlage/Gpio value Look up table 2274 uint8_t phase_delay_us; // phase delay in unit of micro second 2275 uint8_t reserved; 2276 uint32_t gpio_mask_val; // GPIO Mask value 2277 struct atom_voltage_gpio_map_lut voltage_gpio_lut[1]; 2278 }; 2279 2280 struct atom_svid2_voltage_object_v4 2281 { 2282 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_SVID2 2283 uint8_t loadline_psi1; // bit4:0= loadline setting ( Core Loadline trim and offset trim ), bit5=0:PSI1_L disable =1: PSI1_L enable 2284 uint8_t psi0_l_vid_thresd; // VR PSI0_L VID threshold 2285 uint8_t psi0_enable; // 2286 uint8_t maxvstep; 2287 uint8_t telemetry_offset; 2288 uint8_t telemetry_gain; 2289 uint16_t reserved1; 2290 }; 2291 2292 struct atom_merged_voltage_object_v4 2293 { 2294 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_MERGED_POWER 2295 uint8_t merged_powerrail_type; //enum atom_voltage_type 2296 uint8_t reserved[3]; 2297 }; 2298 2299 union atom_voltage_object_v4{ 2300 struct atom_gpio_voltage_object_v4 gpio_voltage_obj; 2301 struct atom_i2c_voltage_object_v4 i2c_voltage_obj; 2302 struct atom_svid2_voltage_object_v4 svid2_voltage_obj; 2303 struct atom_merged_voltage_object_v4 merged_voltage_obj; 2304 }; 2305 2306 struct atom_voltage_objects_info_v4_1 2307 { 2308 struct atom_common_table_header table_header; 2309 union atom_voltage_object_v4 voltage_object[1]; //Info for Voltage control 2310 }; 2311 2312 2313 /* 2314 *************************************************************************** 2315 All Command Function structure definition 2316 *************************************************************************** 2317 */ 2318 2319 /* 2320 *************************************************************************** 2321 Structures used by asic_init 2322 *************************************************************************** 2323 */ 2324 2325 struct asic_init_engine_parameters 2326 { 2327 uint32_t sclkfreqin10khz:24; 2328 uint32_t engineflag:8; /* enum atom_asic_init_engine_flag */ 2329 }; 2330 2331 struct asic_init_mem_parameters 2332 { 2333 uint32_t mclkfreqin10khz:24; 2334 uint32_t memflag:8; /* enum atom_asic_init_mem_flag */ 2335 }; 2336 2337 struct asic_init_parameters_v2_1 2338 { 2339 struct asic_init_engine_parameters engineparam; 2340 struct asic_init_mem_parameters memparam; 2341 }; 2342 2343 struct asic_init_ps_allocation_v2_1 2344 { 2345 struct asic_init_parameters_v2_1 param; 2346 uint32_t reserved[16]; 2347 }; 2348 2349 2350 enum atom_asic_init_engine_flag 2351 { 2352 b3NORMAL_ENGINE_INIT = 0, 2353 b3SRIOV_SKIP_ASIC_INIT = 0x02, 2354 b3SRIOV_LOAD_UCODE = 0x40, 2355 }; 2356 2357 enum atom_asic_init_mem_flag 2358 { 2359 b3NORMAL_MEM_INIT = 0, 2360 b3DRAM_SELF_REFRESH_EXIT =0x20, 2361 }; 2362 2363 /* 2364 *************************************************************************** 2365 Structures used by setengineclock 2366 *************************************************************************** 2367 */ 2368 2369 struct set_engine_clock_parameters_v2_1 2370 { 2371 uint32_t sclkfreqin10khz:24; 2372 uint32_t sclkflag:8; /* enum atom_set_engine_mem_clock_flag, */ 2373 uint32_t reserved[10]; 2374 }; 2375 2376 struct set_engine_clock_ps_allocation_v2_1 2377 { 2378 struct set_engine_clock_parameters_v2_1 clockinfo; 2379 uint32_t reserved[10]; 2380 }; 2381 2382 2383 enum atom_set_engine_mem_clock_flag 2384 { 2385 b3NORMAL_CHANGE_CLOCK = 0, 2386 b3FIRST_TIME_CHANGE_CLOCK = 0x08, 2387 b3STORE_DPM_TRAINGING = 0x40, //Applicable to memory clock change,when set, it store specific DPM mode training result 2388 }; 2389 2390 /* 2391 *************************************************************************** 2392 Structures used by getengineclock 2393 *************************************************************************** 2394 */ 2395 struct get_engine_clock_parameter 2396 { 2397 uint32_t sclk_10khz; // current engine speed in 10KHz unit 2398 uint32_t reserved; 2399 }; 2400 2401 /* 2402 *************************************************************************** 2403 Structures used by setmemoryclock 2404 *************************************************************************** 2405 */ 2406 struct set_memory_clock_parameters_v2_1 2407 { 2408 uint32_t mclkfreqin10khz:24; 2409 uint32_t mclkflag:8; /* enum atom_set_engine_mem_clock_flag, */ 2410 uint32_t reserved[10]; 2411 }; 2412 2413 struct set_memory_clock_ps_allocation_v2_1 2414 { 2415 struct set_memory_clock_parameters_v2_1 clockinfo; 2416 uint32_t reserved[10]; 2417 }; 2418 2419 2420 /* 2421 *************************************************************************** 2422 Structures used by getmemoryclock 2423 *************************************************************************** 2424 */ 2425 struct get_memory_clock_parameter 2426 { 2427 uint32_t mclk_10khz; // current engine speed in 10KHz unit 2428 uint32_t reserved; 2429 }; 2430 2431 2432 2433 /* 2434 *************************************************************************** 2435 Structures used by setvoltage 2436 *************************************************************************** 2437 */ 2438 2439 struct set_voltage_parameters_v1_4 2440 { 2441 uint8_t voltagetype; /* enum atom_voltage_type */ 2442 uint8_t command; /* Indicate action: Set voltage level, enum atom_set_voltage_command */ 2443 uint16_t vlevel_mv; /* real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) */ 2444 }; 2445 2446 //set_voltage_parameters_v2_1.voltagemode 2447 enum atom_set_voltage_command{ 2448 ATOM_SET_VOLTAGE = 0, 2449 ATOM_INIT_VOLTAGE_REGULATOR = 3, 2450 ATOM_SET_VOLTAGE_PHASE = 4, 2451 ATOM_GET_LEAKAGE_ID = 8, 2452 }; 2453 2454 struct set_voltage_ps_allocation_v1_4 2455 { 2456 struct set_voltage_parameters_v1_4 setvoltageparam; 2457 uint32_t reserved[10]; 2458 }; 2459 2460 2461 /* 2462 *************************************************************************** 2463 Structures used by computegpuclockparam 2464 *************************************************************************** 2465 */ 2466 2467 //ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag 2468 enum atom_gpu_clock_type 2469 { 2470 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK =0x00, 2471 COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK =0x01, 2472 COMPUTE_GPUCLK_INPUT_FLAG_UCLK =0x02, 2473 }; 2474 2475 struct compute_gpu_clock_input_parameter_v1_8 2476 { 2477 uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock 2478 uint32_t gpu_clock_type:8; //Input indicate clock type: enum atom_gpu_clock_type 2479 uint32_t reserved[5]; 2480 }; 2481 2482 2483 struct compute_gpu_clock_output_parameter_v1_8 2484 { 2485 uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock 2486 uint32_t dfs_did:8; //return parameter: DFS divider which is used to program to register directly 2487 uint32_t pll_fb_mult; //Feedback Multiplier, bit 8:0 int, bit 15:12 post_div, bit 31:16 frac 2488 uint32_t pll_ss_fbsmult; // Spread FB Mult: bit 8:0 int, bit 31:16 frac 2489 uint16_t pll_ss_slew_frac; 2490 uint8_t pll_ss_enable; 2491 uint8_t reserved; 2492 uint32_t reserved1[2]; 2493 }; 2494 2495 2496 2497 /* 2498 *************************************************************************** 2499 Structures used by ReadEfuseValue 2500 *************************************************************************** 2501 */ 2502 2503 struct read_efuse_input_parameters_v3_1 2504 { 2505 uint16_t efuse_start_index; 2506 uint8_t reserved; 2507 uint8_t bitslen; 2508 }; 2509 2510 // ReadEfuseValue input/output parameter 2511 union read_efuse_value_parameters_v3_1 2512 { 2513 struct read_efuse_input_parameters_v3_1 efuse_info; 2514 uint32_t efusevalue; 2515 }; 2516 2517 2518 /* 2519 *************************************************************************** 2520 Structures used by getsmuclockinfo 2521 *************************************************************************** 2522 */ 2523 struct atom_get_smu_clock_info_parameters_v3_1 2524 { 2525 uint8_t syspll_id; // 0= syspll0, 1=syspll1, 2=syspll2 2526 uint8_t clk_id; // atom_smu9_syspll0_clock_id (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ ) 2527 uint8_t command; // enum of atom_get_smu_clock_info_command 2528 uint8_t dfsdid; // =0: get DFS DID from register, >0, give DFS divider, (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ ) 2529 }; 2530 2531 enum atom_get_smu_clock_info_command 2532 { 2533 GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ = 0, 2534 GET_SMU_CLOCK_INFO_V3_1_GET_PLLVCO_FREQ = 1, 2535 GET_SMU_CLOCK_INFO_V3_1_GET_PLLREFCLK_FREQ = 2, 2536 }; 2537 2538 enum atom_smu9_syspll0_clock_id 2539 { 2540 SMU9_SYSPLL0_SMNCLK_ID = 0, // SMNCLK 2541 SMU9_SYSPLL0_SOCCLK_ID = 1, // SOCCLK (FCLK) 2542 SMU9_SYSPLL0_MP0CLK_ID = 2, // MP0CLK 2543 SMU9_SYSPLL0_MP1CLK_ID = 3, // MP1CLK 2544 SMU9_SYSPLL0_LCLK_ID = 4, // LCLK 2545 SMU9_SYSPLL0_DCLK_ID = 5, // DCLK 2546 SMU9_SYSPLL0_VCLK_ID = 6, // VCLK 2547 SMU9_SYSPLL0_ECLK_ID = 7, // ECLK 2548 SMU9_SYSPLL0_DCEFCLK_ID = 8, // DCEFCLK 2549 SMU9_SYSPLL0_DPREFCLK_ID = 10, // DPREFCLK 2550 SMU9_SYSPLL0_DISPCLK_ID = 11, // DISPCLK 2551 }; 2552 2553 enum atom_smu11_syspll_id { 2554 SMU11_SYSPLL0_ID = 0, 2555 SMU11_SYSPLL1_0_ID = 1, 2556 SMU11_SYSPLL1_1_ID = 2, 2557 SMU11_SYSPLL1_2_ID = 3, 2558 SMU11_SYSPLL2_ID = 4, 2559 SMU11_SYSPLL3_0_ID = 5, 2560 SMU11_SYSPLL3_1_ID = 6, 2561 }; 2562 2563 enum atom_smu11_syspll0_clock_id { 2564 SMU11_SYSPLL0_ECLK_ID = 0, // ECLK 2565 SMU11_SYSPLL0_SOCCLK_ID = 1, // SOCCLK 2566 SMU11_SYSPLL0_MP0CLK_ID = 2, // MP0CLK 2567 SMU11_SYSPLL0_DCLK_ID = 3, // DCLK 2568 SMU11_SYSPLL0_VCLK_ID = 4, // VCLK 2569 SMU11_SYSPLL0_DCEFCLK_ID = 5, // DCEFCLK 2570 }; 2571 2572 enum atom_smu11_syspll1_0_clock_id { 2573 SMU11_SYSPLL1_0_UCLKA_ID = 0, // UCLK_a 2574 }; 2575 2576 enum atom_smu11_syspll1_1_clock_id { 2577 SMU11_SYSPLL1_0_UCLKB_ID = 0, // UCLK_b 2578 }; 2579 2580 enum atom_smu11_syspll1_2_clock_id { 2581 SMU11_SYSPLL1_0_FCLK_ID = 0, // FCLK 2582 }; 2583 2584 enum atom_smu11_syspll2_clock_id { 2585 SMU11_SYSPLL2_GFXCLK_ID = 0, // GFXCLK 2586 }; 2587 2588 enum atom_smu11_syspll3_0_clock_id { 2589 SMU11_SYSPLL3_0_WAFCLK_ID = 0, // WAFCLK 2590 SMU11_SYSPLL3_0_DISPCLK_ID = 1, // DISPCLK 2591 SMU11_SYSPLL3_0_DPREFCLK_ID = 2, // DPREFCLK 2592 }; 2593 2594 enum atom_smu11_syspll3_1_clock_id { 2595 SMU11_SYSPLL3_1_MP1CLK_ID = 0, // MP1CLK 2596 SMU11_SYSPLL3_1_SMNCLK_ID = 1, // SMNCLK 2597 SMU11_SYSPLL3_1_LCLK_ID = 2, // LCLK 2598 }; 2599 2600 struct atom_get_smu_clock_info_output_parameters_v3_1 2601 { 2602 union { 2603 uint32_t smu_clock_freq_hz; 2604 uint32_t syspllvcofreq_10khz; 2605 uint32_t sysspllrefclk_10khz; 2606 }atom_smu_outputclkfreq; 2607 }; 2608 2609 2610 2611 /* 2612 *************************************************************************** 2613 Structures used by dynamicmemorysettings 2614 *************************************************************************** 2615 */ 2616 2617 enum atom_dynamic_memory_setting_command 2618 { 2619 COMPUTE_MEMORY_PLL_PARAM = 1, 2620 COMPUTE_ENGINE_PLL_PARAM = 2, 2621 ADJUST_MC_SETTING_PARAM = 3, 2622 }; 2623 2624 /* when command = COMPUTE_MEMORY_PLL_PARAM or ADJUST_MC_SETTING_PARAM */ 2625 struct dynamic_mclk_settings_parameters_v2_1 2626 { 2627 uint32_t mclk_10khz:24; //Input= target mclk 2628 uint32_t command:8; //command enum of atom_dynamic_memory_setting_command 2629 uint32_t reserved; 2630 }; 2631 2632 /* when command = COMPUTE_ENGINE_PLL_PARAM */ 2633 struct dynamic_sclk_settings_parameters_v2_1 2634 { 2635 uint32_t sclk_10khz:24; //Input= target mclk 2636 uint32_t command:8; //command enum of atom_dynamic_memory_setting_command 2637 uint32_t mclk_10khz; 2638 uint32_t reserved; 2639 }; 2640 2641 union dynamic_memory_settings_parameters_v2_1 2642 { 2643 struct dynamic_mclk_settings_parameters_v2_1 mclk_setting; 2644 struct dynamic_sclk_settings_parameters_v2_1 sclk_setting; 2645 }; 2646 2647 2648 2649 /* 2650 *************************************************************************** 2651 Structures used by memorytraining 2652 *************************************************************************** 2653 */ 2654 2655 enum atom_umc6_0_ucode_function_call_enum_id 2656 { 2657 UMC60_UCODE_FUNC_ID_REINIT = 0, 2658 UMC60_UCODE_FUNC_ID_ENTER_SELFREFRESH = 1, 2659 UMC60_UCODE_FUNC_ID_EXIT_SELFREFRESH = 2, 2660 }; 2661 2662 2663 struct memory_training_parameters_v2_1 2664 { 2665 uint8_t ucode_func_id; 2666 uint8_t ucode_reserved[3]; 2667 uint32_t reserved[5]; 2668 }; 2669 2670 2671 /* 2672 *************************************************************************** 2673 Structures used by setpixelclock 2674 *************************************************************************** 2675 */ 2676 2677 struct set_pixel_clock_parameter_v1_7 2678 { 2679 uint32_t pixclk_100hz; // target the pixel clock to drive the CRTC timing in unit of 100Hz. 2680 2681 uint8_t pll_id; // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0 2682 uint8_t encoderobjid; // ASIC encoder id defined in objectId.h, 2683 // indicate which graphic encoder will be used. 2684 uint8_t encoder_mode; // Encoder mode: 2685 uint8_t miscinfo; // enum atom_set_pixel_clock_v1_7_misc_info 2686 uint8_t crtc_id; // enum of atom_crtc_def 2687 uint8_t deep_color_ratio; // HDMI panel bit depth: enum atom_set_pixel_clock_v1_7_deepcolor_ratio 2688 uint8_t reserved1[2]; 2689 uint32_t reserved2; 2690 }; 2691 2692 //ucMiscInfo 2693 enum atom_set_pixel_clock_v1_7_misc_info 2694 { 2695 PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL = 0x01, 2696 PIXEL_CLOCK_V7_MISC_PROG_PHYPLL = 0x02, 2697 PIXEL_CLOCK_V7_MISC_YUV420_MODE = 0x04, 2698 PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN = 0x08, 2699 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC = 0x30, 2700 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN = 0x00, 2701 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_PCIE = 0x10, 2702 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK = 0x20, 2703 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_REFPAD = 0x30, 2704 PIXEL_CLOCK_V7_MISC_ATOMIC_UPDATE = 0x40, 2705 PIXEL_CLOCK_V7_MISC_FORCE_SS_DIS = 0x80, 2706 }; 2707 2708 /* deep_color_ratio */ 2709 enum atom_set_pixel_clock_v1_7_deepcolor_ratio 2710 { 2711 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO 2712 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4 2713 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2 2714 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1 2715 }; 2716 2717 /* 2718 *************************************************************************** 2719 Structures used by setdceclock 2720 *************************************************************************** 2721 */ 2722 2723 // SetDCEClock input parameter for DCE11.2( ELM and BF ) and above 2724 struct set_dce_clock_parameters_v2_1 2725 { 2726 uint32_t dceclk_10khz; // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency. 2727 uint8_t dceclktype; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK 2728 uint8_t dceclksrc; // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK or ATOM_COMBOPHY_PLLx 2729 uint8_t dceclkflag; // Bit [1:0] = PPLL ref clock source ( when ucDCEClkSrc= ATOM_PPLL0 ) 2730 uint8_t crtc_id; // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use only when ucDCEClkType = PIXCLK 2731 }; 2732 2733 //ucDCEClkType 2734 enum atom_set_dce_clock_clock_type 2735 { 2736 DCE_CLOCK_TYPE_DISPCLK = 0, 2737 DCE_CLOCK_TYPE_DPREFCLK = 1, 2738 DCE_CLOCK_TYPE_PIXELCLK = 2, // used by VBIOS internally, called by SetPixelClock 2739 }; 2740 2741 //ucDCEClkFlag when ucDCEClkType == DPREFCLK 2742 enum atom_set_dce_clock_dprefclk_flag 2743 { 2744 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_MASK = 0x03, 2745 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA = 0x00, 2746 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK = 0x01, 2747 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE = 0x02, 2748 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN = 0x03, 2749 }; 2750 2751 //ucDCEClkFlag when ucDCEClkType == PIXCLK 2752 enum atom_set_dce_clock_pixclk_flag 2753 { 2754 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_MASK = 0x03, 2755 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO 2756 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4 2757 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2 2758 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1 2759 DCE_CLOCK_FLAG_PIXCLK_YUV420_MODE = 0x04, 2760 }; 2761 2762 struct set_dce_clock_ps_allocation_v2_1 2763 { 2764 struct set_dce_clock_parameters_v2_1 param; 2765 uint32_t ulReserved[2]; 2766 }; 2767 2768 2769 /****************************************************************************/ 2770 // Structures used by BlankCRTC 2771 /****************************************************************************/ 2772 struct blank_crtc_parameters 2773 { 2774 uint8_t crtc_id; // enum atom_crtc_def 2775 uint8_t blanking; // enum atom_blank_crtc_command 2776 uint16_t reserved; 2777 uint32_t reserved1; 2778 }; 2779 2780 enum atom_blank_crtc_command 2781 { 2782 ATOM_BLANKING = 1, 2783 ATOM_BLANKING_OFF = 0, 2784 }; 2785 2786 /****************************************************************************/ 2787 // Structures used by enablecrtc 2788 /****************************************************************************/ 2789 struct enable_crtc_parameters 2790 { 2791 uint8_t crtc_id; // enum atom_crtc_def 2792 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE 2793 uint8_t padding[2]; 2794 }; 2795 2796 2797 /****************************************************************************/ 2798 // Structure used by EnableDispPowerGating 2799 /****************************************************************************/ 2800 struct enable_disp_power_gating_parameters_v2_1 2801 { 2802 uint8_t disp_pipe_id; // ATOM_CRTC1, ATOM_CRTC2, ... 2803 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE 2804 uint8_t padding[2]; 2805 }; 2806 2807 struct enable_disp_power_gating_ps_allocation 2808 { 2809 struct enable_disp_power_gating_parameters_v2_1 param; 2810 uint32_t ulReserved[4]; 2811 }; 2812 2813 /****************************************************************************/ 2814 // Structure used in setcrtc_usingdtdtiming 2815 /****************************************************************************/ 2816 struct set_crtc_using_dtd_timing_parameters 2817 { 2818 uint16_t h_size; 2819 uint16_t h_blanking_time; 2820 uint16_t v_size; 2821 uint16_t v_blanking_time; 2822 uint16_t h_syncoffset; 2823 uint16_t h_syncwidth; 2824 uint16_t v_syncoffset; 2825 uint16_t v_syncwidth; 2826 uint16_t modemiscinfo; 2827 uint8_t h_border; 2828 uint8_t v_border; 2829 uint8_t crtc_id; // enum atom_crtc_def 2830 uint8_t encoder_mode; // atom_encode_mode_def 2831 uint8_t padding[2]; 2832 }; 2833 2834 2835 /****************************************************************************/ 2836 // Structures used by processi2cchanneltransaction 2837 /****************************************************************************/ 2838 struct process_i2c_channel_transaction_parameters 2839 { 2840 uint8_t i2cspeed_khz; 2841 union { 2842 uint8_t regindex; 2843 uint8_t status; /* enum atom_process_i2c_flag */ 2844 } regind_status; 2845 uint16_t i2c_data_out; 2846 uint8_t flag; /* enum atom_process_i2c_status */ 2847 uint8_t trans_bytes; 2848 uint8_t slave_addr; 2849 uint8_t i2c_id; 2850 }; 2851 2852 //ucFlag 2853 enum atom_process_i2c_flag 2854 { 2855 HW_I2C_WRITE = 1, 2856 HW_I2C_READ = 0, 2857 I2C_2BYTE_ADDR = 0x02, 2858 HW_I2C_SMBUS_BYTE_WR = 0x04, 2859 }; 2860 2861 //status 2862 enum atom_process_i2c_status 2863 { 2864 HW_ASSISTED_I2C_STATUS_FAILURE =2, 2865 HW_ASSISTED_I2C_STATUS_SUCCESS =1, 2866 }; 2867 2868 2869 /****************************************************************************/ 2870 // Structures used by processauxchanneltransaction 2871 /****************************************************************************/ 2872 2873 struct process_aux_channel_transaction_parameters_v1_2 2874 { 2875 uint16_t aux_request; 2876 uint16_t dataout; 2877 uint8_t channelid; 2878 union { 2879 uint8_t reply_status; 2880 uint8_t aux_delay; 2881 } aux_status_delay; 2882 uint8_t dataout_len; 2883 uint8_t hpd_id; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6 2884 }; 2885 2886 2887 /****************************************************************************/ 2888 // Structures used by selectcrtc_source 2889 /****************************************************************************/ 2890 2891 struct select_crtc_source_parameters_v2_3 2892 { 2893 uint8_t crtc_id; // enum atom_crtc_def 2894 uint8_t encoder_id; // enum atom_dig_def 2895 uint8_t encode_mode; // enum atom_encode_mode_def 2896 uint8_t dst_bpc; // enum atom_panel_bit_per_color 2897 }; 2898 2899 2900 /****************************************************************************/ 2901 // Structures used by digxencodercontrol 2902 /****************************************************************************/ 2903 2904 // ucAction: 2905 enum atom_dig_encoder_control_action 2906 { 2907 ATOM_ENCODER_CMD_DISABLE_DIG = 0, 2908 ATOM_ENCODER_CMD_ENABLE_DIG = 1, 2909 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START = 0x08, 2910 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 = 0x09, 2911 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 = 0x0a, 2912 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 = 0x13, 2913 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE = 0x0b, 2914 ATOM_ENCODER_CMD_DP_VIDEO_OFF = 0x0c, 2915 ATOM_ENCODER_CMD_DP_VIDEO_ON = 0x0d, 2916 ATOM_ENCODER_CMD_SETUP_PANEL_MODE = 0x10, 2917 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4 = 0x14, 2918 ATOM_ENCODER_CMD_STREAM_SETUP = 0x0F, 2919 ATOM_ENCODER_CMD_LINK_SETUP = 0x11, 2920 ATOM_ENCODER_CMD_ENCODER_BLANK = 0x12, 2921 }; 2922 2923 //define ucPanelMode 2924 enum atom_dig_encoder_control_panelmode 2925 { 2926 DP_PANEL_MODE_DISABLE = 0x00, 2927 DP_PANEL_MODE_ENABLE_eDP_MODE = 0x01, 2928 DP_PANEL_MODE_ENABLE_LVLINK_MODE = 0x11, 2929 }; 2930 2931 //ucDigId 2932 enum atom_dig_encoder_control_v5_digid 2933 { 2934 ATOM_ENCODER_CONFIG_V5_DIG0_ENCODER = 0x00, 2935 ATOM_ENCODER_CONFIG_V5_DIG1_ENCODER = 0x01, 2936 ATOM_ENCODER_CONFIG_V5_DIG2_ENCODER = 0x02, 2937 ATOM_ENCODER_CONFIG_V5_DIG3_ENCODER = 0x03, 2938 ATOM_ENCODER_CONFIG_V5_DIG4_ENCODER = 0x04, 2939 ATOM_ENCODER_CONFIG_V5_DIG5_ENCODER = 0x05, 2940 ATOM_ENCODER_CONFIG_V5_DIG6_ENCODER = 0x06, 2941 ATOM_ENCODER_CONFIG_V5_DIG7_ENCODER = 0x07, 2942 }; 2943 2944 struct dig_encoder_stream_setup_parameters_v1_5 2945 { 2946 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 2947 uint8_t action; // = ATOM_ENOCODER_CMD_STREAM_SETUP 2948 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI 2949 uint8_t lanenum; // Lane number 2950 uint32_t pclk_10khz; // Pixel Clock in 10Khz 2951 uint8_t bitpercolor; 2952 uint8_t dplinkrate_270mhz;//= DP link rate/270Mhz, =6: 1.62G = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz etc 2953 uint8_t reserved[2]; 2954 }; 2955 2956 struct dig_encoder_link_setup_parameters_v1_5 2957 { 2958 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 2959 uint8_t action; // = ATOM_ENOCODER_CMD_LINK_SETUP 2960 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI 2961 uint8_t lanenum; // Lane number 2962 uint8_t symclk_10khz; // Symbol Clock in 10Khz 2963 uint8_t hpd_sel; 2964 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable, 2965 uint8_t reserved[2]; 2966 }; 2967 2968 struct dp_panel_mode_set_parameters_v1_5 2969 { 2970 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 2971 uint8_t action; // = ATOM_ENCODER_CMD_DPLINK_SETUP 2972 uint8_t panelmode; // enum atom_dig_encoder_control_panelmode 2973 uint8_t reserved1; 2974 uint32_t reserved2[2]; 2975 }; 2976 2977 struct dig_encoder_generic_cmd_parameters_v1_5 2978 { 2979 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 2980 uint8_t action; // = rest of generic encoder command which does not carry any parameters 2981 uint8_t reserved1[2]; 2982 uint32_t reserved2[2]; 2983 }; 2984 2985 union dig_encoder_control_parameters_v1_5 2986 { 2987 struct dig_encoder_generic_cmd_parameters_v1_5 cmd_param; 2988 struct dig_encoder_stream_setup_parameters_v1_5 stream_param; 2989 struct dig_encoder_link_setup_parameters_v1_5 link_param; 2990 struct dp_panel_mode_set_parameters_v1_5 dppanel_param; 2991 }; 2992 2993 /* 2994 *************************************************************************** 2995 Structures used by dig1transmittercontrol 2996 *************************************************************************** 2997 */ 2998 struct dig_transmitter_control_parameters_v1_6 2999 { 3000 uint8_t phyid; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF 3001 uint8_t action; // define as ATOM_TRANSMITER_ACTION_xxx 3002 union { 3003 uint8_t digmode; // enum atom_encode_mode_def 3004 uint8_t dplaneset; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP_LANE_SET__xDB_y_zV" 3005 } mode_laneset; 3006 uint8_t lanenum; // Lane number 1, 2, 4, 8 3007 uint32_t symclk_10khz; // Symbol Clock in 10Khz 3008 uint8_t hpdsel; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned 3009 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable, 3010 uint8_t connobj_id; // Connector Object Id defined in ObjectId.h 3011 uint8_t reserved; 3012 uint32_t reserved1; 3013 }; 3014 3015 struct dig_transmitter_control_ps_allocation_v1_6 3016 { 3017 struct dig_transmitter_control_parameters_v1_6 param; 3018 uint32_t reserved[4]; 3019 }; 3020 3021 //ucAction 3022 enum atom_dig_transmitter_control_action 3023 { 3024 ATOM_TRANSMITTER_ACTION_DISABLE = 0, 3025 ATOM_TRANSMITTER_ACTION_ENABLE = 1, 3026 ATOM_TRANSMITTER_ACTION_LCD_BLOFF = 2, 3027 ATOM_TRANSMITTER_ACTION_LCD_BLON = 3, 3028 ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL = 4, 3029 ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START = 5, 3030 ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP = 6, 3031 ATOM_TRANSMITTER_ACTION_INIT = 7, 3032 ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT = 8, 3033 ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT = 9, 3034 ATOM_TRANSMITTER_ACTION_SETUP = 10, 3035 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH = 11, 3036 ATOM_TRANSMITTER_ACTION_POWER_ON = 12, 3037 ATOM_TRANSMITTER_ACTION_POWER_OFF = 13, 3038 }; 3039 3040 // digfe_sel 3041 enum atom_dig_transmitter_control_digfe_sel 3042 { 3043 ATOM_TRANMSITTER_V6__DIGA_SEL = 0x01, 3044 ATOM_TRANMSITTER_V6__DIGB_SEL = 0x02, 3045 ATOM_TRANMSITTER_V6__DIGC_SEL = 0x04, 3046 ATOM_TRANMSITTER_V6__DIGD_SEL = 0x08, 3047 ATOM_TRANMSITTER_V6__DIGE_SEL = 0x10, 3048 ATOM_TRANMSITTER_V6__DIGF_SEL = 0x20, 3049 ATOM_TRANMSITTER_V6__DIGG_SEL = 0x40, 3050 }; 3051 3052 3053 //ucHPDSel 3054 enum atom_dig_transmitter_control_hpd_sel 3055 { 3056 ATOM_TRANSMITTER_V6_NO_HPD_SEL = 0x00, 3057 ATOM_TRANSMITTER_V6_HPD1_SEL = 0x01, 3058 ATOM_TRANSMITTER_V6_HPD2_SEL = 0x02, 3059 ATOM_TRANSMITTER_V6_HPD3_SEL = 0x03, 3060 ATOM_TRANSMITTER_V6_HPD4_SEL = 0x04, 3061 ATOM_TRANSMITTER_V6_HPD5_SEL = 0x05, 3062 ATOM_TRANSMITTER_V6_HPD6_SEL = 0x06, 3063 }; 3064 3065 // ucDPLaneSet 3066 enum atom_dig_transmitter_control_dplaneset 3067 { 3068 DP_LANE_SET__0DB_0_4V = 0x00, 3069 DP_LANE_SET__0DB_0_6V = 0x01, 3070 DP_LANE_SET__0DB_0_8V = 0x02, 3071 DP_LANE_SET__0DB_1_2V = 0x03, 3072 DP_LANE_SET__3_5DB_0_4V = 0x08, 3073 DP_LANE_SET__3_5DB_0_6V = 0x09, 3074 DP_LANE_SET__3_5DB_0_8V = 0x0a, 3075 DP_LANE_SET__6DB_0_4V = 0x10, 3076 DP_LANE_SET__6DB_0_6V = 0x11, 3077 DP_LANE_SET__9_5DB_0_4V = 0x18, 3078 }; 3079 3080 3081 3082 /****************************************************************************/ 3083 // Structures used by ExternalEncoderControl V2.4 3084 /****************************************************************************/ 3085 3086 struct external_encoder_control_parameters_v2_4 3087 { 3088 uint16_t pixelclock_10khz; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT 3089 uint8_t config; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT 3090 uint8_t action; // 3091 uint8_t encodermode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT 3092 uint8_t lanenum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT 3093 uint8_t bitpercolor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP 3094 uint8_t hpd_id; 3095 }; 3096 3097 3098 // ucAction 3099 enum external_encoder_control_action_def 3100 { 3101 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT = 0x00, 3102 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT = 0x01, 3103 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT = 0x07, 3104 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP = 0x0f, 3105 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF = 0x10, 3106 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING = 0x11, 3107 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION = 0x12, 3108 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP = 0x14, 3109 }; 3110 3111 // ucConfig 3112 enum external_encoder_control_v2_4_config_def 3113 { 3114 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK = 0x03, 3115 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ = 0x00, 3116 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ = 0x01, 3117 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ = 0x02, 3118 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_3_24GHZ = 0x03, 3119 EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MAKS = 0x70, 3120 EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 = 0x00, 3121 EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 = 0x10, 3122 EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 = 0x20, 3123 }; 3124 3125 struct external_encoder_control_ps_allocation_v2_4 3126 { 3127 struct external_encoder_control_parameters_v2_4 sExtEncoder; 3128 uint32_t reserved[2]; 3129 }; 3130 3131 3132 /* 3133 *************************************************************************** 3134 AMD ACPI Table 3135 3136 *************************************************************************** 3137 */ 3138 3139 struct amd_acpi_description_header{ 3140 uint32_t signature; 3141 uint32_t tableLength; //Length 3142 uint8_t revision; 3143 uint8_t checksum; 3144 uint8_t oemId[6]; 3145 uint8_t oemTableId[8]; //UINT64 OemTableId; 3146 uint32_t oemRevision; 3147 uint32_t creatorId; 3148 uint32_t creatorRevision; 3149 }; 3150 3151 struct uefi_acpi_vfct{ 3152 struct amd_acpi_description_header sheader; 3153 uint8_t tableUUID[16]; //0x24 3154 uint32_t vbiosimageoffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture. 3155 uint32_t lib1Imageoffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture. 3156 uint32_t reserved[4]; //0x3C 3157 }; 3158 3159 struct vfct_image_header{ 3160 uint32_t pcibus; //0x4C 3161 uint32_t pcidevice; //0x50 3162 uint32_t pcifunction; //0x54 3163 uint16_t vendorid; //0x58 3164 uint16_t deviceid; //0x5A 3165 uint16_t ssvid; //0x5C 3166 uint16_t ssid; //0x5E 3167 uint32_t revision; //0x60 3168 uint32_t imagelength; //0x64 3169 }; 3170 3171 3172 struct gop_vbios_content { 3173 struct vfct_image_header vbiosheader; 3174 uint8_t vbioscontent[1]; 3175 }; 3176 3177 struct gop_lib1_content { 3178 struct vfct_image_header lib1header; 3179 uint8_t lib1content[1]; 3180 }; 3181 3182 3183 3184 /* 3185 *************************************************************************** 3186 Scratch Register definitions 3187 Each number below indicates which scratch regiser request, Active and 3188 Connect all share the same definitions as display_device_tag defines 3189 *************************************************************************** 3190 */ 3191 3192 enum scratch_register_def{ 3193 ATOM_DEVICE_CONNECT_INFO_DEF = 0, 3194 ATOM_BL_BRI_LEVEL_INFO_DEF = 2, 3195 ATOM_ACTIVE_INFO_DEF = 3, 3196 ATOM_LCD_INFO_DEF = 4, 3197 ATOM_DEVICE_REQ_INFO_DEF = 5, 3198 ATOM_ACC_CHANGE_INFO_DEF = 6, 3199 ATOM_PRE_OS_MODE_INFO_DEF = 7, 3200 ATOM_PRE_OS_ASSERTION_DEF = 8, //For GOP to record a 32bit assertion code, this is enabled by default in prodution GOP drivers. 3201 ATOM_INTERNAL_TIMER_INFO_DEF = 10, 3202 }; 3203 3204 enum scratch_device_connect_info_bit_def{ 3205 ATOM_DISPLAY_LCD1_CONNECT =0x0002, 3206 ATOM_DISPLAY_DFP1_CONNECT =0x0008, 3207 ATOM_DISPLAY_DFP2_CONNECT =0x0080, 3208 ATOM_DISPLAY_DFP3_CONNECT =0x0200, 3209 ATOM_DISPLAY_DFP4_CONNECT =0x0400, 3210 ATOM_DISPLAY_DFP5_CONNECT =0x0800, 3211 ATOM_DISPLAY_DFP6_CONNECT =0x0040, 3212 ATOM_DISPLAY_DFPx_CONNECT =0x0ec8, 3213 ATOM_CONNECT_INFO_DEVICE_MASK =0x0fff, 3214 }; 3215 3216 enum scratch_bl_bri_level_info_bit_def{ 3217 ATOM_CURRENT_BL_LEVEL_SHIFT =0x8, 3218 #ifndef _H2INC 3219 ATOM_CURRENT_BL_LEVEL_MASK =0x0000ff00, 3220 ATOM_DEVICE_DPMS_STATE =0x00010000, 3221 #endif 3222 }; 3223 3224 enum scratch_active_info_bits_def{ 3225 ATOM_DISPLAY_LCD1_ACTIVE =0x0002, 3226 ATOM_DISPLAY_DFP1_ACTIVE =0x0008, 3227 ATOM_DISPLAY_DFP2_ACTIVE =0x0080, 3228 ATOM_DISPLAY_DFP3_ACTIVE =0x0200, 3229 ATOM_DISPLAY_DFP4_ACTIVE =0x0400, 3230 ATOM_DISPLAY_DFP5_ACTIVE =0x0800, 3231 ATOM_DISPLAY_DFP6_ACTIVE =0x0040, 3232 ATOM_ACTIVE_INFO_DEVICE_MASK =0x0fff, 3233 }; 3234 3235 enum scratch_device_req_info_bits_def{ 3236 ATOM_DISPLAY_LCD1_REQ =0x0002, 3237 ATOM_DISPLAY_DFP1_REQ =0x0008, 3238 ATOM_DISPLAY_DFP2_REQ =0x0080, 3239 ATOM_DISPLAY_DFP3_REQ =0x0200, 3240 ATOM_DISPLAY_DFP4_REQ =0x0400, 3241 ATOM_DISPLAY_DFP5_REQ =0x0800, 3242 ATOM_DISPLAY_DFP6_REQ =0x0040, 3243 ATOM_REQ_INFO_DEVICE_MASK =0x0fff, 3244 }; 3245 3246 enum scratch_acc_change_info_bitshift_def{ 3247 ATOM_ACC_CHANGE_ACC_MODE_SHIFT =4, 3248 ATOM_ACC_CHANGE_LID_STATUS_SHIFT =6, 3249 }; 3250 3251 enum scratch_acc_change_info_bits_def{ 3252 ATOM_ACC_CHANGE_ACC_MODE =0x00000010, 3253 ATOM_ACC_CHANGE_LID_STATUS =0x00000040, 3254 }; 3255 3256 enum scratch_pre_os_mode_info_bits_def{ 3257 ATOM_PRE_OS_MODE_MASK =0x00000003, 3258 ATOM_PRE_OS_MODE_VGA =0x00000000, 3259 ATOM_PRE_OS_MODE_VESA =0x00000001, 3260 ATOM_PRE_OS_MODE_GOP =0x00000002, 3261 ATOM_PRE_OS_MODE_PIXEL_DEPTH =0x0000000C, 3262 ATOM_PRE_OS_MODE_PIXEL_FORMAT_MASK=0x000000F0, 3263 ATOM_PRE_OS_MODE_8BIT_PAL_EN =0x00000100, 3264 ATOM_ASIC_INIT_COMPLETE =0x00000200, 3265 #ifndef _H2INC 3266 ATOM_PRE_OS_MODE_NUMBER_MASK =0xFFFF0000, 3267 #endif 3268 }; 3269 3270 3271 3272 /* 3273 *************************************************************************** 3274 ATOM firmware ID header file 3275 !! Please keep it at end of the atomfirmware.h !! 3276 *************************************************************************** 3277 */ 3278 #include "atomfirmwareid.h" 3279 #pragma pack() 3280 3281 #endif 3282 3283
Indexes created Sat Sep 20 22:09:52 GMT 2025