1 /* $NetBSD: atphy.c,v 1.33 2025/10/04 04:14:56 thorpej Exp $ */ 2 /* $OpenBSD: atphy.c,v 1.1 2008/09/25 20:47:16 brad Exp $ */ 3 4 /*- 5 * Copyright (c) 2008, Pyun YongHyeon <yongari (at) FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * Driver for the Attansic F1 10/100/1000 PHY. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: atphy.c,v 1.33 2025/10/04 04:14:56 thorpej Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <sys/socket.h> 43 44 #include <net/if.h> 45 #include <net/if_media.h> 46 47 #include <dev/mii/mii.h> 48 #include <dev/mii/miivar.h> 49 #include <dev/mii/miidevs.h> 50 51 /* Special Control Register */ 52 #define ATPHY_SCR 0x10 53 #define ATPHY_SCR_JABBER_DISABLE 0x0001 54 #define ATPHY_SCR_POLARITY_REVERSAL 0x0002 55 #define ATPHY_SCR_SQE_TEST 0x0004 56 #define ATPHY_SCR_MAC_PDOWN 0x0008 57 #define ATPHY_SCR_CLK125_DISABLE 0x0010 58 #define ATPHY_SCR_MDI_MANUAL_MODE 0x0000 59 #define ATPHY_SCR_MDIX_MANUAL_MODE 0x0020 60 #define ATPHY_SCR_AUTO_X_1000T 0x0040 61 #define ATPHY_SCR_AUTO_X_MODE 0x0060 62 #define ATPHY_SCR_10BT_EXT_ENABLE 0x0080 63 #define ATPHY_SCR_MII_5BIT_ENABLE 0x0100 64 #define ATPHY_SCR_SCRAMBLER_DISABLE 0x0200 65 #define ATPHY_SCR_FORCE_LINK_GOOD 0x0400 66 #define ATPHY_SCR_ASSERT_CRS_ON_TX 0x0800 67 68 /* Special Status Register. */ 69 #define ATPHY_SSR 0x11 70 #define ATPHY_SSR_SPD_DPLX_RESOLVED 0x0800 71 #define ATPHY_SSR_DUPLEX 0x2000 72 #define ATPHY_SSR_SPEED_MASK 0xC000 73 #define ATPHY_SSR_10MBS 0x0000 74 #define ATPHY_SSR_100MBS 0x4000 75 #define ATPHY_SSR_1000MBS 0x8000 76 77 #define ATPHY_DEBUG_PORT_ADDR 0x1d 78 #define ATPHY_DEBUG_PORT_DATA 0x1e 79 #define ATPHY_RGMII_RX_CLK_DLY __BIT(15) 80 #define ATPHY_RGMII_TX_CLK_DLY __BIT(8) 81 82 static int atphy_match(device_t, cfdata_t, void *); 83 static void atphy_attach(device_t, device_t, void *); 84 85 static int atphy_service(struct mii_softc *, struct mii_data *, int); 86 static void atphy_reset(struct mii_softc *); 87 static void atphy_status(struct mii_softc *); 88 static int atphy_mii_phy_auto(struct mii_softc *); 89 static bool atphy_is_gige(const struct mii_phydesc *); 90 91 struct atphy_softc { 92 struct mii_softc mii_sc; 93 int mii_clk_25m; 94 bool rgmii_tx_internal_delay; 95 bool rgmii_rx_internal_delay; 96 }; 97 98 CFATTACH_DECL_NEW(atphy, sizeof(struct atphy_softc), 99 atphy_match, atphy_attach, mii_phy_detach, mii_phy_activate); 100 101 const struct mii_phy_funcs atphy_funcs = { 102 atphy_service, atphy_status, atphy_reset, 103 }; 104 105 static const struct mii_phydesc atphys[] = { 106 MII_PHY_DESC(ATTANSIC, L1), 107 MII_PHY_DESC(ATTANSIC, L2), 108 MII_PHY_DESC(ATTANSIC, AR8021), 109 MII_PHY_DESC(ATTANSIC, AR8035), 110 MII_PHY_END, 111 }; 112 113 static void 114 atphy_clk_25m(struct atphy_softc *asc) 115 { 116 struct mii_softc *sc = &asc->mii_sc; 117 struct { 118 uint32_t hz; 119 uint16_t data; 120 } select_clk[] = { 121 { 25000000, 0x0 }, 122 { 50000000, 0x1 }, 123 { 62500000, 0x2 }, 124 { 125000000, 0x3 } 125 }; 126 uint16_t data = 0; 127 uint16_t reg = 0; 128 129 for (int i = 0; i < __arraycount(select_clk); i++) { 130 if (asc->mii_clk_25m <= select_clk[i].hz) 131 data = select_clk[i].data; 132 } 133 134 PHY_WRITE(sc, 0x0d, 0x0007); 135 PHY_WRITE(sc, 0x0e, 0x8016); 136 PHY_WRITE(sc, 0x0d, 0x4007); 137 PHY_READ(sc, 0x0e, ®); 138 PHY_WRITE(sc, 0x0e, reg | __SHIFTIN(data, __BITS(4, 3))); 139 } 140 141 142 static bool 143 atphy_is_gige(const struct mii_phydesc *mpd) 144 { 145 switch (mpd->mpd_oui) { 146 case MII_OUI_ATTANSIC: 147 switch (mpd->mpd_model) { 148 case MII_MODEL_ATTANSIC_L2: 149 return false; 150 } 151 } 152 153 return true; 154 } 155 156 static int 157 atphy_match(device_t parent, cfdata_t match, void *aux) 158 { 159 struct mii_attach_args *ma = aux; 160 161 if (mii_phy_match(ma, atphys) != NULL) 162 return 10; 163 164 return 0; 165 } 166 167 void 168 atphy_attach(device_t parent, device_t self, void *aux) 169 { 170 struct atphy_softc *asc = device_private(self); 171 prop_dictionary_t prop = device_properties(self); 172 struct mii_softc *sc = &asc->mii_sc; 173 struct mii_attach_args *ma = aux; 174 struct mii_data *mii = ma->mii_data; 175 const struct mii_phydesc *mpd; 176 uint16_t bmsr; 177 178 mpd = mii_phy_match(ma, atphys); 179 aprint_naive(": Media interface\n"); 180 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2)); 181 182 sc->mii_dev = self; 183 sc->mii_inst = mii->mii_instance; 184 sc->mii_phy = ma->mii_phyno; 185 sc->mii_mpd_oui = MII_OUI(ma->mii_id1, ma->mii_id2); 186 sc->mii_mpd_model = MII_MODEL(ma->mii_id2); 187 sc->mii_mpd_rev = MII_REV(ma->mii_id2); 188 sc->mii_funcs = &atphy_funcs; 189 sc->mii_pdata = mii; 190 sc->mii_flags = ma->mii_flags; 191 sc->mii_flags |= MIIF_NOLOOP; 192 193 asc->rgmii_tx_internal_delay = device_getprop_bool(parent, 194 "tx_internal_delay"); 195 asc->rgmii_rx_internal_delay = device_getprop_bool(parent, 196 "rx_internal_delay"); 197 198 prop_dictionary_get_uint32(prop, "clk_25m", &asc->mii_clk_25m); 199 if (asc->mii_clk_25m != 0) 200 atphy_clk_25m(asc); 201 202 mii_lock(mii); 203 204 PHY_RESET(sc); 205 206 PHY_READ(sc, MII_BMSR, &bmsr); 207 PHY_READ(sc, MII_BMSR, &bmsr); 208 sc->mii_capabilities = bmsr & ma->mii_capmask; 209 if (atphy_is_gige(mpd) && (sc->mii_capabilities & BMSR_EXTSTAT)) 210 PHY_READ(sc, MII_EXTSR, &sc->mii_extcapabilities); 211 212 mii_unlock(mii); 213 214 mii_phy_add_media(sc); 215 } 216 217 int 218 atphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 219 { 220 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 221 uint16_t anar, bmcr, bmsr; 222 223 KASSERT(mii_locked(mii)); 224 225 switch (cmd) { 226 case MII_POLLSTAT: 227 /* If we're not polling our PHY instance, just return. */ 228 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 229 return 0; 230 break; 231 232 case MII_MEDIACHG: 233 /* 234 * If the media indicates a different PHY instance, 235 * isolate ourselves. 236 */ 237 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 238 PHY_READ(sc, MII_BMCR, &bmcr); 239 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO); 240 return 0; 241 } 242 243 /* If the interface is not up, don't do anything. */ 244 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 245 break; 246 247 bmcr = 0; 248 switch (IFM_SUBTYPE(ife->ifm_media)) { 249 case IFM_AUTO: 250 case IFM_1000_T: 251 atphy_mii_phy_auto(sc); 252 goto done; 253 case IFM_100_TX: 254 bmcr = BMCR_S100; 255 break; 256 case IFM_10_T: 257 bmcr = BMCR_S10; 258 break; 259 case IFM_NONE: 260 PHY_READ(sc, MII_BMCR, &bmcr); 261 /* 262 * XXX 263 * Due to an unknown reason powering down PHY resulted 264 * in unexpected results such as inaccessibility of 265 * hardware of freshly rebooted system. Disable 266 * powering down PHY until I got more information for 267 * Attansic/Atheros PHY hardware. 268 */ 269 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO); 270 goto done; 271 default: 272 return EINVAL; 273 } 274 275 anar = mii_anar(ife); 276 if ((ife->ifm_media & IFM_FDX) != 0) { 277 bmcr |= BMCR_FDX; 278 /* Enable pause. */ 279 if (sc->mii_flags & MIIF_DOPAUSE) 280 anar |= ANAR_PAUSE_TOWARDS; 281 } 282 283 if ((sc->mii_extcapabilities & (EXTSR_1000TFDX | 284 EXTSR_1000THDX)) != 0) 285 PHY_WRITE(sc, MII_100T2CR, 0); 286 PHY_WRITE(sc, MII_ANAR, anar); 287 288 /* Start autonegotiation. */ 289 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_AUTOEN | BMCR_STARTNEG); 290 done: 291 break; 292 293 case MII_TICK: 294 /* If we're not currently selected, just return. */ 295 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 296 return 0; 297 298 /* Is the interface even up? */ 299 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 300 return 0; 301 302 /* Only used for autonegotiation. */ 303 if ((IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) && 304 (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)) { 305 sc->mii_ticks = 0; 306 break; 307 } 308 309 /* 310 * Check for link. 311 * Read the status register twice; BMSR_LINK is latch-low. 312 */ 313 PHY_READ(sc, MII_BMSR, &bmsr); 314 PHY_READ(sc, MII_BMSR, &bmsr); 315 if (bmsr & BMSR_LINK) { 316 sc->mii_ticks = 0; 317 break; 318 } 319 320 /* Announce link loss right after it happens. */ 321 if (sc->mii_ticks++ == 0) 322 break; 323 324 /* Only retry autonegotiation every mii_anegticks seconds. */ 325 if (sc->mii_ticks < sc->mii_anegticks) 326 break; 327 328 atphy_mii_phy_auto(sc); 329 break; 330 } 331 332 /* Update the media status. */ 333 mii_phy_status(sc); 334 335 /* Callback if something changed. */ 336 mii_phy_update(sc, cmd); 337 return 0; 338 } 339 340 static void 341 atphy_status(struct mii_softc *sc) 342 { 343 struct mii_data *mii = sc->mii_pdata; 344 uint16_t bmsr, bmcr, gsr, ssr; 345 346 KASSERT(mii_locked(mii)); 347 348 mii->mii_media_status = IFM_AVALID; 349 mii->mii_media_active = IFM_ETHER; 350 351 PHY_READ(sc, MII_BMSR, &bmsr); 352 PHY_READ(sc, MII_BMSR, &bmsr); 353 if (bmsr & BMSR_LINK) 354 mii->mii_media_status |= IFM_ACTIVE; 355 356 PHY_READ(sc, MII_BMCR, &bmcr); 357 if (bmcr & BMCR_ISO) { 358 mii->mii_media_active |= IFM_NONE; 359 mii->mii_media_status = 0; 360 return; 361 } 362 363 if (bmcr & BMCR_LOOP) 364 mii->mii_media_active |= IFM_LOOP; 365 366 PHY_READ(sc, ATPHY_SSR, &ssr); 367 if (!(ssr & ATPHY_SSR_SPD_DPLX_RESOLVED)) { 368 /* Erg, still trying, I guess... */ 369 mii->mii_media_active |= IFM_NONE; 370 return; 371 } 372 373 switch (ssr & ATPHY_SSR_SPEED_MASK) { 374 case ATPHY_SSR_1000MBS: 375 mii->mii_media_active |= IFM_1000_T; 376 /* 377 * atphy(4) has a valid link so reset mii_ticks. 378 * Resetting mii_ticks is needed in order to 379 * detect link loss after auto-negotiation. 380 */ 381 sc->mii_ticks = 0; 382 break; 383 case ATPHY_SSR_100MBS: 384 mii->mii_media_active |= IFM_100_TX; 385 sc->mii_ticks = 0; 386 break; 387 case ATPHY_SSR_10MBS: 388 mii->mii_media_active |= IFM_10_T; 389 sc->mii_ticks = 0; 390 break; 391 default: 392 mii->mii_media_active |= IFM_NONE; 393 return; 394 } 395 396 if (ssr & ATPHY_SSR_DUPLEX) 397 mii->mii_media_active |= IFM_FDX | mii_phy_flowstatus(sc); 398 else 399 mii->mii_media_active |= IFM_HDX; 400 401 PHY_READ(sc, MII_100T2SR, &gsr); 402 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) && 403 gsr & GTSR_MS_RES) 404 mii->mii_media_active |= IFM_ETH_MASTER; 405 } 406 407 static void 408 atphy_reset(struct mii_softc *sc) 409 { 410 struct atphy_softc *asc = (struct atphy_softc *)sc; 411 uint16_t reg; 412 int i; 413 414 KASSERT(mii_locked(sc->mii_pdata)); 415 416 /* 417 * Take PHY out of power down mode. 418 * 419 * XXX AR8021 document has no description about the power saving 420 * control register. Shouldn't we write it? 421 */ 422 PHY_WRITE(sc, 29, 0x29); 423 /* 424 * XXX AR8031 document says the lower 14 bits are reserved and the 425 * default value is 0x36d0. Shouldn't we clear those bits? 426 * I have no document neither L1(F1) nor L2(F2). 427 */ 428 PHY_WRITE(sc, 30, 0); 429 430 if ((sc->mii_mpd_model == MII_MODEL_ATTANSIC_L2) 431 && (sc->mii_mpd_rev == 1)) { 432 /* 433 * On NVIDIA MCP61 with Attansic L2 rev. 1, changing debug 434 * port 0x29's value makes the next PHY read fail with error. 435 * This is observed on ASUS M2N-MX SE Plus. Read any register 436 * to ignore this problem. 437 */ 438 (void)PHY_READ(sc, ATPHY_SCR, ®); 439 } 440 PHY_READ(sc, ATPHY_SCR, ®); 441 /* Enable automatic crossover. */ 442 reg |= ATPHY_SCR_AUTO_X_MODE; 443 /* Disable power down. */ 444 reg &= ~ATPHY_SCR_MAC_PDOWN; 445 /* Enable CRS on Tx. */ 446 reg |= ATPHY_SCR_ASSERT_CRS_ON_TX; 447 /* Auto correction for reversed cable polarity. */ 448 reg |= ATPHY_SCR_POLARITY_REVERSAL; 449 PHY_WRITE(sc, ATPHY_SCR, reg); 450 451 atphy_mii_phy_auto(sc); 452 453 /* Workaround F1 bug to reset phy. */ 454 PHY_READ(sc, MII_BMCR, ®); 455 reg |= BMCR_RESET; 456 PHY_WRITE(sc, MII_BMCR, reg); 457 458 for (i = 0; i < 1000; i++) { 459 DELAY(1); 460 PHY_READ(sc, MII_BMCR, ®); 461 if ((reg & BMCR_RESET) == 0) 462 break; 463 } 464 465 if (asc->rgmii_tx_internal_delay) { 466 PHY_WRITE(sc, ATPHY_DEBUG_PORT_ADDR, 0x05); 467 PHY_WRITE(sc, ATPHY_DEBUG_PORT_DATA, ATPHY_RGMII_TX_CLK_DLY); 468 } 469 if (asc->rgmii_rx_internal_delay) { 470 PHY_WRITE(sc, ATPHY_DEBUG_PORT_ADDR, 0x00); 471 PHY_WRITE(sc, ATPHY_DEBUG_PORT_DATA, ATPHY_RGMII_RX_CLK_DLY); 472 } 473 } 474 475 static int 476 atphy_mii_phy_auto(struct mii_softc *sc) 477 { 478 uint16_t anar; 479 480 KASSERT(mii_locked(sc->mii_pdata)); 481 482 sc->mii_ticks = 0; 483 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 484 if (sc->mii_flags & MIIF_DOPAUSE) 485 anar |= ANAR_PAUSE_TOWARDS; 486 PHY_WRITE(sc, MII_ANAR, anar); 487 if (sc->mii_extcapabilities & (EXTSR_1000TFDX | EXTSR_1000THDX)) 488 PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000TFDX | 489 GTCR_ADV_1000THDX); 490 PHY_WRITE(sc, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 491 492 return EJUSTRETURN; 493 } 494
Indexes created Thu Oct 23 18:09:57 GMT 2025