1 /* $NetBSD: pccbb.c,v 1.217 2021/08/07 16:19:14 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.217 2021/08/07 16:19:14 thorpej Exp $"); 30 31 /* 32 #define CBB_DEBUG 33 #define SHOW_REGS 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/kernel.h> 39 #include <sys/errno.h> 40 #include <sys/ioctl.h> 41 #include <sys/reboot.h> /* for bootverbose */ 42 #include <sys/syslog.h> 43 #include <sys/device.h> 44 #include <sys/malloc.h> 45 #include <sys/proc.h> 46 47 #include <sys/intr.h> 48 #include <sys/bus.h> 49 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcidevs.h> 53 54 #include <dev/pci/pccbbreg.h> 55 56 #include <dev/cardbus/cardslotvar.h> 57 #include <dev/cardbus/cardbusvar.h> 58 59 #include <dev/pcmcia/pcmciareg.h> 60 #include <dev/pcmcia/pcmciavar.h> 61 62 #include <dev/ic/i82365reg.h> 63 #include <dev/pci/pccbbvar.h> 64 65 #ifndef __NetBSD_Version__ 66 struct cfdriver cbb_cd = { 67 NULL, "cbb", DV_DULL 68 }; 69 #endif 70 71 #ifdef CBB_DEBUG 72 #define DPRINTF(x) printf x 73 #define STATIC 74 #else 75 #define DPRINTF(x) 76 #define STATIC static 77 #endif 78 79 int pccbb_burstup = 1; 80 81 /* 82 * delay_ms() is wait in milliseconds. It should be used instead 83 * of delay() if you want to wait more than 1 ms. 84 */ 85 static inline void 86 delay_ms(int millis, struct pccbb_softc *sc) 87 { 88 if (cold) 89 delay(millis * 1000); 90 else 91 kpause("pccbb", false, mstohz(millis), NULL); 92 } 93 94 int pcicbbmatch(device_t, cfdata_t, void *); 95 void pccbbattach(device_t, device_t, void *); 96 void pccbbchilddet(device_t, device_t); 97 int pccbbdetach(device_t, int); 98 int pccbbintr(void *); 99 static void pci113x_insert(void *); 100 static int pccbbintr_function(struct pccbb_softc *); 101 102 static int pccbb_detect_card(struct pccbb_softc *); 103 104 static void pccbb_pcmcia_write(struct pccbb_softc *, int, uint8_t); 105 static uint8_t pccbb_pcmcia_read(struct pccbb_softc *, int); 106 #define Pcic_read(sc, reg) pccbb_pcmcia_read((sc), (reg)) 107 #define Pcic_write(sc, reg, val) pccbb_pcmcia_write((sc), (reg), (val)) 108 109 STATIC int cb_reset(struct pccbb_softc *); 110 STATIC int cb_detect_voltage(struct pccbb_softc *); 111 STATIC int cbbprint(void *, const char *); 112 113 static int cb_chipset(uint32_t, int *); 114 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 115 struct pcmciabus_attach_args *); 116 117 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 118 STATIC int pccbb_power(struct pccbb_softc *, int); 119 STATIC int pccbb_power_ct(cardbus_chipset_tag_t, int); 120 STATIC int pccbb_cardenable(struct pccbb_softc *, int); 121 static void *pccbb_intr_establish(struct pccbb_softc *, 122 int, int (*ih) (void *), void *); 123 static void pccbb_intr_disestablish(struct pccbb_softc *, void *); 124 125 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, 126 int, int (*ih) (void *), void *); 127 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t, void *); 128 129 static pcitag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 130 static pcireg_t pccbb_conf_read(cardbus_chipset_tag_t, pcitag_t, int); 131 static void pccbb_conf_write(cardbus_chipset_tag_t, pcitag_t, int, pcireg_t); 132 static void pccbb_chipinit(struct pccbb_softc *); 133 static void pccbb_intrinit(struct pccbb_softc *); 134 135 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 136 struct pcmcia_mem_handle *); 137 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 138 struct pcmcia_mem_handle *); 139 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 140 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 141 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 142 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 143 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 144 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 145 struct pcmcia_io_handle *); 146 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 147 bus_size_t, struct pcmcia_io_handle *, int *); 148 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 149 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 150 struct pcmcia_function *, int, int (*)(void *), void *); 151 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 152 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 153 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 154 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 155 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t); 156 157 static int pccbb_pcmcia_wait_ready(struct pccbb_softc *); 158 static void pccbb_pcmcia_delay(struct pccbb_softc *, int, const char *); 159 160 static void pccbb_pcmcia_do_io_map(struct pccbb_softc *, int); 161 static void pccbb_pcmcia_do_mem_map(struct pccbb_softc *, int); 162 163 /* bus-space allocation and deallocation functions */ 164 165 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 166 bus_addr_t, bus_size_t, bus_addr_t, bus_size_t, 167 int, bus_addr_t *, bus_space_handle_t *); 168 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 169 bus_space_handle_t, bus_size_t); 170 171 172 173 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 174 bus_addr_t, bus_size_t, bus_space_handle_t, int); 175 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 176 bus_space_handle_t, bus_size_t); 177 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 178 bus_size_t, bus_space_handle_t, int); 179 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 180 bus_space_handle_t, bus_size_t); 181 static void pccbb_winset(bus_addr_t, struct pccbb_softc *, bus_space_tag_t); 182 void pccbb_winlist_show(struct pccbb_win_chain *); 183 184 185 /* for config_defer */ 186 static void pccbb_pci_callback(device_t); 187 188 static bool pccbb_suspend(device_t, const pmf_qual_t *); 189 static bool pccbb_resume(device_t, const pmf_qual_t *); 190 191 #if defined SHOW_REGS 192 static void cb_show_regs(pci_chipset_tag_t, pcitag_t, 193 bus_space_tag_t, bus_space_handle_t); 194 #endif 195 196 CFATTACH_DECL3_NEW(cbb_pci, sizeof(struct pccbb_softc), 197 pcicbbmatch, pccbbattach, pccbbdetach, NULL, NULL, pccbbchilddet, 198 DVF_DETACH_SHUTDOWN); 199 200 static const struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 201 pccbb_pcmcia_mem_alloc, 202 pccbb_pcmcia_mem_free, 203 pccbb_pcmcia_mem_map, 204 pccbb_pcmcia_mem_unmap, 205 pccbb_pcmcia_io_alloc, 206 pccbb_pcmcia_io_free, 207 pccbb_pcmcia_io_map, 208 pccbb_pcmcia_io_unmap, 209 pccbb_pcmcia_intr_establish, 210 pccbb_pcmcia_intr_disestablish, 211 pccbb_pcmcia_socket_enable, 212 pccbb_pcmcia_socket_disable, 213 pccbb_pcmcia_socket_settype, 214 pccbb_pcmcia_card_detect 215 }; 216 217 static const struct cardbus_functions pccbb_funcs = { 218 pccbb_rbus_cb_space_alloc, 219 pccbb_rbus_cb_space_free, 220 pccbb_cb_intr_establish, 221 pccbb_cb_intr_disestablish, 222 pccbb_ctrl, 223 pccbb_power_ct, 224 pccbb_make_tag, 225 pccbb_conf_read, 226 pccbb_conf_write, 227 }; 228 229 int 230 pcicbbmatch(device_t parent, cfdata_t match, void *aux) 231 { 232 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 233 234 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 235 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 236 PCI_INTERFACE(pa->pa_class) == 0) { 237 return 1; 238 } 239 240 return 0; 241 } 242 243 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 244 | ((prod) << PCI_PRODUCT_SHIFT)) 245 246 const struct yenta_chipinfo { 247 pcireg_t yc_id; /* vendor tag | product tag */ 248 int yc_chiptype; 249 int yc_flags; 250 } yc_chipsets[] = { 251 /* Texas Instruments chips */ 252 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 253 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 254 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 255 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 256 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 257 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 258 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 259 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 260 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 261 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 262 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 263 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 264 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 265 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 266 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 267 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 268 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 269 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 270 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 271 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 272 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI1420, 273 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 274 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 275 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 276 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 277 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 278 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1510), CB_TI12XX, 279 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 280 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 281 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 282 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 283 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 284 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 285 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 286 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI7420YENTA), CB_TI12XX, 287 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 288 289 /* Ricoh chips */ 290 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 291 PCCBB_PCMCIA_MEM_32}, 292 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 293 PCCBB_PCMCIA_MEM_32}, 294 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 295 PCCBB_PCMCIA_MEM_32}, 296 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 297 PCCBB_PCMCIA_MEM_32}, 298 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 299 PCCBB_PCMCIA_MEM_32}, 300 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 301 PCCBB_PCMCIA_MEM_32}, 302 303 /* Toshiba products */ 304 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 305 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 306 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 307 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 309 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 311 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 312 313 /* Cirrus Logic products */ 314 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 315 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 317 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 318 319 /* O2 Micro products */ 320 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6729), 321 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 322 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6730), 323 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6832), 325 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6836), 327 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 328 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6872), 329 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 330 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6922), 331 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 332 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6933), 333 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 334 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6972), 335 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 336 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_7223), 337 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 338 339 /* sentinel, or Generic chip */ 340 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 341 }; 342 343 static int 344 cb_chipset(uint32_t pci_id, int *flagp) 345 { 346 const struct yenta_chipinfo *yc; 347 348 /* Loop over except the last default entry. */ 349 for (yc = yc_chipsets; yc < yc_chipsets + 350 __arraycount(yc_chipsets) - 1; yc++) 351 if (pci_id == yc->yc_id) 352 break; 353 354 if (flagp != NULL) 355 *flagp = yc->yc_flags; 356 357 return yc->yc_chiptype; 358 } 359 360 void 361 pccbbchilddet(device_t self, device_t child) 362 { 363 struct pccbb_softc *sc = device_private(self); 364 int s; 365 366 KASSERT(sc->sc_csc == device_private(child)); 367 368 s = splbio(); 369 if (sc->sc_csc == device_private(child)) 370 sc->sc_csc = NULL; 371 splx(s); 372 } 373 374 void 375 pccbbattach(device_t parent, device_t self, void *aux) 376 { 377 struct pccbb_softc *sc = device_private(self); 378 struct pci_attach_args *pa = aux; 379 pci_chipset_tag_t pc = pa->pa_pc; 380 pcireg_t reg, sock_base; 381 bus_addr_t sockbase; 382 int flags; 383 384 #ifdef __HAVE_PCCBB_ATTACH_HOOK 385 pccbb_attach_hook(parent, self, pa); 386 #endif 387 388 sc->sc_dev = self; 389 390 mutex_init(&sc->sc_pwr_mtx, MUTEX_DEFAULT, IPL_BIO); 391 cv_init(&sc->sc_pwr_cv, "pccpwr"); 392 393 callout_init(&sc->sc_insert_ch, 0); 394 callout_setfunc(&sc->sc_insert_ch, pci113x_insert, sc); 395 396 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 397 398 pci_aprint_devinfo(pa, NULL); 399 DPRINTF(("(chipflags %x)", flags)); 400 401 TAILQ_INIT(&sc->sc_memwindow); 402 TAILQ_INIT(&sc->sc_iowindow); 403 404 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 405 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 406 407 #if 0 408 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 409 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 410 #endif 411 412 sc->sc_flags &= ~CBB_MEMHMAPPED; 413 414 /* 415 * MAP socket registers and ExCA registers on memory-space 416 * When no valid address is set on socket base registers (on pci 417 * config space), get it not polite way. 418 */ 419 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 420 421 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 422 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 423 /* The address must be valid. */ 424 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 425 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 426 &sc->sc_base_size)) { 427 aprint_error_dev(self, 428 "can't map socket base address 0x%lx\n", 429 (unsigned long)sock_base); 430 /* 431 * I think it's funny: socket base registers must be 432 * mapped on memory space, but ... 433 */ 434 if (pci_mapreg_map(pa, PCI_SOCKBASE, 435 PCI_MAPREG_TYPE_IO, 0, &sc->sc_base_memt, 436 &sc->sc_base_memh, &sockbase, &sc->sc_base_size)) { 437 aprint_error_dev(self, 438 "can't map socket base address" 439 " 0x%lx: io mode\n", 440 (unsigned long)sockbase); 441 /* give up... allocate reg space via rbus. */ 442 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 443 } else 444 sc->sc_flags |= CBB_MEMHMAPPED; 445 } else { 446 DPRINTF(("%s: socket base address 0x%lx\n", 447 device_xname(self), (unsigned long)sockbase)); 448 sc->sc_flags |= CBB_MEMHMAPPED; 449 } 450 } 451 452 sc->sc_mem_start = 0; /* XXX */ 453 sc->sc_mem_end = 0xffffffff; /* XXX */ 454 455 /* pccbb_machdep.c end */ 456 457 #if defined CBB_DEBUG 458 { 459 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 460 aprint_debug_dev(self, "intrpin %s, intrtag %d\n", 461 intrname[pa->pa_intrpin], pa->pa_intrline); 462 } 463 #endif 464 465 /* setup softc */ 466 sc->sc_pc = pc; 467 sc->sc_iot = pa->pa_iot; 468 sc->sc_memt = pa->pa_memt; 469 sc->sc_dmat = pa->pa_dmat; 470 sc->sc_tag = pa->pa_tag; 471 472 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 473 474 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 475 476 /* Disable legacy register mapping. */ 477 switch (sc->sc_chipset) { 478 case CB_RX5C46X: /* fallthrough */ 479 #if 0 480 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 481 case CB_RX5C47X: 482 #endif 483 /* 484 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 485 * cannot be disabled by substituting 0 into PCI_LEGACY 486 * register. Ricoh CardBus bridges have special bits on Bridge 487 * control reg (addr 0x3e on PCI config space). 488 */ 489 reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG); 490 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 491 pci_conf_write(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG, reg); 492 break; 493 494 default: 495 /* XXX I don't know proper way to kill legacy I/O. */ 496 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 497 break; 498 } 499 500 if (!pmf_device_register(self, pccbb_suspend, pccbb_resume)) 501 aprint_error_dev(self, "couldn't establish power handler\n"); 502 503 config_defer(self, pccbb_pci_callback); 504 } 505 506 int 507 pccbbdetach(device_t self, int flags) 508 { 509 struct pccbb_softc *sc = device_private(self); 510 pci_chipset_tag_t pc = sc->sc_pa.pa_pc; 511 bus_space_tag_t bmt = sc->sc_base_memt; 512 bus_space_handle_t bmh = sc->sc_base_memh; 513 uint32_t sockmask; 514 int rc; 515 516 if ((rc = config_detach_children(self, flags)) != 0) 517 return rc; 518 519 if (!LIST_EMPTY(&sc->sc_pil)) { 520 panic("%s: interrupt handlers still registered", 521 device_xname(self)); 522 return EBUSY; 523 } 524 525 if (sc->sc_ih != NULL) { 526 pci_intr_disestablish(pc, sc->sc_ih); 527 sc->sc_ih = NULL; 528 } 529 530 /* CSC Interrupt: turn off card detect and power cycle interrupts */ 531 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 532 sockmask &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | 533 CB_SOCKET_MASK_POWER); 534 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 535 /* reset interrupt */ 536 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 537 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 538 539 switch (sc->sc_flags & (CBB_MEMHMAPPED|CBB_SPECMAPPED)) { 540 case CBB_MEMHMAPPED: 541 bus_space_unmap(bmt, bmh, sc->sc_base_size); 542 break; 543 case CBB_MEMHMAPPED|CBB_SPECMAPPED: 544 #if rbus 545 { 546 rbus_space_free(sc->sc_rbus_memt, bmh, 0x1000, NULL); 547 } 548 #else 549 bus_space_free(bmt, bmh, 0x1000); 550 #endif 551 } 552 sc->sc_flags &= ~(CBB_MEMHMAPPED|CBB_SPECMAPPED); 553 554 if (!TAILQ_EMPTY(&sc->sc_iowindow)) 555 aprint_error_dev(self, "i/o windows not empty\n"); 556 if (!TAILQ_EMPTY(&sc->sc_memwindow)) 557 aprint_error_dev(self, "memory windows not empty\n"); 558 559 callout_halt(&sc->sc_insert_ch, NULL); 560 callout_destroy(&sc->sc_insert_ch); 561 562 mutex_destroy(&sc->sc_pwr_mtx); 563 cv_destroy(&sc->sc_pwr_cv); 564 565 return 0; 566 } 567 568 /* 569 * static void pccbb_pci_callback(device_t self) 570 * 571 * The actual attach routine: get memory space for YENTA register 572 * space, setup YENTA register and route interrupt. 573 * 574 * This function should be deferred because this device may obtain 575 * memory space dynamically. This function must avoid obtaining 576 * memory area which has already kept for another device. 577 */ 578 static void 579 pccbb_pci_callback(device_t self) 580 { 581 struct pccbb_softc *sc = device_private(self); 582 pci_chipset_tag_t pc = sc->sc_pc; 583 bus_addr_t sockbase; 584 struct cbslot_attach_args cba; 585 struct pcmciabus_attach_args paa; 586 struct cardslot_attach_args caa; 587 device_t csc; 588 589 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 590 /* The socket registers aren't mapped correctly. */ 591 #if rbus 592 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 593 (sc->sc_chipset == CB_RX5C47X 594 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 595 0, &sockbase, &sc->sc_base_memh)) { 596 return; 597 } 598 sc->sc_base_memt = sc->sc_memt; 599 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 600 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 601 device_xname(self), (unsigned long)sockbase, 602 (unsigned long)pci_conf_read(pc, sc->sc_tag, 603 PCI_SOCKBASE))); 604 #else 605 sc->sc_base_memt = sc->sc_memt; 606 #if !defined CBB_PCI_BASE 607 #define CBB_PCI_BASE 0x20000000 608 #endif 609 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 610 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 611 /* cannot allocate memory space */ 612 return; 613 } 614 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 615 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 616 device_xname(self), (unsigned long)sock_base, 617 (unsigned long)pci_conf_read(pc, 618 sc->sc_tag, PCI_SOCKBASE))); 619 #endif 620 sc->sc_flags |= CBB_MEMHMAPPED|CBB_SPECMAPPED; 621 } 622 623 /* clear data structure for child device interrupt handlers */ 624 LIST_INIT(&sc->sc_pil); 625 626 /* bus bridge initialization */ 627 pccbb_chipinit(sc); 628 629 sc->sc_pil_intr_enable = true; 630 631 { 632 uint32_t sockstat; 633 634 sockstat = bus_space_read_4(sc->sc_base_memt, 635 sc->sc_base_memh, CB_SOCKET_STAT); 636 if (0 == (sockstat & CB_SOCKET_STAT_CD)) 637 sc->sc_flags |= CBB_CARDEXIST; 638 } 639 640 /* 641 * attach cardbus 642 */ 643 { 644 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 645 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 646 647 /* initialize cbslot_attach */ 648 cba.cba_iot = sc->sc_iot; 649 cba.cba_memt = sc->sc_memt; 650 cba.cba_dmat = sc->sc_dmat; 651 cba.cba_bus = (busreg >> 8) & 0x0ff; 652 cba.cba_cc = (void *)sc; 653 cba.cba_cf = &pccbb_funcs; 654 655 #if rbus 656 cba.cba_rbus_iot = sc->sc_rbus_iot; 657 cba.cba_rbus_memt = sc->sc_rbus_memt; 658 #endif 659 660 cba.cba_cacheline = PCI_CACHELINE(bhlc); 661 cba.cba_max_lattimer = PCI_LATTIMER(bhlc); 662 663 aprint_verbose_dev(self, "cacheline 0x%x lattimer 0x%x\n", 664 cba.cba_cacheline, cba.cba_max_lattimer); 665 aprint_verbose_dev(self, "bhlc 0x%x\n", bhlc); 666 #if defined SHOW_REGS 667 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 668 sc->sc_base_memh); 669 #endif 670 } 671 672 pccbb_pcmcia_attach_setup(sc, &paa); 673 caa.caa_cb_attach = NULL; 674 if (cba.cba_bus == 0) 675 aprint_error_dev(self, 676 "secondary bus number uninitialized; try PCI_BUS_FIXUP\n"); 677 else 678 caa.caa_cb_attach = &cba; 679 caa.caa_16_attach = &paa; 680 681 pccbb_intrinit(sc); 682 683 if (NULL != (csc = config_found(self, &caa, cbbprint, 684 CFARGS(.iattr = "pcmciaslot")))) { 685 DPRINTF(("%s: found cardslot\n", __func__)); 686 sc->sc_csc = device_private(csc); 687 } 688 689 return; 690 } 691 692 693 694 695 696 /* 697 * static void pccbb_chipinit(struct pccbb_softc *sc) 698 * 699 * This function initialize YENTA chip registers listed below: 700 * 1) PCI command reg, 701 * 2) PCI and CardBus latency timer, 702 * 3) route PCI interrupt, 703 * 4) close all memory and io windows. 704 * 5) turn off bus power. 705 * 6) card detect and power cycle interrupts on. 706 * 7) clear interrupt 707 */ 708 static void 709 pccbb_chipinit(struct pccbb_softc *sc) 710 { 711 pci_chipset_tag_t pc = sc->sc_pc; 712 pcitag_t tag = sc->sc_tag; 713 bus_space_tag_t bmt = sc->sc_base_memt; 714 bus_space_handle_t bmh = sc->sc_base_memh; 715 pcireg_t bcr, bhlc, cbctl, csr, lscp, mfunc, mrburst, slotctl, sockctl, 716 sysctrl; 717 718 /* 719 * Set PCI command reg. 720 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 721 */ 722 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 723 /* I believe it is harmless. */ 724 csr |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 725 PCI_COMMAND_MASTER_ENABLE); 726 727 /* All O2 Micro chips have broken parity-error reporting 728 * until proven otherwise. The OZ6933 PCI-CardBus Bridge 729 * is known to have the defect---see PR kern/38698. 730 */ 731 if (sc->sc_chipset != CB_O2MICRO) 732 csr |= PCI_COMMAND_PARITY_ENABLE; 733 734 csr |= PCI_COMMAND_SERR_ENABLE; 735 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 736 737 /* 738 * Set CardBus latency timer. 739 */ 740 lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 741 if (PCI_CB_LATENCY(lscp) < 0x20) { 742 lscp &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 743 lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 744 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, lscp); 745 } 746 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 747 PCI_CB_LATENCY(lscp), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 748 749 /* 750 * Set PCI latency timer. 751 */ 752 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 753 if (PCI_LATTIMER(bhlc) < 0x10) { 754 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 755 bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 756 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 757 } 758 DPRINTF(("PCI latency timer 0x%x (%x)\n", 759 PCI_LATTIMER(bhlc), pci_conf_read(pc, tag, PCI_BHLC_REG))); 760 761 762 /* Route functional interrupts to PCI. */ 763 bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 764 bcr |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 765 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 766 /* assert reset */ 767 bcr |= PCI_BRIDGE_CONTROL_SECBR; 768 /* Set master abort mode to 1, forward SERR# from secondary 769 * to primary, and detect parity errors on secondary. 770 */ 771 bcr |= PCI_BRIDGE_CONTROL_MABRT; 772 bcr |= PCI_BRIDGE_CONTROL_SERR; 773 bcr |= PCI_BRIDGE_CONTROL_PERE; 774 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 775 776 switch (sc->sc_chipset) { 777 case CB_TI113X: 778 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 779 /* This bit is shared, but may read as 0 on some chips, so set 780 it explicitly on both functions. */ 781 cbctl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 782 /* CSC intr enable */ 783 cbctl |= PCI113X_CBCTRL_PCI_CSC; 784 /* functional intr prohibit | prohibit ISA routing */ 785 cbctl &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 786 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 787 break; 788 789 case CB_TI1420: 790 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 791 mrburst = pccbb_burstup 792 ? PCI1420_SYSCTRL_MRBURST : PCI1420_SYSCTRL_MRBURSTDN; 793 if ((sysctrl & PCI1420_SYSCTRL_MRBURST) == mrburst) { 794 printf("%s: %swrite bursts enabled\n", 795 device_xname(sc->sc_dev), 796 pccbb_burstup ? "read/" : ""); 797 } else if (pccbb_burstup) { 798 printf("%s: enabling read/write bursts\n", 799 device_xname(sc->sc_dev)); 800 sysctrl |= PCI1420_SYSCTRL_MRBURST; 801 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 802 } else { 803 printf("%s: disabling read bursts, " 804 "enabling write bursts\n", 805 device_xname(sc->sc_dev)); 806 sysctrl |= PCI1420_SYSCTRL_MRBURSTDN; 807 sysctrl &= ~PCI1420_SYSCTRL_MRBURSTUP; 808 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 809 } 810 /*FALLTHROUGH*/ 811 case CB_TI12XX: 812 /* 813 * Some TI 12xx (and [14][45]xx) based pci cards 814 * sometimes have issues with the MFUNC register not 815 * being initialized due to a bad EEPROM on board. 816 * Laptops that this matters on have this register 817 * properly initialized. 818 * 819 * The TI125X parts have a different register. 820 */ 821 mfunc = pci_conf_read(pc, tag, PCI12XX_MFUNC); 822 if ((mfunc & (PCI12XX_MFUNC_PIN0 | PCI12XX_MFUNC_PIN1)) == 0) { 823 /* Enable PCI interrupt /INTA */ 824 mfunc |= PCI12XX_MFUNC_PIN0_INTA; 825 826 /* XXX this is TI1520 only */ 827 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 828 PCI12XX_SYSCTRL_INTRTIE) == 0) 829 /* Enable PCI interrupt /INTB */ 830 mfunc |= PCI12XX_MFUNC_PIN1_INTB; 831 832 pci_conf_write(pc, tag, PCI12XX_MFUNC, mfunc); 833 } 834 /* fallthrough */ 835 836 case CB_TI125X: 837 /* 838 * Disable zoom video. Some machines initialize this 839 * improperly and experience has shown that this helps 840 * prevent strange behavior. 841 */ 842 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 843 844 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 845 sysctrl |= PCI12XX_SYSCTRL_VCCPROT; 846 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 847 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 848 cbctl |= PCI12XX_CBCTRL_CSC; 849 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 850 break; 851 852 case CB_TOPIC95B: 853 sockctl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 854 sockctl |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 855 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, sockctl); 856 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 857 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 858 device_xname(sc->sc_dev), slotctl)); 859 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 860 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 861 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 862 DPRINTF(("0x%x\n", slotctl)); 863 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 864 break; 865 866 case CB_TOPIC97: 867 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 868 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 869 device_xname(sc->sc_dev), slotctl)); 870 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 871 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 872 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 873 slotctl |= TOPIC97_SLOT_CTRL_PCIINT; 874 slotctl &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 875 DPRINTF(("0x%x\n", slotctl)); 876 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 877 /* make sure to assert LV card support bits */ 878 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 879 0x800 + 0x3e, 880 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 881 0x800 + 0x3e) | 0x03); 882 break; 883 } 884 885 /* Close all memory and I/O windows. */ 886 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 887 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 888 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 889 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 890 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 891 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 892 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 893 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 894 895 /* reset 16-bit pcmcia bus */ 896 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 897 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 898 899 /* turn off power */ 900 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 901 } 902 903 static void 904 pccbb_intrinit(struct pccbb_softc *sc) 905 { 906 pcireg_t sockmask; 907 const char *intrstr = NULL; 908 pci_intr_handle_t ih; 909 pci_chipset_tag_t pc = sc->sc_pc; 910 bus_space_tag_t bmt = sc->sc_base_memt; 911 bus_space_handle_t bmh = sc->sc_base_memh; 912 char intrbuf[PCI_INTRSTR_LEN]; 913 914 /* Map and establish the interrupt. */ 915 if (pci_intr_map(&sc->sc_pa, &ih)) { 916 aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n"); 917 return; 918 } 919 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 920 921 /* 922 * XXX pccbbintr should be called under the priority lower 923 * than any other hard interrupts. 924 */ 925 KASSERT(sc->sc_ih == NULL); 926 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_BIO, pccbbintr, sc, 927 device_xname(sc->sc_dev)); 928 929 if (sc->sc_ih == NULL) { 930 aprint_error_dev(sc->sc_dev, "couldn't establish interrupt"); 931 if (intrstr != NULL) 932 aprint_error(" at %s\n", intrstr); 933 else 934 aprint_error("\n"); 935 return; 936 } 937 938 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 939 940 /* CSC Interrupt: Card detect and power cycle interrupts on */ 941 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 942 sockmask |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | 943 CB_SOCKET_MASK_POWER; 944 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 945 /* reset interrupt */ 946 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 947 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 948 } 949 950 /* 951 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 952 * struct pcmciabus_attach_args *paa) 953 * 954 * This function attaches 16-bit PCcard bus. 955 */ 956 STATIC void 957 pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 958 struct pcmciabus_attach_args *paa) 959 { 960 /* 961 * We need to do a few things here: 962 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 963 * setting the IRQ numbers to 0. 964 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 965 * routing of CSC interrupts (e.g. card removal) to PCI while in 966 * PCMCIA mode. We just leave this set all the time. 967 * 3) Enable card insertion/removal interrupts in case the chip also 968 * needs that while in PCMCIA mode. 969 * 4) Clear any pending CSC interrupt. 970 */ 971 Pcic_write(sc, PCIC_INTR, PCIC_INTR_ENABLE); 972 if (sc->sc_chipset == CB_TI113X) { 973 Pcic_write(sc, PCIC_CSC_INTR, 0); 974 } else { 975 Pcic_write(sc, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 976 Pcic_read(sc, PCIC_CSC); 977 } 978 979 /* initialize pcmcia bus attachment */ 980 paa->paa_busname = "pcmcia"; 981 paa->pct = &pccbb_pcmcia_funcs; 982 paa->pch = sc; 983 return; 984 } 985 986 /* 987 * int pccbbintr(arg) 988 * void *arg; 989 * This routine handles the interrupt from Yenta PCI-CardBus bridge 990 * itself. 991 */ 992 int 993 pccbbintr(void *arg) 994 { 995 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 996 struct cardslot_softc *csc; 997 uint32_t sockevent, sockstate; 998 bus_space_tag_t memt = sc->sc_base_memt; 999 bus_space_handle_t memh = sc->sc_base_memh; 1000 1001 if (!device_has_power(sc->sc_dev)) 1002 return 0; 1003 1004 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1005 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1006 Pcic_read(sc, PCIC_CSC); 1007 1008 if (sockevent != 0) { 1009 DPRINTF(("%s: enter sockevent %" PRIx32 "\n", 1010 __func__, sockevent)); 1011 } 1012 1013 /* XXX sockevent == CB_SOCKET_EVENT_CSTS|CB_SOCKET_EVENT_POWER 1014 * does occur in the wild. Check for a _POWER event before 1015 * possibly exiting because of an _CSTS event. 1016 */ 1017 if (sockevent & CB_SOCKET_EVENT_POWER) { 1018 DPRINTF(("Powercycling because of socket event\n")); 1019 /* XXX: Does not happen when attaching a 16-bit card */ 1020 mutex_enter(&sc->sc_pwr_mtx); 1021 sc->sc_pwrcycle++; 1022 cv_signal(&sc->sc_pwr_cv); 1023 mutex_exit(&sc->sc_pwr_mtx); 1024 } 1025 1026 /* Sometimes a change of CSTSCHG# accompanies the first 1027 * interrupt from an Atheros WLAN. That generates a 1028 * CB_SOCKET_EVENT_CSTS event on the bridge. The event 1029 * isn't interesting to pccbb(4), so we used to ignore the 1030 * interrupt. Now, let the child devices try to handle 1031 * the interrupt, instead. The Atheros NIC produces 1032 * interrupts more reliably, now: used to be that it would 1033 * only interrupt if the driver avoided powering down the 1034 * NIC's cardslot, and then the NIC would only work after 1035 * it was reset a second time. 1036 */ 1037 if (sockevent == 0 || 1038 (sockevent & ~(CB_SOCKET_EVENT_POWER|CB_SOCKET_EVENT_CD)) != 0) { 1039 /* This intr is not for me: it may be for my child devices. */ 1040 if (sc->sc_pil_intr_enable) { 1041 return pccbbintr_function(sc); 1042 } else { 1043 return 0; 1044 } 1045 } 1046 1047 if (sockevent & CB_SOCKET_EVENT_CD) { 1048 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1049 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1050 /* A card should be removed. */ 1051 if (sc->sc_flags & CBB_CARDEXIST) { 1052 DPRINTF(("%s: 0x%08x", 1053 device_xname(sc->sc_dev), sockevent)); 1054 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1055 sc->sc_flags &= ~CBB_CARDEXIST; 1056 if ((csc = sc->sc_csc) == NULL) 1057 ; 1058 else if (csc->sc_status & 1059 CARDSLOT_STATUS_CARD_16) { 1060 cardslot_event_throw(csc, 1061 CARDSLOT_EVENT_REMOVAL_16); 1062 } else if (csc->sc_status & 1063 CARDSLOT_STATUS_CARD_CB) { 1064 /* Cardbus intr removed */ 1065 cardslot_event_throw(csc, 1066 CARDSLOT_EVENT_REMOVAL_CB); 1067 } 1068 } else if (sc->sc_flags & CBB_INSERTING) { 1069 sc->sc_flags &= ~CBB_INSERTING; 1070 callout_stop(&sc->sc_insert_ch); 1071 } 1072 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1073 /* 1074 * The pccbbintr may called from powerdown hook when 1075 * the system resumed, to detect the card 1076 * insertion/removal during suspension. 1077 */ 1078 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1079 if (sc->sc_flags & CBB_INSERTING) { 1080 callout_stop(&sc->sc_insert_ch); 1081 } 1082 callout_schedule(&sc->sc_insert_ch, mstohz(200)); 1083 sc->sc_flags |= CBB_INSERTING; 1084 } 1085 } 1086 1087 return 1; 1088 } 1089 1090 /* 1091 * static int pccbbintr_function(struct pccbb_softc *sc) 1092 * 1093 * This function calls each interrupt handler registered at the 1094 * bridge. The interrupt handlers are called in registered order. 1095 */ 1096 static int 1097 pccbbintr_function(struct pccbb_softc *sc) 1098 { 1099 int retval = 0, val; 1100 struct pccbb_intrhand_list *pil; 1101 int s; 1102 1103 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1104 s = splraiseipl(pil->pil_icookie); 1105 val = (*pil->pil_func)(pil->pil_arg); 1106 splx(s); 1107 1108 retval = retval == 1 ? 1 : 1109 retval == 0 ? val : val != 0 ? val : retval; 1110 } 1111 1112 return retval; 1113 } 1114 1115 static void 1116 pci113x_insert(void *arg) 1117 { 1118 struct pccbb_softc *sc = arg; 1119 struct cardslot_softc *csc; 1120 uint32_t sockevent, sockstate; 1121 1122 if (!(sc->sc_flags & CBB_INSERTING)) { 1123 /* We add a card only under inserting state. */ 1124 return; 1125 } 1126 sc->sc_flags &= ~CBB_INSERTING; 1127 1128 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1129 CB_SOCKET_EVENT); 1130 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1131 CB_SOCKET_STAT); 1132 1133 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1134 #ifdef CBB_DEBUG 1135 DPRINTF(("%s: 0x%08x", device_xname(sc->sc_dev), sockevent)); 1136 #else 1137 __USE(sockevent); 1138 #endif 1139 1140 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1141 sc->sc_flags |= CBB_CARDEXIST; 1142 /* call pccard interrupt handler here */ 1143 if ((csc = sc->sc_csc) == NULL) 1144 ; 1145 else if (sockstate & CB_SOCKET_STAT_16BIT) { 1146 /* 16-bit card found */ 1147 cardslot_event_throw(csc, CARDSLOT_EVENT_INSERTION_16); 1148 } else if (sockstate & CB_SOCKET_STAT_CB) { 1149 /* cardbus card found */ 1150 cardslot_event_throw(csc, CARDSLOT_EVENT_INSERTION_CB); 1151 } else { 1152 /* who are you? */ 1153 } 1154 } else 1155 callout_schedule(&sc->sc_insert_ch, mstohz(100)); 1156 } 1157 1158 #define PCCBB_PCMCIA_OFFSET 0x800 1159 static uint8_t 1160 pccbb_pcmcia_read(struct pccbb_softc *sc, int reg) 1161 { 1162 bus_space_barrier(sc->sc_base_memt, sc->sc_base_memh, 1163 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1164 1165 return bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 1166 PCCBB_PCMCIA_OFFSET + reg); 1167 } 1168 1169 static void 1170 pccbb_pcmcia_write(struct pccbb_softc *sc, int reg, uint8_t val) 1171 { 1172 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 1173 PCCBB_PCMCIA_OFFSET + reg, val); 1174 1175 bus_space_barrier(sc->sc_base_memt, sc->sc_base_memh, 1176 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1177 } 1178 1179 /* 1180 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1181 */ 1182 STATIC int 1183 pccbb_ctrl(cardbus_chipset_tag_t ct, int command) 1184 { 1185 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1186 1187 switch (command) { 1188 case CARDBUS_CD: 1189 if (2 == pccbb_detect_card(sc)) { 1190 int retval = 0; 1191 int status = cb_detect_voltage(sc); 1192 if (PCCARD_VCC_5V & status) { 1193 retval |= CARDBUS_5V_CARD; 1194 } 1195 if (PCCARD_VCC_3V & status) { 1196 retval |= CARDBUS_3V_CARD; 1197 } 1198 if (PCCARD_VCC_XV & status) { 1199 retval |= CARDBUS_XV_CARD; 1200 } 1201 if (PCCARD_VCC_YV & status) { 1202 retval |= CARDBUS_YV_CARD; 1203 } 1204 return retval; 1205 } else { 1206 return 0; 1207 } 1208 case CARDBUS_RESET: 1209 return cb_reset(sc); 1210 case CARDBUS_IO_ENABLE: /* fallthrough */ 1211 case CARDBUS_IO_DISABLE: /* fallthrough */ 1212 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1213 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1214 case CARDBUS_BM_ENABLE: /* fallthrough */ 1215 case CARDBUS_BM_DISABLE: /* fallthrough */ 1216 /* XXX: I think we don't need to call this function below. */ 1217 return pccbb_cardenable(sc, command); 1218 } 1219 1220 return 0; 1221 } 1222 1223 STATIC int 1224 pccbb_power_ct(cardbus_chipset_tag_t ct, int command) 1225 { 1226 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1227 1228 return pccbb_power(sc, command); 1229 } 1230 1231 /* 1232 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1233 * This function returns true when it succeeds and returns false when 1234 * it fails. 1235 */ 1236 STATIC int 1237 pccbb_power(struct pccbb_softc *sc, int command) 1238 { 1239 uint32_t status, osock_ctrl, sock_ctrl, reg_ctrl; 1240 bus_space_tag_t memt = sc->sc_base_memt; 1241 bus_space_handle_t memh = sc->sc_base_memh; 1242 int on = 0, pwrcycle, times; 1243 struct timeval before, after, diff; 1244 1245 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1246 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1247 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1248 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1249 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1250 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1251 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1252 "UNKNOWN", 1253 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1254 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1255 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1256 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1257 "UNKNOWN", command)); 1258 1259 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1260 osock_ctrl = sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1261 1262 switch (command & CARDBUS_VCCMASK) { 1263 case CARDBUS_VCC_UC: 1264 break; 1265 case CARDBUS_VCC_5V: 1266 on++; 1267 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1268 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1269 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1270 } else { 1271 aprint_error_dev(sc->sc_dev, 1272 "BAD voltage request: no 5 V card\n"); 1273 return 0; 1274 } 1275 break; 1276 case CARDBUS_VCC_3V: 1277 on++; 1278 if (CB_SOCKET_STAT_3VCARD & status) { 1279 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1280 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1281 } else { 1282 aprint_error_dev(sc->sc_dev, 1283 "BAD voltage request: no 3.3 V card\n"); 1284 return 0; 1285 } 1286 break; 1287 case CARDBUS_VCC_0V: 1288 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1289 break; 1290 default: 1291 return 0; /* power NEVER changed */ 1292 } 1293 1294 switch (command & CARDBUS_VPPMASK) { 1295 case CARDBUS_VPP_UC: 1296 break; 1297 case CARDBUS_VPP_0V: 1298 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1299 break; 1300 case CARDBUS_VPP_VCC: 1301 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1302 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1303 break; 1304 case CARDBUS_VPP_12V: 1305 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1306 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1307 break; 1308 } 1309 aprint_debug_dev(sc->sc_dev, "osock_ctrl %#" PRIx32 1310 " sock_ctrl %#" PRIx32 "\n", osock_ctrl, sock_ctrl); 1311 1312 microtime(&before); 1313 mutex_enter(&sc->sc_pwr_mtx); 1314 pwrcycle = sc->sc_pwrcycle; 1315 1316 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1317 1318 /* 1319 * Wait as long as 200ms for a power-cycle interrupt. If 1320 * interrupts are enabled, but the socket has already 1321 * changed to the desired status, keep waiting for the 1322 * interrupt. "Consuming" the interrupt in this way keeps 1323 * the interrupt from prematurely waking some subsequent 1324 * pccbb_power call. 1325 * 1326 * XXX Not every bridge interrupts on the ->OFF transition. 1327 * XXX That's ok, we will time-out after 200ms. 1328 * 1329 * XXX The power cycle event will never happen when attaching 1330 * XXX a 16-bit card. That's ok, we will time-out after 1331 * XXX 200ms. 1332 */ 1333 for (times = 5; --times >= 0; ) { 1334 if (cold) 1335 DELAY(40 * 1000); 1336 else { 1337 (void)cv_timedwait(&sc->sc_pwr_cv, &sc->sc_pwr_mtx, 1338 mstohz(40)); 1339 if (pwrcycle == sc->sc_pwrcycle) 1340 continue; 1341 } 1342 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1343 if ((status & CB_SOCKET_STAT_PWRCYCLE) != 0 && on) 1344 break; 1345 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0 && !on) 1346 break; 1347 } 1348 mutex_exit(&sc->sc_pwr_mtx); 1349 microtime(&after); 1350 timersub(&after, &before, &diff); 1351 aprint_debug_dev(sc->sc_dev, "wait took%s %lld.%06lds\n", 1352 (on && times < 0) ? " too long" : "", (long long)diff.tv_sec, 1353 (long)diff.tv_usec); 1354 1355 /* 1356 * Ok, wait a bit longer for things to settle. 1357 */ 1358 if (on && sc->sc_chipset == CB_TOPIC95B) 1359 delay_ms(100, sc); 1360 1361 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1362 1363 if (on && sc->sc_chipset != CB_TOPIC95B) { 1364 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1365 aprint_error_dev(sc->sc_dev, "power on failed?\n"); 1366 } 1367 1368 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1369 aprint_error_dev(sc->sc_dev, 1370 "bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1371 sock_ctrl, status); 1372 aprint_error_dev(sc->sc_dev, "disabling socket\n"); 1373 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1374 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1375 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1376 status &= ~CB_SOCKET_STAT_BADVCC; 1377 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, status); 1378 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1379 CB_SOCKET_STAT)); 1380 return 0; 1381 } 1382 1383 if (sc->sc_chipset == CB_TOPIC97) { 1384 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1385 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1386 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1387 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1388 else 1389 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1390 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1391 } 1392 1393 return 1; /* power changed correctly */ 1394 } 1395 1396 /* 1397 * static int pccbb_detect_card(struct pccbb_softc *sc) 1398 * return value: 0 if no card exists. 1399 * 1 if 16-bit card exists. 1400 * 2 if cardbus card exists. 1401 */ 1402 static int 1403 pccbb_detect_card(struct pccbb_softc *sc) 1404 { 1405 bus_space_handle_t base_memh = sc->sc_base_memh; 1406 bus_space_tag_t base_memt = sc->sc_base_memt; 1407 uint32_t sockstat = 1408 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1409 int retval = 0; 1410 1411 /* CD1 and CD2 asserted */ 1412 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1413 /* card must be present */ 1414 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1415 /* NOTACARD DEASSERTED */ 1416 if (CB_SOCKET_STAT_CB & sockstat) { 1417 /* CardBus mode */ 1418 retval = 2; 1419 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1420 /* 16-bit mode */ 1421 retval = 1; 1422 } 1423 } 1424 } 1425 return retval; 1426 } 1427 1428 /* 1429 * STATIC int cb_reset(struct pccbb_softc *sc) 1430 * This function resets CardBus card. 1431 */ 1432 STATIC int 1433 cb_reset(struct pccbb_softc *sc) 1434 { 1435 /* 1436 * Reset Assert at least 20 ms 1437 * Some machines request longer duration. 1438 */ 1439 int reset_duration = 1440 (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1441 uint32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1442 PCI_BRIDGE_CONTROL_REG); 1443 aprint_debug("%s: enter bcr %" PRIx32 "\n", __func__, bcr); 1444 1445 /* Reset bit Assert (bit 6 at 0x3E) */ 1446 bcr |= PCI_BRIDGE_CONTROL_SECBR; 1447 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1448 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1449 delay_ms(reset_duration, sc); 1450 1451 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1452 /* Reset bit Deassert (bit 6 at 0x3E) */ 1453 bcr &= ~(PCI_BRIDGE_CONTROL_SECBR); 1454 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, 1455 bcr); 1456 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1457 delay_ms(reset_duration, sc); 1458 aprint_debug("%s: end of delay\n", __func__); 1459 } 1460 /* No card found on the slot. Keep Reset. */ 1461 return 1; 1462 } 1463 1464 /* 1465 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1466 * This function detect card Voltage. 1467 */ 1468 STATIC int 1469 cb_detect_voltage(struct pccbb_softc *sc) 1470 { 1471 uint32_t psr; /* socket present-state reg */ 1472 bus_space_tag_t iot = sc->sc_base_memt; 1473 bus_space_handle_t ioh = sc->sc_base_memh; 1474 int vol = PCCARD_VCC_UKN; /* set 0 */ 1475 1476 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1477 1478 if (0x400u & psr) 1479 vol |= PCCARD_VCC_5V; 1480 1481 if (0x800u & psr) 1482 vol |= PCCARD_VCC_3V; 1483 1484 return vol; 1485 } 1486 1487 STATIC int 1488 cbbprint(void *aux, const char *pcic) 1489 { 1490 #if 0 1491 struct cbslot_attach_args *cba = aux; 1492 1493 if (cba->cba_slot >= 0) 1494 aprint_normal(" slot %d", cba->cba_slot); 1495 #endif 1496 return UNCONF; 1497 } 1498 1499 /* 1500 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1501 * This function enables and disables the card 1502 */ 1503 STATIC int 1504 pccbb_cardenable(struct pccbb_softc *sc, int function) 1505 { 1506 uint32_t command = 1507 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1508 1509 DPRINTF(("pccbb_cardenable:")); 1510 switch (function) { 1511 case CARDBUS_IO_ENABLE: 1512 command |= PCI_COMMAND_IO_ENABLE; 1513 break; 1514 case CARDBUS_IO_DISABLE: 1515 command &= ~PCI_COMMAND_IO_ENABLE; 1516 break; 1517 case CARDBUS_MEM_ENABLE: 1518 command |= PCI_COMMAND_MEM_ENABLE; 1519 break; 1520 case CARDBUS_MEM_DISABLE: 1521 command &= ~PCI_COMMAND_MEM_ENABLE; 1522 break; 1523 case CARDBUS_BM_ENABLE: 1524 command |= PCI_COMMAND_MASTER_ENABLE; 1525 break; 1526 case CARDBUS_BM_DISABLE: 1527 command &= ~PCI_COMMAND_MASTER_ENABLE; 1528 break; 1529 default: 1530 return 0; 1531 } 1532 1533 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1534 DPRINTF((" command reg 0x%x\n", command)); 1535 return 1; 1536 } 1537 1538 #if !rbus 1539 static int 1540 pccbb_io_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1541 { 1542 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1543 int basereg; 1544 int limitreg; 1545 1546 if ((win < 0) || (win > 2)) { 1547 #if defined DIAGNOSTIC 1548 printf("cardbus_io_open: window out of range %d\n", win); 1549 #endif 1550 return 0; 1551 } 1552 1553 basereg = win * 8 + PCI_CB_IOBASE0; 1554 limitreg = win * 8 + PCI_CB_IOLIMIT0; 1555 1556 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1557 start, basereg, end, limitreg)); 1558 1559 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1560 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1561 return 1; 1562 } 1563 1564 /* 1565 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1566 */ 1567 static int 1568 pccbb_io_close(cardbus_chipset_tag_t ct, int win) 1569 { 1570 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1571 int basereg; 1572 int limitreg; 1573 1574 if ((win < 0) || (win > 2)) { 1575 #if defined DIAGNOSTIC 1576 printf("cardbus_io_close: window out of range %d\n", win); 1577 #endif 1578 return 0; 1579 } 1580 1581 basereg = win * 8 + PCI_CB_IOBASE0; 1582 limitreg = win * 8 + PCI_CB_IOLIMIT0; 1583 1584 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1585 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1586 return 1; 1587 } 1588 1589 static int 1590 pccbb_mem_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1591 { 1592 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1593 int basereg; 1594 int limitreg; 1595 1596 if ((win < 0) || (win > 2)) { 1597 #if defined DIAGNOSTIC 1598 printf("cardbus_mem_open: window out of range %d\n", win); 1599 #endif 1600 return 0; 1601 } 1602 1603 basereg = win * 8 + PCI_CB_MEMBASE0; 1604 limitreg = win * 8 + PCI_CB_MEMLIMIT0; 1605 1606 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1607 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1608 return 1; 1609 } 1610 1611 static int 1612 pccbb_mem_close(cardbus_chipset_tag_t ct, int win) 1613 { 1614 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1615 int basereg; 1616 int limitreg; 1617 1618 if ((win < 0) || (win > 2)) { 1619 #if defined DIAGNOSTIC 1620 printf("cardbus_mem_close: window out of range %d\n", win); 1621 #endif 1622 return 0; 1623 } 1624 1625 basereg = win * 8 + PCI_CB_MEMBASE0; 1626 limitreg = win * 8 + PCI_CB_MEMLIMIT0; 1627 1628 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1629 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1630 return 1; 1631 } 1632 #endif 1633 1634 /* 1635 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1636 * int level, 1637 * int (* func)(void *), 1638 * void *arg) 1639 * 1640 * This function registers an interrupt handler at the bridge, in 1641 * order not to call the interrupt handlers of child devices when 1642 * a card-deletion interrupt occurs. 1643 * 1644 * The argument level is not used. 1645 */ 1646 static void * 1647 pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, int level, 1648 int (*func)(void *), void *arg) 1649 { 1650 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1651 1652 return pccbb_intr_establish(sc, level, func, arg); 1653 } 1654 1655 1656 /* 1657 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1658 * void *ih) 1659 * 1660 * This function removes an interrupt handler pointed by ih. 1661 */ 1662 static void 1663 pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih) 1664 { 1665 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1666 1667 pccbb_intr_disestablish(sc, ih); 1668 } 1669 1670 1671 void 1672 pccbb_intr_route(struct pccbb_softc *sc) 1673 { 1674 pcireg_t bcr, cbctrl; 1675 1676 /* initialize bridge intr routing */ 1677 bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1678 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; 1679 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1680 1681 switch (sc->sc_chipset) { 1682 case CB_TI113X: 1683 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1684 /* functional intr enabled */ 1685 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1686 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1687 break; 1688 default: 1689 break; 1690 } 1691 } 1692 1693 /* 1694 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1695 * int irq, 1696 * int level, 1697 * int (* func)(void *), 1698 * void *arg) 1699 * 1700 * This function registers an interrupt handler at the bridge, in 1701 * order not to call the interrupt handlers of child devices when 1702 * a card-deletion interrupt occurs. 1703 * 1704 */ 1705 static void * 1706 pccbb_intr_establish(struct pccbb_softc *sc, int level, 1707 int (*func)(void *), void *arg) 1708 { 1709 struct pccbb_intrhand_list *pil, *newpil; 1710 1711 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1712 1713 if (LIST_EMPTY(&sc->sc_pil)) 1714 pccbb_intr_route(sc); 1715 1716 /* 1717 * Allocate a room for interrupt handler structure. 1718 */ 1719 if (NULL == (newpil = 1720 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1721 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1722 return NULL; 1723 } 1724 1725 newpil->pil_func = func; 1726 newpil->pil_arg = arg; 1727 newpil->pil_icookie = makeiplcookie(level); 1728 1729 if (LIST_EMPTY(&sc->sc_pil)) { 1730 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1731 } else { 1732 for (pil = LIST_FIRST(&sc->sc_pil); 1733 LIST_NEXT(pil, pil_next) != NULL; 1734 pil = LIST_NEXT(pil, pil_next)); 1735 LIST_INSERT_AFTER(pil, newpil, pil_next); 1736 } 1737 1738 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1739 LIST_FIRST(&sc->sc_pil))); 1740 1741 return newpil; 1742 } 1743 1744 /* 1745 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1746 * void *ih) 1747 * 1748 * This function removes an interrupt handler pointed by ih. ih 1749 * should be the value returned by cardbus_intr_establish() or 1750 * NULL. 1751 * 1752 * When ih is NULL, this function will do nothing. 1753 */ 1754 static void 1755 pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih) 1756 { 1757 struct pccbb_intrhand_list *pil; 1758 pcireg_t reg; 1759 1760 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1761 LIST_FIRST(&sc->sc_pil))); 1762 1763 if (ih == NULL) { 1764 /* intr handler is not set */ 1765 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1766 return; 1767 } 1768 1769 #ifdef DIAGNOSTIC 1770 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1771 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1772 if (pil == ih) { 1773 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1774 break; 1775 } 1776 } 1777 if (pil == NULL) { 1778 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1779 device_xname(sc->sc_dev), ih); 1780 } 1781 #endif 1782 1783 pil = (struct pccbb_intrhand_list *)ih; 1784 LIST_REMOVE(pil, pil_next); 1785 free(pil, M_DEVBUF); 1786 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1787 1788 if (LIST_EMPTY(&sc->sc_pil)) { 1789 /* No interrupt handlers */ 1790 1791 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1792 1793 /* stop routing PCI intr */ 1794 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 1795 PCI_BRIDGE_CONTROL_REG); 1796 reg |= CB_BCR_INTR_IREQ_ENABLE; 1797 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, 1798 reg); 1799 1800 switch (sc->sc_chipset) { 1801 case CB_TI113X: 1802 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1803 /* functional intr disabled */ 1804 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1805 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1806 break; 1807 default: 1808 break; 1809 } 1810 } 1811 } 1812 1813 #if defined SHOW_REGS 1814 static void 1815 cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, 1816 bus_space_handle_t memh) 1817 { 1818 int i; 1819 printf("PCI config regs:"); 1820 for (i = 0; i < 0x50; i += 4) { 1821 if (i % 16 == 0) 1822 printf("\n 0x%02x:", i); 1823 printf(" %08x", pci_conf_read(pc, tag, i)); 1824 } 1825 for (i = 0x80; i < 0xb0; i += 4) { 1826 if (i % 16 == 0) 1827 printf("\n 0x%02x:", i); 1828 printf(" %08x", pci_conf_read(pc, tag, i)); 1829 } 1830 1831 if (memh == 0) { 1832 printf("\n"); 1833 return; 1834 } 1835 1836 printf("\nsocket regs:"); 1837 for (i = 0; i <= 0x10; i += 0x04) 1838 printf(" %08x", bus_space_read_4(memt, memh, i)); 1839 printf("\nExCA regs:"); 1840 for (i = 0; i < 0x08; ++i) 1841 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1842 printf("\n"); 1843 return; 1844 } 1845 #endif 1846 1847 /* 1848 * static pcitag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1849 * int busno, int function) 1850 * This is the function to make a tag to access config space of 1851 * a CardBus Card. It works same as pci_conf_read. 1852 */ 1853 static pcitag_t 1854 pccbb_make_tag(cardbus_chipset_tag_t cc, int busno, int function) 1855 { 1856 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1857 1858 return pci_make_tag(sc->sc_pc, busno, 0, function); 1859 } 1860 1861 /* 1862 * pccbb_conf_read 1863 * 1864 * This is the function to read the config space of a CardBus card. 1865 * It works the same as pci_conf_read(9). 1866 */ 1867 static pcireg_t 1868 pccbb_conf_read(cardbus_chipset_tag_t cc, pcitag_t tag, int offset) 1869 { 1870 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1871 pcitag_t brtag = sc->sc_tag; 1872 pcireg_t reg; 1873 1874 /* 1875 * clear cardbus master abort status; it is OK to write without 1876 * reading before because all bits are r/o or w1tc 1877 */ 1878 pci_conf_write(sc->sc_pc, brtag, PCI_CBB_SECSTATUS, 1879 CBB_SECSTATUS_CBMABORT); 1880 reg = pci_conf_read(sc->sc_pc, tag, offset); 1881 /* check cardbus master abort status */ 1882 if (pci_conf_read(sc->sc_pc, brtag, PCI_CBB_SECSTATUS) 1883 & CBB_SECSTATUS_CBMABORT) 1884 return 0xffffffff; 1885 return reg; 1886 } 1887 1888 /* 1889 * pccbb_conf_write 1890 * 1891 * This is the function to write the config space of a CardBus 1892 * card. It works the same as pci_conf_write(9). 1893 */ 1894 static void 1895 pccbb_conf_write(cardbus_chipset_tag_t cc, pcitag_t tag, int reg, pcireg_t val) 1896 { 1897 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1898 1899 pci_conf_write(sc->sc_pc, tag, reg, val); 1900 } 1901 1902 #if 0 1903 STATIC int 1904 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1905 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1906 int speed, int flags, 1907 bus_space_handle_t * iohp) 1908 #endif 1909 /* 1910 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1911 * bus_addr_t start, bus_size_t size, 1912 * bus_size_t align, 1913 * struct pcmcia_io_handle *pcihp 1914 * 1915 * This function only allocates I/O region for pccard. This function 1916 * never maps the allocated region to pccard I/O area. 1917 * 1918 * XXX: The interface of this function is not very good, I believe. 1919 */ 1920 STATIC int 1921 pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 1922 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 1923 { 1924 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 1925 bus_addr_t ioaddr; 1926 int flags = 0; 1927 bus_space_tag_t iot; 1928 bus_space_handle_t ioh; 1929 bus_addr_t mask; 1930 #if rbus 1931 rbus_tag_t rb; 1932 #endif 1933 if (align == 0) 1934 align = size; /* XXX: funny??? */ 1935 1936 if (start != 0) { 1937 /* XXX: assume all card decode lower 10 bits by its hardware */ 1938 mask = 0x3ff; 1939 /* enforce to use only masked address */ 1940 start &= mask; 1941 } else { 1942 /* 1943 * calculate mask: 1944 * 1. get the most significant bit of size (call it msb). 1945 * 2. compare msb with the value of size. 1946 * 3. if size is larger, shift msb left once. 1947 * 4. obtain mask value to decrement msb. 1948 */ 1949 bus_size_t size_tmp = size; 1950 int shifts = 0; 1951 1952 mask = 1; 1953 while (size_tmp) { 1954 ++shifts; 1955 size_tmp >>= 1; 1956 } 1957 mask = (1 << shifts); 1958 if (mask < size) { 1959 mask <<= 1; 1960 } 1961 --mask; 1962 } 1963 1964 /* 1965 * Allocate some arbitrary I/O space. 1966 */ 1967 1968 iot = sc->sc_iot; 1969 1970 #if rbus 1971 rb = sc->sc_rbus_iot; 1972 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 1973 return 1; 1974 } 1975 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1976 (u_long) ioaddr, (u_long) size)); 1977 #else 1978 if (start) { 1979 ioaddr = start; 1980 if (bus_space_map(iot, start, size, 0, &ioh)) { 1981 return 1; 1982 } 1983 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 1984 (u_long) ioaddr, (u_long) size)); 1985 } else { 1986 flags |= PCMCIA_IO_ALLOCATED; 1987 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 1988 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 1989 size, align, 0, 0, &ioaddr, &ioh)) { 1990 /* No room be able to be get. */ 1991 return 1; 1992 } 1993 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1994 (u_long) ioaddr, (u_long) size)); 1995 } 1996 #endif 1997 1998 pcihp->iot = iot; 1999 pcihp->ioh = ioh; 2000 pcihp->addr = ioaddr; 2001 pcihp->size = size; 2002 pcihp->flags = flags; 2003 2004 return 0; 2005 } 2006 2007 /* 2008 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2009 * struct pcmcia_io_handle *pcihp) 2010 * 2011 * This function only frees I/O region for pccard. 2012 * 2013 * XXX: The interface of this function is not very good, I believe. 2014 */ 2015 void 2016 pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2017 struct pcmcia_io_handle *pcihp) 2018 { 2019 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2020 #if !rbus 2021 bus_space_tag_t iot = pcihp->iot; 2022 #endif 2023 bus_space_handle_t ioh = pcihp->ioh; 2024 bus_size_t size = pcihp->size; 2025 2026 #if rbus 2027 rbus_tag_t rb = sc->sc_rbus_iot; 2028 2029 rbus_space_free(rb, ioh, size, NULL); 2030 #else 2031 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2032 bus_space_free(iot, ioh, size); 2033 else 2034 bus_space_unmap(iot, ioh, size); 2035 #endif 2036 } 2037 2038 /* 2039 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2040 * bus_addr_t offset, bus_size_t size, 2041 * struct pcmcia_io_handle *pcihp, 2042 * int *windowp) 2043 * 2044 * This function maps the allocated I/O region to pccard. This function 2045 * never allocates any I/O region for pccard I/O area. I don't 2046 * understand why the original authors of pcmciabus separated alloc and 2047 * map. I believe the two must be unite. 2048 * 2049 * XXX: no wait timing control? 2050 */ 2051 int 2052 pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 2053 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 2054 { 2055 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2056 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2057 bus_addr_t ioaddr = pcihp->addr + offset; 2058 int i, win; 2059 #if defined CBB_DEBUG 2060 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2061 #endif 2062 2063 /* Sanity check I/O handle. */ 2064 2065 if (!bus_space_is_equal(sc->sc_iot, pcihp->iot)) 2066 panic("pccbb_pcmcia_io_map iot is bogus"); 2067 2068 /* XXX Sanity check offset/size. */ 2069 2070 win = -1; 2071 for (i = 0; i < PCIC_IO_WINS; i++) { 2072 if ((ph->ioalloc & (1 << i)) == 0) { 2073 win = i; 2074 ph->ioalloc |= (1 << i); 2075 break; 2076 } 2077 } 2078 2079 if (win == -1) 2080 return 1; 2081 2082 *windowp = win; 2083 2084 /* XXX this is pretty gross */ 2085 2086 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2087 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2088 2089 /* XXX wtf is this doing here? */ 2090 2091 #if 0 2092 printf(" port 0x%lx", (u_long) ioaddr); 2093 if (size > 1) 2094 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2095 #endif 2096 2097 ph->io[win].addr = ioaddr; 2098 ph->io[win].size = size; 2099 ph->io[win].width = width; 2100 2101 /* actual dirty register-value changing in the function below. */ 2102 pccbb_pcmcia_do_io_map(sc, win); 2103 2104 return 0; 2105 } 2106 2107 /* 2108 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2109 * 2110 * This function changes register-value to map I/O region for pccard. 2111 */ 2112 static void 2113 pccbb_pcmcia_do_io_map(struct pccbb_softc *sc, int win) 2114 { 2115 static uint8_t pcic_iowidth[3] = { 2116 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2117 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2118 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2119 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2120 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2121 }; 2122 2123 #define PCIC_SIA_START_LOW 0 2124 #define PCIC_SIA_START_HIGH 1 2125 #define PCIC_SIA_STOP_LOW 2 2126 #define PCIC_SIA_STOP_HIGH 3 2127 2128 int regbase_win = 0x8 + win * 0x04; 2129 uint8_t ioctl, enable; 2130 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2131 2132 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2133 "width %d\n", win, (unsigned long)ph->io[win].addr, 2134 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2135 2136 Pcic_write(sc, regbase_win + PCIC_SIA_START_LOW, 2137 ph->io[win].addr & 0xff); 2138 Pcic_write(sc, regbase_win + PCIC_SIA_START_HIGH, 2139 (ph->io[win].addr >> 8) & 0xff); 2140 2141 Pcic_write(sc, regbase_win + PCIC_SIA_STOP_LOW, 2142 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2143 Pcic_write(sc, regbase_win + PCIC_SIA_STOP_HIGH, 2144 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2145 2146 ioctl = Pcic_read(sc, PCIC_IOCTL); 2147 enable = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2148 switch (win) { 2149 case 0: 2150 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2151 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2152 PCIC_IOCTL_IO0_DATASIZE_MASK); 2153 ioctl |= pcic_iowidth[ph->io[win].width]; 2154 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2155 break; 2156 case 1: 2157 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2158 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2159 PCIC_IOCTL_IO1_DATASIZE_MASK); 2160 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2161 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2162 break; 2163 } 2164 Pcic_write(sc, PCIC_IOCTL, ioctl); 2165 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, enable); 2166 #if defined(CBB_DEBUG) 2167 { 2168 uint8_t start_low = 2169 Pcic_read(sc, regbase_win + PCIC_SIA_START_LOW); 2170 uint8_t start_high = 2171 Pcic_read(sc, regbase_win + PCIC_SIA_START_HIGH); 2172 uint8_t stop_low = 2173 Pcic_read(sc, regbase_win + PCIC_SIA_STOP_LOW); 2174 uint8_t stop_high = 2175 Pcic_read(sc, regbase_win + PCIC_SIA_STOP_HIGH); 2176 printf("pccbb_pcmcia_do_io_map start %02x %02x, " 2177 "stop %02x %02x, ioctl %02x enable %02x\n", 2178 start_low, start_high, stop_low, stop_high, ioctl, enable); 2179 } 2180 #endif 2181 } 2182 2183 /* 2184 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2185 * 2186 * This function unmaps I/O region. No return value. 2187 */ 2188 STATIC void 2189 pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win) 2190 { 2191 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2192 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2193 int reg; 2194 2195 if (win >= PCIC_IO_WINS || win < 0) 2196 panic("pccbb_pcmcia_io_unmap: window out of range"); 2197 2198 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2199 switch (win) { 2200 case 0: 2201 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2202 break; 2203 case 1: 2204 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2205 break; 2206 } 2207 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2208 2209 ph->ioalloc &= ~(1 << win); 2210 } 2211 2212 static int 2213 pccbb_pcmcia_wait_ready(struct pccbb_softc *sc) 2214 { 2215 uint8_t stat; 2216 int i; 2217 2218 /* wait an initial 10ms for quick cards */ 2219 stat = Pcic_read(sc, PCIC_IF_STATUS); 2220 if (stat & PCIC_IF_STATUS_READY) 2221 return 0; 2222 pccbb_pcmcia_delay(sc, 10, "pccwr0"); 2223 for (i = 0; i < 50; i++) { 2224 stat = Pcic_read(sc, PCIC_IF_STATUS); 2225 if (stat & PCIC_IF_STATUS_READY) 2226 return 0; 2227 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2228 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2229 return ENXIO; 2230 /* wait .1s (100ms) each iteration now */ 2231 pccbb_pcmcia_delay(sc, 100, "pccwr1"); 2232 } 2233 2234 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", 2235 stat); 2236 return EWOULDBLOCK; 2237 } 2238 2239 /* 2240 * Perform long (msec order) delay. timo is in milliseconds. 2241 */ 2242 static void 2243 pccbb_pcmcia_delay(struct pccbb_softc *sc, int timo, const char *wmesg) 2244 { 2245 #ifdef DIAGNOSTIC 2246 if (timo <= 0) 2247 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2248 if (!curlwp) 2249 panic("pccbb_pcmcia_delay: called in interrupt context"); 2250 #endif 2251 DPRINTF(("pccbb_pcmcia_delay: \"%s\", sleep %d ms\n", wmesg, timo)); 2252 kpause(wmesg, false, uimax(mstohz(timo), 1), NULL); 2253 } 2254 2255 /* 2256 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2257 * 2258 * This function enables the card. All information is stored in 2259 * the first argument, pcmcia_chipset_handle_t. 2260 */ 2261 STATIC void 2262 pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2263 { 2264 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2265 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2266 pcireg_t spsr; 2267 int voltage; 2268 int win; 2269 uint8_t power, intr; 2270 #ifdef DIAGNOSTIC 2271 int reg; 2272 #endif 2273 2274 /* this bit is mostly stolen from pcic_attach_card */ 2275 2276 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2277 2278 /* get card Vcc info */ 2279 spsr = 2280 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2281 CB_SOCKET_STAT); 2282 if (spsr & CB_SOCKET_STAT_5VCARD) { 2283 DPRINTF(("5V card\n")); 2284 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2285 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2286 DPRINTF(("3V card\n")); 2287 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2288 } else { 2289 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 2290 return; 2291 } 2292 2293 /* disable interrupts; assert RESET */ 2294 intr = Pcic_read(sc, PCIC_INTR); 2295 intr &= PCIC_INTR_ENABLE; 2296 Pcic_write(sc, PCIC_INTR, intr); 2297 2298 /* zero out the address windows */ 2299 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, 0); 2300 2301 /* power down the socket to reset it, clear the card reset pin */ 2302 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2303 2304 /* power off; assert output enable bit */ 2305 power = PCIC_PWRCTL_OE; 2306 Pcic_write(sc, PCIC_PWRCTL, power); 2307 2308 /* power up the socket */ 2309 if (pccbb_power(sc, voltage) == 0) 2310 return; 2311 2312 /* 2313 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2314 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2315 * RESET Width (Th (Hi-z RESET)) = 1ms 2316 * RESET Width (Tw (RESET)) = 10us 2317 * 2318 * some machines require some more time to be settled 2319 * for example old toshiba topic bridges! 2320 * (100ms is added here). 2321 */ 2322 pccbb_pcmcia_delay(sc, 200 + 1, "pccen1"); 2323 2324 /* negate RESET */ 2325 intr |= PCIC_INTR_RESET; 2326 Pcic_write(sc, PCIC_INTR, intr); 2327 2328 /* 2329 * RESET Setup Time (Tsu (RESET)) = 20ms 2330 */ 2331 pccbb_pcmcia_delay(sc, 20, "pccen2"); 2332 2333 #ifdef DIAGNOSTIC 2334 reg = Pcic_read(sc, PCIC_IF_STATUS); 2335 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2336 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", 2337 reg); 2338 #endif 2339 2340 /* wait for the chip to finish initializing */ 2341 if (pccbb_pcmcia_wait_ready(sc)) { 2342 #ifdef DIAGNOSTIC 2343 printf("pccbb_pcmcia_socket_enable: never became ready\n"); 2344 #endif 2345 /* XXX return a failure status?? */ 2346 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2347 Pcic_write(sc, PCIC_PWRCTL, 0); 2348 return; 2349 } 2350 2351 /* reinstall all the memory and io mappings */ 2352 for (win = 0; win < PCIC_MEM_WINS; ++win) 2353 if (ph->memalloc & (1 << win)) 2354 pccbb_pcmcia_do_mem_map(sc, win); 2355 for (win = 0; win < PCIC_IO_WINS; ++win) 2356 if (ph->ioalloc & (1 << win)) 2357 pccbb_pcmcia_do_io_map(sc, win); 2358 } 2359 2360 /* 2361 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2362 * 2363 * This function disables the card. All information is stored in 2364 * the first argument, pcmcia_chipset_handle_t. 2365 */ 2366 STATIC void 2367 pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch) 2368 { 2369 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2370 uint8_t intr; 2371 2372 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2373 2374 /* disable interrupts; assert RESET */ 2375 intr = Pcic_read(sc, PCIC_INTR); 2376 intr &= PCIC_INTR_ENABLE; 2377 Pcic_write(sc, PCIC_INTR, intr); 2378 2379 /* zero out the address windows */ 2380 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, 0); 2381 2382 /* power down the socket to reset it, clear the card reset pin */ 2383 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2384 2385 /* disable socket: negate output enable bit and power off */ 2386 Pcic_write(sc, PCIC_PWRCTL, 0); 2387 2388 /* 2389 * Vcc Falling Time (Tpf) = 300ms 2390 */ 2391 pccbb_pcmcia_delay(sc, 300, "pccwr1"); 2392 } 2393 2394 STATIC void 2395 pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t pch, int type) 2396 { 2397 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2398 uint8_t intr; 2399 2400 /* set the card type */ 2401 2402 intr = Pcic_read(sc, PCIC_INTR); 2403 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2404 if (type == PCMCIA_IFTYPE_IO) 2405 intr |= PCIC_INTR_CARDTYPE_IO; 2406 else 2407 intr |= PCIC_INTR_CARDTYPE_MEM; 2408 Pcic_write(sc, PCIC_INTR, intr); 2409 2410 DPRINTF(("%s: pccbb_pcmcia_socket_settype type %s %02x\n", 2411 device_xname(sc->sc_dev), 2412 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2413 } 2414 2415 /* 2416 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2417 * 2418 * This function detects whether a card is in the slot or not. 2419 * If a card is inserted, return 1. Otherwise, return 0. 2420 */ 2421 STATIC int 2422 pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch) 2423 { 2424 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2425 2426 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2427 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2428 } 2429 2430 #if 0 2431 STATIC int 2432 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2433 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2434 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2435 #endif 2436 /* 2437 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2438 * bus_size_t size, 2439 * struct pcmcia_mem_handle *pcmhp) 2440 * 2441 * This function only allocates memory region for pccard. This 2442 * function never maps the allocated region to pccard memory area. 2443 * 2444 * XXX: Why the argument of start address is not in? 2445 */ 2446 STATIC int 2447 pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 2448 struct pcmcia_mem_handle *pcmhp) 2449 { 2450 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2451 bus_space_handle_t memh; 2452 bus_addr_t addr; 2453 bus_size_t sizepg; 2454 #if rbus 2455 rbus_tag_t rb; 2456 #endif 2457 2458 /* Check that the card is still there. */ 2459 if ((Pcic_read(sc, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2460 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2461 return 1; 2462 2463 /* out of sc->memh, allocate as many pages as necessary */ 2464 2465 /* convert size to PCIC pages */ 2466 /* 2467 * This is not enough; when the requested region is on the page 2468 * boundaries, this may calculate wrong result. 2469 */ 2470 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2471 #if 0 2472 if (sizepg > PCIC_MAX_MEM_PAGES) 2473 return 1; 2474 #endif 2475 2476 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) 2477 return 1; 2478 2479 addr = 0; /* XXX gcc -Wuninitialized */ 2480 2481 #if rbus 2482 rb = sc->sc_rbus_memt; 2483 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2484 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2485 &addr, &memh)) { 2486 return 1; 2487 } 2488 #else 2489 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2490 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2491 0, /* boundary */ 2492 0, /* flags */ 2493 &addr, &memh)) { 2494 return 1; 2495 } 2496 #endif 2497 2498 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2499 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2500 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2501 2502 pcmhp->memt = sc->sc_memt; 2503 pcmhp->memh = memh; 2504 pcmhp->addr = addr; 2505 pcmhp->size = size; 2506 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2507 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2508 pcmhp->mhandle = 0; 2509 /* No offset??? Funny. */ 2510 2511 return 0; 2512 } 2513 2514 /* 2515 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2516 * struct pcmcia_mem_handle *pcmhp) 2517 * 2518 * This function release the memory space allocated by the function 2519 * pccbb_pcmcia_mem_alloc(). 2520 */ 2521 STATIC void 2522 pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2523 struct pcmcia_mem_handle *pcmhp) 2524 { 2525 #if rbus 2526 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2527 2528 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2529 #else 2530 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2531 #endif 2532 } 2533 2534 /* 2535 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2536 * 2537 * This function release the memory space allocated by the function 2538 * pccbb_pcmcia_mem_alloc(). 2539 */ 2540 STATIC void 2541 pccbb_pcmcia_do_mem_map(struct pccbb_softc *sc, int win) 2542 { 2543 int regbase_win; 2544 bus_addr_t phys_addr; 2545 bus_addr_t phys_end; 2546 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2547 2548 #define PCIC_SMM_START_LOW 0 2549 #define PCIC_SMM_START_HIGH 1 2550 #define PCIC_SMM_STOP_LOW 2 2551 #define PCIC_SMM_STOP_HIGH 3 2552 #define PCIC_CMA_LOW 4 2553 #define PCIC_CMA_HIGH 5 2554 2555 uint8_t start_low, start_high = 0; 2556 uint8_t stop_low, stop_high; 2557 uint8_t off_low, off_high; 2558 uint8_t mem_window; 2559 int reg; 2560 2561 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2562 int mem8 = 2563 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2564 || (kind == PCMCIA_MEM_ATTR); 2565 2566 regbase_win = 0x10 + win * 0x08; 2567 2568 phys_addr = ph->mem[win].addr; 2569 phys_end = phys_addr + ph->mem[win].size; 2570 2571 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2572 (unsigned long)phys_addr, (unsigned long)phys_end, 2573 (unsigned long)ph->mem[win].offset)); 2574 2575 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2576 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2577 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2578 2579 /* bit 19:12 */ 2580 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2581 /* bit 23:20 and bit 7 on */ 2582 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2583 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2584 /* bit 31:24, for 32-bit address */ 2585 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2586 2587 Pcic_write(sc, regbase_win + PCIC_SMM_START_LOW, start_low); 2588 Pcic_write(sc, regbase_win + PCIC_SMM_START_HIGH, start_high); 2589 2590 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2591 Pcic_write(sc, 0x40 + win, mem_window); 2592 } 2593 2594 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2595 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2596 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2597 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2598 2599 Pcic_write(sc, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2600 Pcic_write(sc, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2601 2602 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2603 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2604 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2605 | ((kind == PCMCIA_MEM_ATTR) ? 2606 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2607 2608 Pcic_write(sc, regbase_win + PCIC_CMA_LOW, off_low); 2609 Pcic_write(sc, regbase_win + PCIC_CMA_HIGH, off_high); 2610 2611 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2612 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2613 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2614 2615 #if defined(CBB_DEBUG) 2616 { 2617 int r1, r2, r3, r4, r5, r6, r7 = 0; 2618 2619 r1 = Pcic_read(sc, regbase_win + PCIC_SMM_START_LOW); 2620 r2 = Pcic_read(sc, regbase_win + PCIC_SMM_START_HIGH); 2621 r3 = Pcic_read(sc, regbase_win + PCIC_SMM_STOP_LOW); 2622 r4 = Pcic_read(sc, regbase_win + PCIC_SMM_STOP_HIGH); 2623 r5 = Pcic_read(sc, regbase_win + PCIC_CMA_LOW); 2624 r6 = Pcic_read(sc, regbase_win + PCIC_CMA_HIGH); 2625 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2626 r7 = Pcic_read(sc, 0x40 + win); 2627 } 2628 2629 printf("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2630 "%02x%02x", win, r1, r2, r3, r4, r5, r6); 2631 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2632 printf(" %02x", r7); 2633 } 2634 printf("\n"); 2635 } 2636 #endif 2637 } 2638 2639 /* 2640 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2641 * bus_addr_t card_addr, bus_size_t size, 2642 * struct pcmcia_mem_handle *pcmhp, 2643 * bus_addr_t *offsetp, int *windowp) 2644 * 2645 * This function maps memory space allocated by the function 2646 * pccbb_pcmcia_mem_alloc(). 2647 */ 2648 STATIC int 2649 pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2650 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 2651 bus_size_t *offsetp, int *windowp) 2652 { 2653 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2654 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2655 bus_addr_t busaddr; 2656 long card_offset; 2657 int win; 2658 2659 /* Check that the card is still there. */ 2660 if ((Pcic_read(sc, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2661 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2662 return 1; 2663 2664 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2665 if ((ph->memalloc & (1 << win)) == 0) { 2666 ph->memalloc |= (1 << win); 2667 break; 2668 } 2669 } 2670 2671 if (win == PCIC_MEM_WINS) 2672 return 1; 2673 2674 *windowp = win; 2675 2676 /* XXX this is pretty gross */ 2677 2678 if (!bus_space_is_equal(sc->sc_memt, pcmhp->memt)) { 2679 panic("pccbb_pcmcia_mem_map memt is bogus"); 2680 } 2681 2682 busaddr = pcmhp->addr; 2683 2684 /* 2685 * compute the address offset to the pcmcia address space for the 2686 * pcic. this is intentionally signed. The masks and shifts below 2687 * will cause TRT to happen in the pcic registers. Deal with making 2688 * sure the address is aligned, and return the alignment offset. 2689 */ 2690 2691 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2692 card_addr -= *offsetp; 2693 2694 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2695 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2696 (u_long) card_addr)); 2697 2698 /* 2699 * include the offset in the size, and decrement size by one, since 2700 * the hw wants start/stop 2701 */ 2702 size += *offsetp - 1; 2703 2704 card_offset = (((long)card_addr) - ((long)busaddr)); 2705 2706 ph->mem[win].addr = busaddr; 2707 ph->mem[win].size = size; 2708 ph->mem[win].offset = card_offset; 2709 ph->mem[win].kind = kind; 2710 2711 pccbb_pcmcia_do_mem_map(sc, win); 2712 2713 return 0; 2714 } 2715 2716 /* 2717 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2718 * int window) 2719 * 2720 * This function unmaps memory space which mapped by the function 2721 * pccbb_pcmcia_mem_map(). 2722 */ 2723 STATIC void 2724 pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window) 2725 { 2726 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2727 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2728 int reg; 2729 2730 if (window >= PCIC_MEM_WINS) 2731 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2732 2733 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2734 reg &= ~(1 << window); 2735 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2736 2737 ph->memalloc &= ~(1 << window); 2738 } 2739 2740 /* 2741 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2742 * struct pcmcia_function *pf, 2743 * int ipl, 2744 * int (*func)(void *), 2745 * void *arg); 2746 * 2747 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2748 */ 2749 STATIC void * 2750 pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2751 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg) 2752 { 2753 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2754 2755 if (!(pf->cfe->flags & (PCMCIA_CFE_IRQLEVEL|PCMCIA_CFE_IRQPULSE))) { 2756 /* 2757 * XXX Noooooo! The interrupt flag must set properly!! 2758 * dumb pcmcia driver!! 2759 */ 2760 DPRINTF(("%s does not provide edge nor pulse interrupt\n", 2761 device_xname(sc->sc_dev))); 2762 return NULL; 2763 } 2764 2765 return pccbb_intr_establish(sc, ipl, func, arg); 2766 } 2767 2768 /* 2769 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2770 * void *ih) 2771 * 2772 * This function disables PC-Card interrupt. 2773 */ 2774 STATIC void 2775 pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 2776 { 2777 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2778 2779 pccbb_intr_disestablish(sc, ih); 2780 } 2781 2782 #if rbus 2783 /* 2784 * static int 2785 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2786 * bus_addr_t addr, bus_size_t size, 2787 * bus_addr_t mask, bus_size_t align, 2788 * int flags, bus_addr_t *addrp; 2789 * bus_space_handle_t *bshp) 2790 * 2791 * This function allocates a portion of memory or io space for 2792 * clients. This function is called from CardBus card drivers. 2793 */ 2794 static int 2795 pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2796 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 2797 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 2798 { 2799 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2800 2801 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 2802 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 2803 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 2804 2805 if (align == 0) 2806 align = size; 2807 2808 if (bus_space_is_equal(rb->rb_bt, sc->sc_memt)) { 2809 if (align < 16) { 2810 return 1; 2811 } 2812 /* 2813 * XXX: align more than 0x1000 to avoid overwrapping 2814 * memory windows for two or more devices. 0x1000 2815 * means memory window's granularity. 2816 * 2817 * Two or more devices should be able to share same 2818 * memory window region. However, overrapping memory 2819 * window is not good because some devices, such as 2820 * 3Com 3C575[BC], have a broken address decoder and 2821 * intrude other's memory region. 2822 */ 2823 if (align < 0x1000) { 2824 align = 0x1000; 2825 } 2826 } else if (bus_space_is_equal(rb->rb_bt, sc->sc_iot)) { 2827 if (align < 4) { 2828 return 1; 2829 } 2830 /* XXX: hack for avoiding ISA image */ 2831 if (mask < 0x0100) { 2832 mask = 0x3ff; 2833 addr = 0x300; 2834 } 2835 2836 } else { 2837 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 2838 "NOT used. io: 0x%lx, mem: 0x%lx\n", 2839 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 2840 (unsigned long)sc->sc_memt)); 2841 return 1; 2842 /* XXX: panic here? */ 2843 } 2844 2845 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2846 aprint_normal_dev(sc->sc_dev, "<rbus> no bus space\n"); 2847 return 1; 2848 } 2849 2850 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2851 2852 return 0; 2853 } 2854 2855 /* 2856 * static int 2857 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2858 * bus_space_handle_t *bshp, bus_size_t size); 2859 * 2860 * This function is called from CardBus card drivers. 2861 */ 2862 static int 2863 pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2864 bus_space_handle_t bsh, bus_size_t size) 2865 { 2866 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2867 bus_space_tag_t bt = rb->rb_bt; 2868 2869 pccbb_close_win(sc, bt, bsh, size); 2870 2871 if (bus_space_is_equal(bt, sc->sc_memt)) { 2872 } else if (bus_space_is_equal(bt, sc->sc_iot)) { 2873 } else { 2874 return 1; 2875 /* XXX: panic here? */ 2876 } 2877 2878 return rbus_space_free(rb, bsh, size, NULL); 2879 } 2880 #endif /* rbus */ 2881 2882 #if rbus 2883 2884 static int 2885 pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr, 2886 bus_size_t size, bus_space_handle_t bsh, int flags) 2887 { 2888 struct pccbb_win_chain_head *head; 2889 bus_addr_t align; 2890 2891 head = &sc->sc_iowindow; 2892 align = 0x04; 2893 if (bus_space_is_equal(sc->sc_memt, bst)) { 2894 head = &sc->sc_memwindow; 2895 align = 0x1000; 2896 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 2897 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 2898 (unsigned long)bst)); 2899 } 2900 2901 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2902 aprint_error_dev(sc->sc_dev, 2903 "pccbb_open_win: %s winlist insert failed\n", 2904 (head == &sc->sc_memwindow) ? "mem" : "io"); 2905 } 2906 pccbb_winset(align, sc, bst); 2907 2908 return 0; 2909 } 2910 2911 static int 2912 pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst, 2913 bus_space_handle_t bsh, bus_size_t size) 2914 { 2915 struct pccbb_win_chain_head *head; 2916 bus_addr_t align; 2917 2918 head = &sc->sc_iowindow; 2919 align = 0x04; 2920 if (bus_space_is_equal(sc->sc_memt, bst)) { 2921 head = &sc->sc_memwindow; 2922 align = 0x1000; 2923 } 2924 2925 if (pccbb_winlist_delete(head, bsh, size)) { 2926 aprint_error_dev(sc->sc_dev, 2927 "pccbb_close_win: %s winlist delete failed\n", 2928 (head == &sc->sc_memwindow) ? "mem" : "io"); 2929 } 2930 pccbb_winset(align, sc, bst); 2931 2932 return 0; 2933 } 2934 2935 static int 2936 pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start, 2937 bus_size_t size, bus_space_handle_t bsh, int flags) 2938 { 2939 struct pccbb_win_chain *chainp, *elem; 2940 2941 elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 2942 M_WAITOK); 2943 elem->wc_start = start; 2944 elem->wc_end = start + (size - 1); 2945 elem->wc_handle = bsh; 2946 elem->wc_flags = flags; 2947 2948 TAILQ_FOREACH(chainp, head, wc_list) { 2949 if (chainp->wc_end >= start) 2950 break; 2951 } 2952 if (chainp != NULL) 2953 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 2954 else 2955 TAILQ_INSERT_TAIL(head, elem, wc_list); 2956 return 0; 2957 } 2958 2959 static int 2960 pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh, 2961 bus_size_t size) 2962 { 2963 struct pccbb_win_chain *chainp; 2964 2965 TAILQ_FOREACH(chainp, head, wc_list) { 2966 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh)) == 0) 2967 break; 2968 } 2969 if (chainp == NULL) 2970 return 1; /* fail: no candidate to remove */ 2971 2972 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 2973 printf("pccbb_winlist_delete: window 0x%lx size " 2974 "inconsistent: 0x%lx, 0x%lx\n", 2975 (unsigned long)chainp->wc_start, 2976 (unsigned long)(chainp->wc_end - chainp->wc_start), 2977 (unsigned long)(size - 1)); 2978 return 1; 2979 } 2980 2981 TAILQ_REMOVE(head, chainp, wc_list); 2982 free(chainp, M_DEVBUF); 2983 2984 return 0; 2985 } 2986 2987 static void 2988 pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst) 2989 { 2990 pci_chipset_tag_t pc; 2991 pcitag_t tag; 2992 bus_addr_t mask = ~(align - 1); 2993 struct { 2994 pcireg_t win_start; 2995 pcireg_t win_limit; 2996 int win_flags; 2997 } win[2]; 2998 struct pccbb_win_chain *chainp; 2999 int offs; 3000 3001 win[0].win_start = win[1].win_start = 0xffffffff; 3002 win[0].win_limit = win[1].win_limit = 0; 3003 win[0].win_flags = win[1].win_flags = 0; 3004 3005 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3006 offs = PCI_CB_IOBASE0; 3007 if (bus_space_is_equal(sc->sc_memt, bst)) { 3008 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3009 offs = PCI_CB_MEMBASE0; 3010 } 3011 3012 if (chainp != NULL) { 3013 win[0].win_start = chainp->wc_start & mask; 3014 win[0].win_limit = chainp->wc_end & mask; 3015 win[0].win_flags = chainp->wc_flags; 3016 chainp = TAILQ_NEXT(chainp, wc_list); 3017 } 3018 3019 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3020 if (win[1].win_start == 0xffffffff) { 3021 /* window 1 is not used */ 3022 if ((win[0].win_flags == chainp->wc_flags) && 3023 (win[0].win_limit + align >= 3024 (chainp->wc_start & mask))) { 3025 /* concatenate */ 3026 win[0].win_limit = chainp->wc_end & mask; 3027 } else { 3028 /* make new window */ 3029 win[1].win_start = chainp->wc_start & mask; 3030 win[1].win_limit = chainp->wc_end & mask; 3031 win[1].win_flags = chainp->wc_flags; 3032 } 3033 continue; 3034 } 3035 3036 /* Both windows are engaged. */ 3037 if (win[0].win_flags == win[1].win_flags) { 3038 /* same flags */ 3039 if (win[0].win_flags == chainp->wc_flags) { 3040 if (win[1].win_start - (win[0].win_limit + 3041 align) < 3042 (chainp->wc_start & mask) - 3043 ((chainp->wc_end & mask) + align)) { 3044 /* 3045 * merge window 0 and 1, and set win1 3046 * to chainp 3047 */ 3048 win[0].win_limit = win[1].win_limit; 3049 win[1].win_start = 3050 chainp->wc_start & mask; 3051 win[1].win_limit = 3052 chainp->wc_end & mask; 3053 } else { 3054 win[1].win_limit = 3055 chainp->wc_end & mask; 3056 } 3057 } else { 3058 /* different flags */ 3059 3060 /* concatenate win0 and win1 */ 3061 win[0].win_limit = win[1].win_limit; 3062 /* allocate win[1] to new space */ 3063 win[1].win_start = chainp->wc_start & mask; 3064 win[1].win_limit = chainp->wc_end & mask; 3065 win[1].win_flags = chainp->wc_flags; 3066 } 3067 } else { 3068 /* the flags of win[0] and win[1] is different */ 3069 if (win[0].win_flags == chainp->wc_flags) { 3070 win[0].win_limit = chainp->wc_end & mask; 3071 /* 3072 * XXX this creates overlapping windows, so 3073 * what should the poor bridge do if one is 3074 * cachable, and the other is not? 3075 */ 3076 aprint_error_dev(sc->sc_dev, 3077 "overlapping windows\n"); 3078 } else { 3079 win[1].win_limit = chainp->wc_end & mask; 3080 } 3081 } 3082 } 3083 3084 pc = sc->sc_pc; 3085 tag = sc->sc_tag; 3086 pci_conf_write(pc, tag, offs, win[0].win_start); 3087 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3088 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3089 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3090 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3091 (unsigned long)pci_conf_read(pc, tag, offs), 3092 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3093 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3094 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3095 3096 if (bus_space_is_equal(bst, sc->sc_memt)) { 3097 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 3098 3099 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3100 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3101 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3102 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3103 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3104 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 3105 } 3106 } 3107 3108 #endif /* rbus */ 3109 3110 static bool 3111 pccbb_suspend(device_t dv, const pmf_qual_t *qual) 3112 { 3113 struct pccbb_softc *sc = device_private(dv); 3114 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3115 bus_space_handle_t base_memh = sc->sc_base_memh; 3116 pcireg_t reg; 3117 3118 if (sc->sc_pil_intr_enable) 3119 (void)pccbbintr_function(sc); 3120 sc->sc_pil_intr_enable = false; 3121 3122 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3123 /* Disable interrupts. */ 3124 reg &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER); 3125 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3126 /* XXX joerg Disable power to the socket? */ 3127 3128 /* XXX flush PCI write */ 3129 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3130 3131 /* reset interrupt */ 3132 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 3133 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 3134 /* XXX flush PCI write */ 3135 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3136 3137 if (sc->sc_ih != NULL) { 3138 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 3139 sc->sc_ih = NULL; 3140 } 3141 3142 return true; 3143 } 3144 3145 static bool 3146 pccbb_resume(device_t dv, const pmf_qual_t *qual) 3147 { 3148 struct pccbb_softc *sc = device_private(dv); 3149 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3150 bus_space_handle_t base_memh = sc->sc_base_memh; 3151 pcireg_t reg; 3152 3153 pccbb_chipinit(sc); 3154 pccbb_intrinit(sc); 3155 /* setup memory and io space window for CB */ 3156 pccbb_winset(0x1000, sc, sc->sc_memt); 3157 pccbb_winset(0x04, sc, sc->sc_iot); 3158 3159 /* CSC Interrupt: Card detect interrupt on */ 3160 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3161 /* Card detect intr is turned on. */ 3162 reg |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3163 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3164 /* reset interrupt */ 3165 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3166 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3167 3168 /* 3169 * check for card insertion or removal during suspend period. 3170 * XXX: the code can't cope with card swap (remove then 3171 * insert). how can we detect such situation? 3172 */ 3173 (void)pccbbintr(sc); 3174 3175 sc->sc_pil_intr_enable = true; 3176 3177 return true; 3178 } 3179
Indexes created Thu Sep 25 16:09:42 GMT 2025