/src/sys/dev/pci/ |
if_ath_pci.c | 257 pcireg_t bhlc, csr, icr, lattimer; local in function:ath_pci_setup 301 bhlc = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BHLC_REG); 304 if (PCI_LATTIMER(bhlc) < lattimer) { 305 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 306 bhlc |= (lattimer << PCI_LATTIMER_SHIFT); 307 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BHLC_REG, bhlc);
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puc.c | 106 pcireg_t bhlc, subsys; local in function:puc_match 108 bhlc = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 109 if (PCI_HDRTYPE_TYPE(bhlc) != 0)
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if_rtw_pci.c | 329 pcireg_t bhlc, csr, lattimer; local in function:rtw_pci_setup 344 bhlc = pci_conf_read(psc->psc_pc, tag, PCI_BHLC_REG); 345 lattimer = rounddown(PCI_LATTIMER(bhlc), 0x10); 346 if (PCI_LATTIMER(bhlc) != lattimer) { 347 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 348 bhlc |= (lattimer << PCI_LATTIMER_SHIFT); 349 pci_conf_write(psc->psc_pc, tag, PCI_BHLC_REG, bhlc);
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ppb.c | 98 pcireg_t bhlc = pci_conf_read(pa->pa_pc, pa->pa_tag, local in function:ppbmatch 101 && PCI_HDRTYPE(bhlc) == PCI_HDRTYPE_RC)
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pciconf.c | 593 pcireg_t classreg, cmd, icr, bhlc, bar, mask, bar64, mask64, local in function:pci_do_device_query 608 bhlc = pci_conf_read(pb->pc, tag, PCI_BHLC_REG); 619 && PCI_HDRTYPE_TYPE(bhlc) != PCI_HDRTYPE_PPB) { 634 switch (PCI_HDRTYPE_TYPE(bhlc)) { 1526 * 4. The latency part of the PCI BHLC (BIST (Built-In Self Test),
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pccbb.c | 645 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); local in function:pccbb_pci_callback 660 cba.cba_cacheline = PCI_CACHELINE(bhlc); 661 cba.cba_max_lattimer = PCI_LATTIMER(bhlc); 665 aprint_verbose_dev(self, "bhlc 0x%x\n", bhlc); 715 pcireg_t bcr, bhlc, cbctl, csr, lscp, mfunc, mrburst, slotctl, sockctl, local in function:pccbb_chipinit 752 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 753 if (PCI_LATTIMER(bhlc) < 0x10) { 754 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 755 bhlc |= (0x10 << PCI_LATTIMER_SHIFT) [all...] |
/src/sys/dev/cardbus/ |
if_rtw_cardbus.c | 365 pcireg_t bhlc, csr, lattimer; local in function:rtw_cardbus_setup 372 bhlc = Cardbus_conf_read(ct, tag, PCI_BHLC_REG); 373 lattimer = rounddown(PCI_LATTIMER(bhlc), 0x10); 374 if (PCI_LATTIMER(bhlc) != lattimer) { 375 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 376 bhlc |= (lattimer << PCI_LATTIMER_SHIFT); 377 Cardbus_conf_write(ct, tag, PCI_BHLC_REG, bhlc);
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cardbus.c | 444 pcireg_t bhlc, icr, lattimer; local in function:cardbus_rescan 498 bhlc = cardbus_conf_read(cc, cf, tag, PCI_BHLC_REG); 499 DPRINTF(("%s bhlc 0x%08x -> ", device_xname(sc->sc_dev), bhlc)); 500 nfunction = PCI_HDRTYPE_MULTIFN(bhlc) ? 8 : 1; 541 bhlc = cardbus_conf_read(cc, cf, tag, PCI_BHLC_REG); 543 DPRINTF(("%s func%d icr 0x%08x bhlc 0x%08x -> ", 544 device_xname(sc->sc_dev), function, icr, bhlc)); 545 bhlc &= ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT); 546 bhlc |= (sc->sc_cacheline & PCI_CACHELINE_MASK) < [all...] |
/src/sys/arch/sparc64/dev/ |
pci_machdep.c | 254 pcireg_t class, csr, bhlc, ic; local in function:sparc64_pci_enumerate_bus1 294 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 295 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 296 bhlc |= 0x40 << PCI_LATTIMER_SHIFT; 297 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 350 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 354 if (lt == 0 || lt < PCI_LATTIMER(bhlc)) 355 lt = PCI_LATTIMER(bhlc); 357 cl = PCI_CACHELINE(bhlc); 361 bhlc &= ~((PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT) [all...] |
/src/sys/arch/hppa/dev/ |
ssio.c | 130 pcireg_t bhlc, id; local in function:ssio_match 141 bhlc = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 142 if (!PCI_HDRTYPE_MULTIFN(bhlc))
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/src/sys/dev/pci/cxgb/ |
cxgb_main.c | 843 uint32_t bhlc; local in function:t3_os_find_pci_capability 850 bhlc = pci_conf_read(sc->pa.pa_pc, sc->pa.pa_tag, PCI_BHLC_REG); 851 switch (PCI_HDRTYPE(bhlc))
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