1 /* $NetBSD: ixgbe_phy.c,v 1.29 2021/12/24 05:02:11 msaitoh Exp $ */ 2 3 /****************************************************************************** 4 SPDX-License-Identifier: BSD-3-Clause 5 6 Copyright (c) 2001-2020, Intel Corporation 7 All rights reserved. 8 9 Redistribution and use in source and binary forms, with or without 10 modification, are permitted provided that the following conditions are met: 11 12 1. Redistributions of source code must retain the above copyright notice, 13 this list of conditions and the following disclaimer. 14 15 2. Redistributions in binary form must reproduce the above copyright 16 notice, this list of conditions and the following disclaimer in the 17 documentation and/or other materials provided with the distribution. 18 19 3. Neither the name of the Intel Corporation nor the names of its 20 contributors may be used to endorse or promote products derived from 21 this software without specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 27 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 POSSIBILITY OF SUCH DAMAGE. 34 35 ******************************************************************************/ 36 /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_phy.c 331224 2018-03-19 20:55:05Z erj $*/ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: ixgbe_phy.c,v 1.29 2021/12/24 05:02:11 msaitoh Exp $"); 40 41 #include "ixgbe_api.h" 42 #include "ixgbe_common.h" 43 #include "ixgbe_phy.h" 44 45 #include <dev/mii/mdio.h> 46 47 static void ixgbe_i2c_start(struct ixgbe_hw *hw); 48 static void ixgbe_i2c_stop(struct ixgbe_hw *hw); 49 static void ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); 50 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); 51 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 52 static void ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); 53 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); 54 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 55 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 56 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); 57 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl); 58 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 59 u8 *sff8472_data); 60 61 /** 62 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack 63 * @hw: pointer to the hardware structure 64 * @byte: byte to send 65 * 66 * Returns an error code on error. 67 */ 68 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte) 69 { 70 s32 status; 71 72 status = ixgbe_clock_out_i2c_byte(hw, byte); 73 if (status) 74 return status; 75 return ixgbe_get_i2c_ack(hw); 76 } 77 78 /** 79 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack 80 * @hw: pointer to the hardware structure 81 * @byte: pointer to a u8 to receive the byte 82 * 83 * Returns an error code on error. 84 */ 85 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte) 86 { 87 ixgbe_clock_in_i2c_byte(hw, byte); 88 /* ACK */ 89 return ixgbe_clock_out_i2c_bit(hw, FALSE); 90 } 91 92 /** 93 * ixgbe_ones_comp_byte_add - Perform one's complement addition 94 * @add1: addend 1 95 * @add2: addend 2 96 * 97 * Returns one's complement 8-bit sum. 98 */ 99 static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2) 100 { 101 u16 sum = add1 + add2; 102 103 sum = (sum & 0xFF) + (sum >> 8); 104 return sum & 0xFF; 105 } 106 107 /** 108 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation 109 * @hw: pointer to the hardware structure 110 * @addr: I2C bus address to read from 111 * @reg: I2C device register to read from 112 * @val: pointer to location to receive read value 113 * @lock: TRUE if to take and release semaphore 114 * 115 * Returns an error code on error. 116 */ 117 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg, 118 u16 *val, bool lock) 119 { 120 u32 swfw_mask = hw->phy.phy_semaphore_mask; 121 int max_retry = 3; 122 int retry = 0; 123 u8 csum_byte; 124 u8 high_bits; 125 u8 low_bits; 126 u8 reg_high; 127 u8 csum; 128 129 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */ 130 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 131 csum = ~csum; 132 do { 133 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 134 return IXGBE_ERR_SWFW_SYNC; 135 ixgbe_i2c_start(hw); 136 /* Device Address and write indication */ 137 if (ixgbe_out_i2c_byte_ack(hw, addr)) 138 goto fail; 139 /* Write bits 14:8 */ 140 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 141 goto fail; 142 /* Write bits 7:0 */ 143 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 144 goto fail; 145 /* Write csum */ 146 if (ixgbe_out_i2c_byte_ack(hw, csum)) 147 goto fail; 148 /* Re-start condition */ 149 ixgbe_i2c_start(hw); 150 /* Device Address and read indication */ 151 if (ixgbe_out_i2c_byte_ack(hw, addr | 1)) 152 goto fail; 153 /* Get upper bits */ 154 if (ixgbe_in_i2c_byte_ack(hw, &high_bits)) 155 goto fail; 156 /* Get low bits */ 157 if (ixgbe_in_i2c_byte_ack(hw, &low_bits)) 158 goto fail; 159 /* Get csum */ 160 ixgbe_clock_in_i2c_byte(hw, &csum_byte); 161 /* NACK */ 162 if (ixgbe_clock_out_i2c_bit(hw, FALSE)) 163 goto fail; 164 ixgbe_i2c_stop(hw); 165 if (lock) 166 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 167 *val = (high_bits << 8) | low_bits; 168 return 0; 169 170 fail: 171 ixgbe_i2c_bus_clear(hw); 172 if (lock) 173 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 174 if (retry < max_retry) 175 DEBUGOUT("I2C byte read combined error - Retrying.\n"); 176 else 177 DEBUGOUT("I2C byte read combined error.\n"); 178 retry++; 179 } while (retry <= max_retry); 180 181 return IXGBE_ERR_I2C; 182 } 183 184 /** 185 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation 186 * @hw: pointer to the hardware structure 187 * @addr: I2C bus address to write to 188 * @reg: I2C device register to write to 189 * @val: value to write 190 * @lock: TRUE if to take and release semaphore 191 * 192 * Returns an error code on error. 193 */ 194 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg, 195 u16 val, bool lock) 196 { 197 u32 swfw_mask = hw->phy.phy_semaphore_mask; 198 int max_retry = 1; 199 int retry = 0; 200 u8 reg_high; 201 u8 csum; 202 203 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */ 204 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 205 csum = ixgbe_ones_comp_byte_add(csum, val >> 8); 206 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF); 207 csum = ~csum; 208 do { 209 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 210 return IXGBE_ERR_SWFW_SYNC; 211 ixgbe_i2c_start(hw); 212 /* Device Address and write indication */ 213 if (ixgbe_out_i2c_byte_ack(hw, addr)) 214 goto fail; 215 /* Write bits 14:8 */ 216 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 217 goto fail; 218 /* Write bits 7:0 */ 219 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 220 goto fail; 221 /* Write data 15:8 */ 222 if (ixgbe_out_i2c_byte_ack(hw, val >> 8)) 223 goto fail; 224 /* Write data 7:0 */ 225 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF)) 226 goto fail; 227 /* Write csum */ 228 if (ixgbe_out_i2c_byte_ack(hw, csum)) 229 goto fail; 230 ixgbe_i2c_stop(hw); 231 if (lock) 232 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 233 return 0; 234 235 fail: 236 ixgbe_i2c_bus_clear(hw); 237 if (lock) 238 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 239 if (retry < max_retry) 240 DEBUGOUT("I2C byte write combined error - Retrying.\n"); 241 else 242 DEBUGOUT("I2C byte write combined error.\n"); 243 retry++; 244 } while (retry <= max_retry); 245 246 return IXGBE_ERR_I2C; 247 } 248 249 /** 250 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs 251 * @hw: pointer to the hardware structure 252 * 253 * Initialize the function pointers. 254 **/ 255 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw) 256 { 257 struct ixgbe_phy_info *phy = &hw->phy; 258 259 DEBUGFUNC("ixgbe_init_phy_ops_generic"); 260 261 /* PHY */ 262 phy->ops.identify = ixgbe_identify_phy_generic; 263 phy->ops.reset = ixgbe_reset_phy_generic; 264 phy->ops.read_reg = ixgbe_read_phy_reg_generic; 265 phy->ops.write_reg = ixgbe_write_phy_reg_generic; 266 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi; 267 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi; 268 phy->ops.setup_link = ixgbe_setup_phy_link_generic; 269 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic; 270 phy->ops.check_link = NULL; 271 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic; 272 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic; 273 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic; 274 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic; 275 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic; 276 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic; 277 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear; 278 phy->ops.identify_sfp = ixgbe_identify_module_generic; 279 phy->sfp_type = ixgbe_sfp_type_unknown; 280 phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked; 281 phy->ops.write_i2c_byte_unlocked = 282 ixgbe_write_i2c_byte_generic_unlocked; 283 phy->ops.check_overtemp = ixgbe_tn_check_overtemp; 284 return IXGBE_SUCCESS; 285 } 286 287 /** 288 * ixgbe_probe_phy - Probe a single address for a PHY 289 * @hw: pointer to hardware structure 290 * @phy_addr: PHY address to probe 291 * 292 * Returns TRUE if PHY found 293 */ 294 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr) 295 { 296 u16 ext_ability = 0; 297 298 if (!ixgbe_validate_phy_addr(hw, phy_addr)) { 299 DEBUGOUT1("Unable to validate PHY address 0x%04X\n", 300 phy_addr); 301 return FALSE; 302 } 303 304 if (ixgbe_get_phy_id(hw)) 305 return FALSE; 306 307 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id); 308 309 if (hw->phy.type == ixgbe_phy_unknown) { 310 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 311 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 312 if (ext_ability & 313 (IXGBE_MDIO_PHY_10GBASET_ABILITY | 314 IXGBE_MDIO_PHY_1000BASET_ABILITY)) 315 hw->phy.type = ixgbe_phy_cu_unknown; 316 else 317 hw->phy.type = ixgbe_phy_generic; 318 } 319 320 return TRUE; 321 } 322 323 /** 324 * ixgbe_identify_phy_generic - Get physical layer module 325 * @hw: pointer to hardware structure 326 * 327 * Determines the physical layer module found on the current adapter. 328 **/ 329 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 330 { 331 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 332 u16 phy_addr; 333 334 DEBUGFUNC("ixgbe_identify_phy_generic"); 335 336 if (!hw->phy.phy_semaphore_mask) { 337 if (hw->bus.lan_id) 338 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 339 else 340 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 341 } 342 343 if (hw->phy.type != ixgbe_phy_unknown) 344 return IXGBE_SUCCESS; 345 346 if (hw->phy.nw_mng_if_sel) { 347 phy_addr = (hw->phy.nw_mng_if_sel & 348 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >> 349 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT; 350 if (ixgbe_probe_phy(hw, phy_addr)) 351 return IXGBE_SUCCESS; 352 else 353 return IXGBE_ERR_PHY_ADDR_INVALID; 354 } 355 356 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 357 if (ixgbe_probe_phy(hw, phy_addr)) { 358 status = IXGBE_SUCCESS; 359 break; 360 } 361 } 362 363 /* Certain media types do not have a phy so an address will not 364 * be found and the code will take this path. Caller has to 365 * decide if it is an error or not. 366 */ 367 if (status != IXGBE_SUCCESS) 368 hw->phy.addr = 0; 369 370 return status; 371 } 372 373 /** 374 * ixgbe_check_reset_blocked - check status of MNG FW veto bit 375 * @hw: pointer to the hardware structure 376 * 377 * This function checks the MMNGC.MNG_VETO bit to see if there are 378 * any constraints on link from manageability. For MAC's that don't 379 * have this bit just return faluse since the link can not be blocked 380 * via this method. 381 **/ 382 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw) 383 { 384 u32 mmngc; 385 386 DEBUGFUNC("ixgbe_check_reset_blocked"); 387 388 /* If we don't have this bit, it can't be blocking */ 389 if (hw->mac.type == ixgbe_mac_82598EB) 390 return FALSE; 391 392 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC); 393 if (mmngc & IXGBE_MMNGC_MNG_VETO) { 394 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, 395 "MNG_VETO bit detected.\n"); 396 return TRUE; 397 } 398 399 return FALSE; 400 } 401 402 /** 403 * ixgbe_validate_phy_addr - Determines phy address is valid 404 * @hw: pointer to hardware structure 405 * @phy_addr: PHY address 406 * 407 **/ 408 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) 409 { 410 u16 phy_id = 0; 411 bool valid = FALSE; 412 413 DEBUGFUNC("ixgbe_validate_phy_addr"); 414 415 hw->phy.addr = phy_addr; 416 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 417 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); 418 419 if (phy_id != 0xFFFF && phy_id != 0x0) 420 valid = TRUE; 421 422 DEBUGOUT1("PHY ID HIGH is 0x%04X\n", phy_id); 423 424 return valid; 425 } 426 427 /** 428 * ixgbe_get_phy_id - Get the phy type 429 * @hw: pointer to hardware structure 430 * 431 **/ 432 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) 433 { 434 u32 status; 435 u16 phy_id_high = 0; 436 u16 phy_id_low = 0; 437 438 DEBUGFUNC("ixgbe_get_phy_id"); 439 440 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 441 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 442 &phy_id_high); 443 444 if (status == IXGBE_SUCCESS) { 445 hw->phy.id = (u32)(phy_id_high << 16); 446 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW, 447 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 448 &phy_id_low); 449 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 450 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 451 } 452 DEBUGOUT2("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n", 453 phy_id_high, phy_id_low); 454 455 return status; 456 } 457 458 /** 459 * ixgbe_get_phy_type_from_id - Get the phy type 460 * @phy_id: PHY ID information 461 * 462 **/ 463 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) 464 { 465 enum ixgbe_phy_type phy_type; 466 467 DEBUGFUNC("ixgbe_get_phy_type_from_id"); 468 469 switch (phy_id) { 470 case TN1010_PHY_ID: 471 phy_type = ixgbe_phy_tn; 472 break; 473 case X550_PHY_ID: 474 case X540_PHY_ID: 475 phy_type = ixgbe_phy_aq; 476 break; 477 case QT2022_PHY_ID: 478 phy_type = ixgbe_phy_qt; 479 break; 480 case ATH_PHY_ID: 481 phy_type = ixgbe_phy_nl; 482 break; 483 case X557_PHY_ID: 484 case X557_PHY_ID2: 485 phy_type = ixgbe_phy_x550em_ext_t; 486 break; 487 case IXGBE_M88E1500_E_PHY_ID: 488 case IXGBE_M88E1543_E_PHY_ID: 489 phy_type = ixgbe_phy_ext_1g_t; 490 break; 491 default: 492 phy_type = ixgbe_phy_unknown; 493 break; 494 } 495 return phy_type; 496 } 497 498 /** 499 * ixgbe_reset_phy_generic - Performs a PHY reset 500 * @hw: pointer to hardware structure 501 **/ 502 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 503 { 504 u32 i; 505 u16 ctrl = 0; 506 s32 status = IXGBE_SUCCESS; 507 508 DEBUGFUNC("ixgbe_reset_phy_generic"); 509 510 if (hw->phy.type == ixgbe_phy_unknown) 511 status = ixgbe_identify_phy_generic(hw); 512 513 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none) 514 goto out; 515 516 /* Don't reset PHY if it's shut down due to overtemp. */ 517 if (!hw->phy.reset_if_overtemp && 518 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) 519 goto out; 520 521 /* Blocked by MNG FW so bail */ 522 if (ixgbe_check_reset_blocked(hw)) 523 goto out; 524 525 /* 526 * Perform soft PHY reset to the PHY_XS. 527 * This will cause a soft reset to the PHY 528 */ 529 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 530 IXGBE_MDIO_PHY_XS_DEV_TYPE, 531 IXGBE_MDIO_PHY_XS_RESET); 532 533 /* 534 * Poll for reset bit to self-clear indicating reset is complete. 535 * Some PHYs could take up to 3 seconds to complete and need about 536 * 1.7 usec delay after the reset is complete. 537 */ 538 for (i = 0; i < 30; i++) { 539 msec_delay(100); 540 if (hw->phy.type == ixgbe_phy_x550em_ext_t) { 541 status = hw->phy.ops.read_reg(hw, 542 IXGBE_MDIO_TX_VENDOR_ALARMS_3, 543 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 544 &ctrl); 545 if (status != IXGBE_SUCCESS) 546 return status; 547 548 if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) { 549 usec_delay(2); 550 break; 551 } 552 } else { 553 status = hw->phy.ops.read_reg(hw, 554 IXGBE_MDIO_PHY_XS_CONTROL, 555 IXGBE_MDIO_PHY_XS_DEV_TYPE, 556 &ctrl); 557 if (status != IXGBE_SUCCESS) 558 return status; 559 560 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) { 561 usec_delay(2); 562 break; 563 } 564 } 565 } 566 567 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) { 568 status = IXGBE_ERR_RESET_FAILED; 569 ERROR_REPORT1(IXGBE_ERROR_POLLING, 570 "PHY reset polling failed to complete.\n"); 571 } 572 573 out: 574 return status; 575 } 576 577 /** 578 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without 579 * the SWFW lock 580 * @hw: pointer to hardware structure 581 * @reg_addr: 32 bit address of PHY register to read 582 * @device_type: 5 bit device type 583 * @phy_data: Pointer to read data from PHY register 584 **/ 585 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 586 u16 *phy_data) 587 { 588 u32 i, data, command; 589 590 /* Setup and write the address cycle command */ 591 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 592 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 593 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 594 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 595 596 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 597 598 /* 599 * Check every 10 usec to see if the address cycle completed. 600 * The MDI Command bit will clear when the operation is 601 * complete 602 */ 603 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 604 usec_delay(10); 605 606 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 607 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 608 break; 609 } 610 611 612 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 613 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n"); 614 DEBUGOUT("PHY address command did not complete, returning IXGBE_ERR_PHY\n"); 615 return IXGBE_ERR_PHY; 616 } 617 618 /* 619 * Address cycle complete, setup and write the read 620 * command 621 */ 622 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 623 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 624 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 625 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 626 627 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 628 629 /* 630 * Check every 10 usec to see if the address cycle 631 * completed. The MDI Command bit will clear when the 632 * operation is complete 633 */ 634 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 635 usec_delay(10); 636 637 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 638 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 639 break; 640 } 641 642 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 643 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n"); 644 DEBUGOUT("PHY read command didn't complete, returning IXGBE_ERR_PHY\n"); 645 return IXGBE_ERR_PHY; 646 } 647 648 /* 649 * Read operation is complete. Get the data 650 * from MSRWD 651 */ 652 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 653 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 654 *phy_data = (u16)(data); 655 656 return IXGBE_SUCCESS; 657 } 658 659 /** 660 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 661 * using the SWFW lock - this function is needed in most cases 662 * @hw: pointer to hardware structure 663 * @reg_addr: 32 bit address of PHY register to read 664 * @device_type: 5 bit device type 665 * @phy_data: Pointer to read data from PHY register 666 **/ 667 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 668 u32 device_type, u16 *phy_data) 669 { 670 s32 status; 671 u32 gssr = hw->phy.phy_semaphore_mask; 672 673 DEBUGFUNC("ixgbe_read_phy_reg_generic"); 674 675 if (hw->mac.ops.acquire_swfw_sync(hw, gssr)) 676 return IXGBE_ERR_SWFW_SYNC; 677 678 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data); 679 680 hw->mac.ops.release_swfw_sync(hw, gssr); 681 682 return status; 683 } 684 685 /** 686 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register 687 * without SWFW lock 688 * @hw: pointer to hardware structure 689 * @reg_addr: 32 bit PHY register to write 690 * @device_type: 5 bit device type 691 * @phy_data: Data to write to the PHY register 692 **/ 693 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, 694 u32 device_type, u16 phy_data) 695 { 696 u32 i, command; 697 698 /* Put the data in the MDI single read and write data register*/ 699 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 700 701 /* Setup and write the address cycle command */ 702 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 703 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 704 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 705 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 706 707 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 708 709 /* 710 * Check every 10 usec to see if the address cycle completed. 711 * The MDI Command bit will clear when the operation is 712 * complete 713 */ 714 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 715 usec_delay(10); 716 717 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 718 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 719 break; 720 } 721 722 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 723 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n"); 724 return IXGBE_ERR_PHY; 725 } 726 727 /* 728 * Address cycle complete, setup and write the write 729 * command 730 */ 731 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 732 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 733 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 734 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 735 736 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 737 738 /* 739 * Check every 10 usec to see if the address cycle 740 * completed. The MDI Command bit will clear when the 741 * operation is complete 742 */ 743 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 744 usec_delay(10); 745 746 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 747 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 748 break; 749 } 750 751 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 752 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n"); 753 return IXGBE_ERR_PHY; 754 } 755 756 return IXGBE_SUCCESS; 757 } 758 759 /** 760 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 761 * using SWFW lock- this function is needed in most cases 762 * @hw: pointer to hardware structure 763 * @reg_addr: 32 bit PHY register to write 764 * @device_type: 5 bit device type 765 * @phy_data: Data to write to the PHY register 766 **/ 767 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 768 u32 device_type, u16 phy_data) 769 { 770 s32 status; 771 u32 gssr = hw->phy.phy_semaphore_mask; 772 773 DEBUGFUNC("ixgbe_write_phy_reg_generic"); 774 775 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) { 776 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type, 777 phy_data); 778 hw->mac.ops.release_swfw_sync(hw, gssr); 779 } else { 780 status = IXGBE_ERR_SWFW_SYNC; 781 } 782 783 return status; 784 } 785 786 /** 787 * ixgbe_setup_phy_link_generic - Set and restart auto-neg 788 * @hw: pointer to hardware structure 789 * 790 * Restart auto-negotiation and PHY and waits for completion. 791 **/ 792 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 793 { 794 s32 status = IXGBE_SUCCESS; 795 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 796 bool autoneg = FALSE; 797 ixgbe_link_speed speed; 798 799 DEBUGFUNC("ixgbe_setup_phy_link_generic"); 800 801 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 802 803 /* Set or unset auto-negotiation 10G advertisement */ 804 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 805 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 806 &autoneg_reg); 807 808 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 809 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) && 810 (speed & IXGBE_LINK_SPEED_10GB_FULL)) 811 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 812 813 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 814 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 815 autoneg_reg); 816 817 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 818 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 819 &autoneg_reg); 820 821 if (hw->mac.type == ixgbe_mac_X550) { 822 /* Set or unset auto-negotiation 5G advertisement */ 823 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE; 824 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) && 825 (speed & IXGBE_LINK_SPEED_5GB_FULL)) 826 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE; 827 828 /* Set or unset auto-negotiation 2.5G advertisement */ 829 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE; 830 if ((hw->phy.autoneg_advertised & 831 IXGBE_LINK_SPEED_2_5GB_FULL) && 832 (speed & IXGBE_LINK_SPEED_2_5GB_FULL)) 833 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE; 834 } 835 836 /* Set or unset auto-negotiation 1G advertisement */ 837 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; 838 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) && 839 (speed & IXGBE_LINK_SPEED_1GB_FULL)) 840 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; 841 842 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 843 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 844 autoneg_reg); 845 846 /* Set or unset auto-negotiation 100M advertisement */ 847 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 848 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 849 &autoneg_reg); 850 851 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE | 852 IXGBE_MII_100BASE_T_ADVERTISE_HALF); 853 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) && 854 (speed & IXGBE_LINK_SPEED_100_FULL)) 855 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 856 857 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 858 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 859 autoneg_reg); 860 861 if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_100_FULL) { 862 u16 ctrl; 863 864 /* Force 100Mbps */ 865 hw->phy.ops.read_reg(hw, MDIO_PMAPMD_CTRL1, MDIO_MMD_PMAPMD, 866 &ctrl); 867 ctrl &= ~PMAPMD_CTRL1_SPEED_MASK; 868 ctrl |= PMAPMD_CTRL1_SPEED_100; 869 hw->phy.ops.write_reg(hw, MDIO_PMAPMD_CTRL1,MDIO_MMD_PMAPMD, 870 ctrl); 871 872 /* Don't use auto-nego for 100Mbps */ 873 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 874 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 875 876 autoneg_reg &= ~AN_CTRL1_AUTOEN; 877 878 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 879 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 880 } else { 881 /* Blocked by MNG FW so don't reset PHY */ 882 if (ixgbe_check_reset_blocked(hw)) 883 return status; 884 885 /* Restart PHY auto-negotiation. */ 886 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 887 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 888 889 autoneg_reg |= IXGBE_MII_RESTART | AN_CTRL1_AUTOEN; 890 891 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 892 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 893 } 894 895 return status; 896 } 897 898 /** 899 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 900 * @hw: pointer to hardware structure 901 * @speed: new link speed 902 * @autoneg_wait_to_complete: unused 903 **/ 904 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 905 ixgbe_link_speed speed, 906 bool autoneg_wait_to_complete) 907 { 908 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete); 909 910 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic"); 911 912 /* 913 * Clear autoneg_advertised and set new values based on input link 914 * speed. 915 */ 916 hw->phy.autoneg_advertised = 0; 917 918 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 919 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 920 921 if (speed & IXGBE_LINK_SPEED_5GB_FULL) 922 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL; 923 924 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) 925 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL; 926 927 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 928 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 929 930 if (speed & IXGBE_LINK_SPEED_100_FULL) 931 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 932 933 if (speed & IXGBE_LINK_SPEED_10_FULL) 934 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL; 935 936 /* Setup link based on the new speed settings */ 937 ixgbe_setup_phy_link(hw); 938 939 return IXGBE_SUCCESS; 940 } 941 942 /** 943 * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy 944 * @hw: pointer to hardware structure 945 * 946 * Determines the supported link capabilities by reading the PHY auto 947 * negotiation register. 948 **/ 949 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw) 950 { 951 s32 status; 952 u16 speed_ability; 953 954 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 955 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 956 &speed_ability); 957 if (status) 958 return status; 959 960 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 961 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL; 962 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) 963 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL; 964 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M) 965 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL; 966 967 switch (hw->mac.type) { 968 case ixgbe_mac_X550: 969 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL; 970 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL; 971 break; 972 case ixgbe_mac_X550EM_x: 973 case ixgbe_mac_X550EM_a: 974 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL; 975 break; 976 default: 977 break; 978 } 979 980 return status; 981 } 982 983 /** 984 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 985 * @hw: pointer to hardware structure 986 * @speed: pointer to link speed 987 * @autoneg: boolean auto-negotiation value 988 **/ 989 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 990 ixgbe_link_speed *speed, 991 bool *autoneg) 992 { 993 s32 status = IXGBE_SUCCESS; 994 995 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic"); 996 997 *autoneg = TRUE; 998 if (!hw->phy.speeds_supported) 999 status = ixgbe_get_copper_speeds_supported(hw); 1000 1001 *speed = hw->phy.speeds_supported; 1002 return status; 1003 } 1004 1005 /** 1006 * ixgbe_check_phy_link_tnx - Determine link and speed status 1007 * @hw: pointer to hardware structure 1008 * @speed: current link speed 1009 * @link_up: TRUE is link is up, FALSE otherwise 1010 * 1011 * Reads the VS1 register to determine if link is up and the current speed for 1012 * the PHY. 1013 **/ 1014 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 1015 bool *link_up) 1016 { 1017 s32 status = IXGBE_SUCCESS; 1018 u32 time_out; 1019 u32 max_time_out = 10; 1020 u16 phy_link = 0; 1021 u16 phy_speed = 0; 1022 u16 phy_data = 0; 1023 1024 DEBUGFUNC("ixgbe_check_phy_link_tnx"); 1025 1026 /* Initialize speed and link to default case */ 1027 *link_up = FALSE; 1028 *speed = IXGBE_LINK_SPEED_10GB_FULL; 1029 1030 /* 1031 * Check current speed and link status of the PHY register. 1032 * This is a vendor specific register and may have to 1033 * be changed for other copper PHYs. 1034 */ 1035 for (time_out = 0; time_out < max_time_out; time_out++) { 1036 usec_delay(10); 1037 status = hw->phy.ops.read_reg(hw, 1038 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, 1039 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1040 &phy_data); 1041 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 1042 phy_speed = phy_data & 1043 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 1044 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 1045 *link_up = TRUE; 1046 if (phy_speed == 1047 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 1048 *speed = IXGBE_LINK_SPEED_1GB_FULL; 1049 break; 1050 } 1051 } 1052 1053 return status; 1054 } 1055 1056 /** 1057 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg 1058 * @hw: pointer to hardware structure 1059 * 1060 * Restart auto-negotiation and PHY and waits for completion. 1061 **/ 1062 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) 1063 { 1064 s32 status = IXGBE_SUCCESS; 1065 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 1066 bool autoneg = FALSE; 1067 ixgbe_link_speed speed; 1068 1069 DEBUGFUNC("ixgbe_setup_phy_link_tnx"); 1070 1071 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 1072 1073 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 1074 /* Set or unset auto-negotiation 10G advertisement */ 1075 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1076 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1077 &autoneg_reg); 1078 1079 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 1080 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 1081 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 1082 1083 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1084 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1085 autoneg_reg); 1086 } 1087 1088 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 1089 /* Set or unset auto-negotiation 1G advertisement */ 1090 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1091 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1092 &autoneg_reg); 1093 1094 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1095 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 1096 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1097 1098 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1099 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1100 autoneg_reg); 1101 } 1102 1103 if (speed & IXGBE_LINK_SPEED_100_FULL) { 1104 /* Set or unset auto-negotiation 100M advertisement */ 1105 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1106 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1107 &autoneg_reg); 1108 1109 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; 1110 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 1111 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 1112 1113 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1114 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1115 autoneg_reg); 1116 } 1117 1118 /* Blocked by MNG FW so don't reset PHY */ 1119 if (ixgbe_check_reset_blocked(hw)) 1120 return status; 1121 1122 /* Restart PHY auto-negotiation. */ 1123 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 1124 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 1125 1126 autoneg_reg |= IXGBE_MII_RESTART; 1127 1128 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 1129 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 1130 1131 return status; 1132 } 1133 1134 /** 1135 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 1136 * @hw: pointer to hardware structure 1137 * @firmware_version: pointer to the PHY Firmware Version 1138 **/ 1139 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 1140 u16 *firmware_version) 1141 { 1142 s32 status; 1143 1144 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx"); 1145 1146 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 1147 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1148 firmware_version); 1149 1150 return status; 1151 } 1152 1153 /** 1154 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version 1155 * @hw: pointer to hardware structure 1156 * @firmware_version: pointer to the PHY Firmware Version 1157 **/ 1158 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 1159 u16 *firmware_version) 1160 { 1161 s32 status; 1162 1163 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic"); 1164 1165 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, 1166 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1167 firmware_version); 1168 1169 return status; 1170 } 1171 1172 /** 1173 * ixgbe_reset_phy_nl - Performs a PHY reset 1174 * @hw: pointer to hardware structure 1175 **/ 1176 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 1177 { 1178 u16 phy_offset, control, eword, edata, block_crc; 1179 bool end_data = FALSE; 1180 u16 list_offset, data_offset; 1181 u16 phy_data = 0; 1182 s32 ret_val = IXGBE_SUCCESS; 1183 u32 i; 1184 1185 DEBUGFUNC("ixgbe_reset_phy_nl"); 1186 1187 /* Blocked by MNG FW so bail */ 1188 if (ixgbe_check_reset_blocked(hw)) 1189 goto out; 1190 1191 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1192 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1193 1194 /* reset the PHY and poll for completion */ 1195 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1196 IXGBE_MDIO_PHY_XS_DEV_TYPE, 1197 (phy_data | IXGBE_MDIO_PHY_XS_RESET)); 1198 1199 for (i = 0; i < 100; i++) { 1200 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1201 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1202 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) 1203 break; 1204 msec_delay(10); 1205 } 1206 1207 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { 1208 DEBUGOUT("PHY reset did not complete.\n"); 1209 ret_val = IXGBE_ERR_PHY; 1210 goto out; 1211 } 1212 1213 /* Get init offsets */ 1214 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 1215 &data_offset); 1216 if (ret_val != IXGBE_SUCCESS) 1217 goto out; 1218 1219 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 1220 data_offset++; 1221 while (!end_data) { 1222 /* 1223 * Read control word from PHY init contents offset 1224 */ 1225 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 1226 if (ret_val) 1227 goto err_eeprom; 1228 control = (eword & IXGBE_CONTROL_MASK_NL) >> 1229 IXGBE_CONTROL_SHIFT_NL; 1230 edata = eword & IXGBE_DATA_MASK_NL; 1231 switch (control) { 1232 case IXGBE_DELAY_NL: 1233 data_offset++; 1234 DEBUGOUT1("DELAY: %d MS\n", edata); 1235 msec_delay(edata); 1236 break; 1237 case IXGBE_DATA_NL: 1238 DEBUGOUT("DATA:\n"); 1239 data_offset++; 1240 ret_val = hw->eeprom.ops.read(hw, data_offset, 1241 &phy_offset); 1242 if (ret_val) 1243 goto err_eeprom; 1244 data_offset++; 1245 for (i = 0; i < edata; i++) { 1246 ret_val = hw->eeprom.ops.read(hw, data_offset, 1247 &eword); 1248 if (ret_val) 1249 goto err_eeprom; 1250 hw->phy.ops.write_reg(hw, phy_offset, 1251 IXGBE_TWINAX_DEV, eword); 1252 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword, 1253 phy_offset); 1254 data_offset++; 1255 phy_offset++; 1256 } 1257 break; 1258 case IXGBE_CONTROL_NL: 1259 data_offset++; 1260 DEBUGOUT("CONTROL:\n"); 1261 if (edata == IXGBE_CONTROL_EOL_NL) { 1262 DEBUGOUT("EOL\n"); 1263 end_data = TRUE; 1264 } else if (edata == IXGBE_CONTROL_SOL_NL) { 1265 DEBUGOUT("SOL\n"); 1266 } else { 1267 DEBUGOUT("Bad control value\n"); 1268 ret_val = IXGBE_ERR_PHY; 1269 goto out; 1270 } 1271 break; 1272 default: 1273 DEBUGOUT("Bad control type\n"); 1274 ret_val = IXGBE_ERR_PHY; 1275 goto out; 1276 } 1277 } 1278 1279 out: 1280 return ret_val; 1281 1282 err_eeprom: 1283 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1284 "eeprom read at offset %d failed", data_offset); 1285 return IXGBE_ERR_PHY; 1286 } 1287 1288 /************************************************************************ 1289 * ixgbe_sfp_cage_full 1290 * 1291 * Determine if an SFP+ module is inserted to the cage. 1292 ************************************************************************/ 1293 bool 1294 ixgbe_sfp_cage_full(struct ixgbe_hw *hw) 1295 { 1296 uint32_t mask; 1297 int rv; 1298 1299 KASSERT(hw->mac.type != ixgbe_mac_82598EB); 1300 1301 if (hw->mac.type >= ixgbe_mac_X540) 1302 mask = IXGBE_ESDP_SDP0; 1303 else 1304 mask = IXGBE_ESDP_SDP2; 1305 1306 rv = IXGBE_READ_REG(hw, IXGBE_ESDP) & mask; 1307 if ((hw->quirks & IXGBE_QUIRK_MOD_ABS_INVERT) != 0) 1308 rv = !rv; 1309 1310 if (hw->mac.type == ixgbe_mac_X550EM_a) { 1311 /* X550EM_a's SDP0 is inverted than others. */ 1312 return !rv; 1313 } 1314 1315 return rv; 1316 } /* ixgbe_sfp_cage_full */ 1317 1318 /** 1319 * ixgbe_identify_module_generic - Identifies module type 1320 * @hw: pointer to hardware structure 1321 * 1322 * Determines HW type and calls appropriate function. 1323 **/ 1324 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw) 1325 { 1326 s32 status = IXGBE_ERR_SFP_NOT_PRESENT; 1327 1328 DEBUGFUNC("ixgbe_identify_module_generic"); 1329 1330 /* Lightweight way to check if the cage is not full. */ 1331 if (hw->mac.type != ixgbe_mac_82598EB) { 1332 if (!ixgbe_sfp_cage_full(hw)) { 1333 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1334 return IXGBE_ERR_SFP_NOT_PRESENT; 1335 } 1336 } 1337 1338 switch (hw->mac.ops.get_media_type(hw)) { 1339 case ixgbe_media_type_fiber: 1340 status = ixgbe_identify_sfp_module_generic(hw); 1341 break; 1342 1343 case ixgbe_media_type_fiber_qsfp: 1344 status = ixgbe_identify_qsfp_module_generic(hw); 1345 break; 1346 1347 default: 1348 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1349 status = IXGBE_ERR_SFP_NOT_PRESENT; 1350 break; 1351 } 1352 1353 return status; 1354 } 1355 1356 /** 1357 * ixgbe_identify_sfp_module_generic - Identifies SFP modules 1358 * @hw: pointer to hardware structure 1359 * 1360 * Searches for and identifies the SFP module and assigns appropriate PHY type. 1361 **/ 1362 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 1363 { 1364 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1365 u32 vendor_oui = 0; 1366 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1367 u8 identifier = 0; 1368 u8 comp_codes_1g = 0; 1369 u8 comp_codes_10g = 0; 1370 u8 oui_bytes[3] = {0, 0, 0}; 1371 u8 cable_tech = 0; 1372 u8 cable_spec = 0; 1373 u16 enforce_sfp = 0; 1374 1375 DEBUGFUNC("ixgbe_identify_sfp_module_generic"); 1376 1377 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 1378 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1379 status = IXGBE_ERR_SFP_NOT_PRESENT; 1380 goto out; 1381 } 1382 1383 /* LAN ID is needed for I2C access */ 1384 hw->mac.ops.set_lan_id(hw); 1385 1386 status = hw->phy.ops.read_i2c_eeprom(hw, 1387 IXGBE_SFF_IDENTIFIER, 1388 &identifier); 1389 1390 if (status != IXGBE_SUCCESS) 1391 goto err_read_i2c_eeprom; 1392 1393 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 1394 if (hw->phy.type != ixgbe_phy_nl) 1395 hw->phy.type = ixgbe_phy_sfp_unsupported; 1396 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1397 } else { 1398 status = hw->phy.ops.read_i2c_eeprom(hw, 1399 IXGBE_SFF_1GBE_COMP_CODES, 1400 &comp_codes_1g); 1401 1402 if (status != IXGBE_SUCCESS) 1403 goto err_read_i2c_eeprom; 1404 1405 status = hw->phy.ops.read_i2c_eeprom(hw, 1406 IXGBE_SFF_10GBE_COMP_CODES, 1407 &comp_codes_10g); 1408 1409 if (status != IXGBE_SUCCESS) 1410 goto err_read_i2c_eeprom; 1411 status = hw->phy.ops.read_i2c_eeprom(hw, 1412 IXGBE_SFF_CABLE_TECHNOLOGY, 1413 &cable_tech); 1414 1415 if (status != IXGBE_SUCCESS) 1416 goto err_read_i2c_eeprom; 1417 1418 /* ID Module 1419 * ========= 1420 * 0 SFP_DA_CU 1421 * 1 SFP_SR 1422 * 2 SFP_LR 1423 * 3 SFP_DA_CORE0 - 82599-specific 1424 * 4 SFP_DA_CORE1 - 82599-specific 1425 * 5 SFP_SR/LR_CORE0 - 82599-specific 1426 * 6 SFP_SR/LR_CORE1 - 82599-specific 1427 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific 1428 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific 1429 * 9 SFP_1g_cu_CORE0 - 82599-specific 1430 * 10 SFP_1g_cu_CORE1 - 82599-specific 1431 * 11 SFP_1g_sx_CORE0 - 82599-specific 1432 * 12 SFP_1g_sx_CORE1 - 82599-specific 1433 */ 1434 if (hw->mac.type == ixgbe_mac_82598EB) { 1435 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1436 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 1437 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1438 hw->phy.sfp_type = ixgbe_sfp_type_sr; 1439 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1440 hw->phy.sfp_type = ixgbe_sfp_type_lr; 1441 else 1442 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1443 } else { 1444 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 1445 if (hw->bus.lan_id == 0) 1446 hw->phy.sfp_type = 1447 ixgbe_sfp_type_da_cu_core0; 1448 else 1449 hw->phy.sfp_type = 1450 ixgbe_sfp_type_da_cu_core1; 1451 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { 1452 hw->phy.ops.read_i2c_eeprom( 1453 hw, IXGBE_SFF_CABLE_SPEC_COMP, 1454 &cable_spec); 1455 if (cable_spec & 1456 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { 1457 if (hw->bus.lan_id == 0) 1458 hw->phy.sfp_type = 1459 ixgbe_sfp_type_da_act_lmt_core0; 1460 else 1461 hw->phy.sfp_type = 1462 ixgbe_sfp_type_da_act_lmt_core1; 1463 } else { 1464 hw->phy.sfp_type = 1465 ixgbe_sfp_type_unknown; 1466 } 1467 } else if (comp_codes_10g & 1468 (IXGBE_SFF_10GBASESR_CAPABLE | 1469 IXGBE_SFF_10GBASELR_CAPABLE)) { 1470 if (hw->bus.lan_id == 0) 1471 hw->phy.sfp_type = 1472 ixgbe_sfp_type_srlr_core0; 1473 else 1474 hw->phy.sfp_type = 1475 ixgbe_sfp_type_srlr_core1; 1476 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { 1477 if (hw->bus.lan_id == 0) 1478 hw->phy.sfp_type = 1479 ixgbe_sfp_type_1g_cu_core0; 1480 else 1481 hw->phy.sfp_type = 1482 ixgbe_sfp_type_1g_cu_core1; 1483 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) { 1484 if (hw->bus.lan_id == 0) 1485 hw->phy.sfp_type = 1486 ixgbe_sfp_type_1g_sx_core0; 1487 else 1488 hw->phy.sfp_type = 1489 ixgbe_sfp_type_1g_sx_core1; 1490 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) { 1491 if (hw->bus.lan_id == 0) 1492 hw->phy.sfp_type = 1493 ixgbe_sfp_type_1g_lx_core0; 1494 else 1495 hw->phy.sfp_type = 1496 ixgbe_sfp_type_1g_lx_core1; 1497 } else { 1498 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1499 } 1500 } 1501 1502 if (hw->phy.sfp_type != stored_sfp_type) 1503 hw->phy.sfp_setup_needed = TRUE; 1504 1505 /* Determine if the SFP+ PHY is dual speed or not. */ 1506 hw->phy.multispeed_fiber = FALSE; 1507 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1508 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1509 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1510 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1511 hw->phy.multispeed_fiber = TRUE; 1512 1513 /* Determine PHY vendor */ 1514 if (hw->phy.type != ixgbe_phy_nl) { 1515 hw->phy.id = identifier; 1516 status = hw->phy.ops.read_i2c_eeprom(hw, 1517 IXGBE_SFF_VENDOR_OUI_BYTE0, 1518 &oui_bytes[0]); 1519 1520 if (status != IXGBE_SUCCESS) 1521 goto err_read_i2c_eeprom; 1522 1523 status = hw->phy.ops.read_i2c_eeprom(hw, 1524 IXGBE_SFF_VENDOR_OUI_BYTE1, 1525 &oui_bytes[1]); 1526 1527 if (status != IXGBE_SUCCESS) 1528 goto err_read_i2c_eeprom; 1529 1530 status = hw->phy.ops.read_i2c_eeprom(hw, 1531 IXGBE_SFF_VENDOR_OUI_BYTE2, 1532 &oui_bytes[2]); 1533 1534 if (status != IXGBE_SUCCESS) 1535 goto err_read_i2c_eeprom; 1536 1537 vendor_oui = 1538 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1539 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1540 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1541 1542 switch (vendor_oui) { 1543 case IXGBE_SFF_VENDOR_OUI_TYCO: 1544 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1545 hw->phy.type = 1546 ixgbe_phy_sfp_passive_tyco; 1547 break; 1548 case IXGBE_SFF_VENDOR_OUI_FTL: 1549 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1550 hw->phy.type = ixgbe_phy_sfp_ftl_active; 1551 else 1552 hw->phy.type = ixgbe_phy_sfp_ftl; 1553 break; 1554 case IXGBE_SFF_VENDOR_OUI_AVAGO: 1555 hw->phy.type = ixgbe_phy_sfp_avago; 1556 break; 1557 case IXGBE_SFF_VENDOR_OUI_INTEL: 1558 hw->phy.type = ixgbe_phy_sfp_intel; 1559 break; 1560 default: 1561 hw->phy.type = ixgbe_phy_sfp_unknown; 1562 break; 1563 } 1564 } 1565 1566 /* Allow any DA cable vendor */ 1567 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 1568 IXGBE_SFF_DA_ACTIVE_CABLE)) { 1569 status = IXGBE_SUCCESS; 1570 1571 /* Keep phy.type for ixgbe_phy_nl */ 1572 if (hw->phy.type == ixgbe_phy_nl) 1573 goto out; 1574 1575 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1576 hw->phy.type = ixgbe_phy_sfp_passive_unknown; 1577 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1578 hw->phy.type = ixgbe_phy_sfp_active_unknown; 1579 goto out; 1580 } 1581 1582 /* Verify supported 1G SFP modules */ 1583 if (comp_codes_10g == 0 && 1584 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1585 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1586 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1587 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1588 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1589 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1590 if (hw->phy.type != ixgbe_phy_nl) 1591 hw->phy.type = ixgbe_phy_sfp_unsupported; 1592 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1593 goto out; 1594 } 1595 1596 /* Anything else 82598-based is supported */ 1597 if (hw->mac.type == ixgbe_mac_82598EB) { 1598 status = IXGBE_SUCCESS; 1599 goto out; 1600 } 1601 1602 ixgbe_get_device_caps(hw, &enforce_sfp); 1603 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && 1604 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1605 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1606 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1607 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1608 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1609 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1610 /* Make sure we're a supported PHY type */ 1611 if (hw->phy.type == ixgbe_phy_sfp_intel) { 1612 status = IXGBE_SUCCESS; 1613 } else { 1614 if (hw->allow_unsupported_sfp == TRUE) { 1615 EWARN(hw, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n"); 1616 status = IXGBE_SUCCESS; 1617 } else { 1618 DEBUGOUT("SFP+ module not supported\n"); 1619 if (hw->phy.type != ixgbe_phy_nl) 1620 hw->phy.type = 1621 ixgbe_phy_sfp_unsupported; 1622 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1623 } 1624 } 1625 } else { 1626 status = IXGBE_SUCCESS; 1627 } 1628 } 1629 1630 out: 1631 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 1632 hw->need_unsupported_sfp_recovery = true; 1633 return status; 1634 1635 err_read_i2c_eeprom: 1636 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1637 if (hw->phy.type != ixgbe_phy_nl) { 1638 hw->phy.id = 0; 1639 hw->phy.type = ixgbe_phy_unknown; 1640 } 1641 return IXGBE_ERR_SFP_NOT_PRESENT; 1642 } 1643 1644 /** 1645 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type 1646 * @hw: pointer to hardware structure 1647 * 1648 * Determines physical layer capabilities of the current SFP. 1649 */ 1650 u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw) 1651 { 1652 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1653 u8 comp_codes_10g = 0; 1654 u8 comp_codes_1g = 0; 1655 1656 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic"); 1657 1658 hw->phy.ops.identify_sfp(hw); 1659 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1660 return physical_layer; 1661 1662 switch (hw->phy.type) { 1663 case ixgbe_phy_sfp_passive_tyco: 1664 case ixgbe_phy_sfp_passive_unknown: 1665 case ixgbe_phy_qsfp_passive_unknown: 1666 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1667 break; 1668 case ixgbe_phy_sfp_ftl_active: 1669 case ixgbe_phy_sfp_active_unknown: 1670 case ixgbe_phy_qsfp_active_unknown: 1671 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA; 1672 break; 1673 case ixgbe_phy_sfp_avago: 1674 case ixgbe_phy_sfp_ftl: 1675 case ixgbe_phy_sfp_intel: 1676 case ixgbe_phy_sfp_unknown: 1677 hw->phy.ops.read_i2c_eeprom(hw, 1678 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g); 1679 hw->phy.ops.read_i2c_eeprom(hw, 1680 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g); 1681 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1682 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1683 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1684 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1685 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) 1686 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T; 1687 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) 1688 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX; 1689 break; 1690 case ixgbe_phy_qsfp_intel: 1691 case ixgbe_phy_qsfp_unknown: 1692 hw->phy.ops.read_i2c_eeprom(hw, 1693 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g); 1694 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1695 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1696 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1697 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1698 break; 1699 default: 1700 break; 1701 } 1702 1703 return physical_layer; 1704 } 1705 1706 /** 1707 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules 1708 * @hw: pointer to hardware structure 1709 * 1710 * Searches for and identifies the QSFP module and assigns appropriate PHY type 1711 **/ 1712 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw) 1713 { 1714 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1715 u32 vendor_oui = 0; 1716 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1717 u8 identifier = 0; 1718 u8 comp_codes_1g = 0; 1719 u8 comp_codes_10g = 0; 1720 u8 oui_bytes[3] = {0, 0, 0}; 1721 u16 enforce_sfp = 0; 1722 u8 connector = 0; 1723 u8 cable_length = 0; 1724 u8 device_tech = 0; 1725 bool active_cable = FALSE; 1726 1727 DEBUGFUNC("ixgbe_identify_qsfp_module_generic"); 1728 1729 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) { 1730 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1731 status = IXGBE_ERR_SFP_NOT_PRESENT; 1732 goto out; 1733 } 1734 1735 /* LAN ID is needed for I2C access */ 1736 hw->mac.ops.set_lan_id(hw); 1737 1738 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, 1739 &identifier); 1740 1741 if (status != IXGBE_SUCCESS) 1742 goto err_read_i2c_eeprom; 1743 1744 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) { 1745 hw->phy.type = ixgbe_phy_sfp_unsupported; 1746 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1747 goto out; 1748 } 1749 1750 hw->phy.id = identifier; 1751 1752 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP, 1753 &comp_codes_10g); 1754 1755 if (status != IXGBE_SUCCESS) 1756 goto err_read_i2c_eeprom; 1757 1758 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP, 1759 &comp_codes_1g); 1760 1761 if (status != IXGBE_SUCCESS) 1762 goto err_read_i2c_eeprom; 1763 1764 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) { 1765 hw->phy.type = ixgbe_phy_qsfp_passive_unknown; 1766 if (hw->bus.lan_id == 0) 1767 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0; 1768 else 1769 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1; 1770 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1771 IXGBE_SFF_10GBASELR_CAPABLE)) { 1772 if (hw->bus.lan_id == 0) 1773 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0; 1774 else 1775 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1; 1776 } else { 1777 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE) 1778 active_cable = TRUE; 1779 1780 if (!active_cable) { 1781 /* check for active DA cables that pre-date 1782 * SFF-8436 v3.6 */ 1783 hw->phy.ops.read_i2c_eeprom(hw, 1784 IXGBE_SFF_QSFP_CONNECTOR, 1785 &connector); 1786 1787 hw->phy.ops.read_i2c_eeprom(hw, 1788 IXGBE_SFF_QSFP_CABLE_LENGTH, 1789 &cable_length); 1790 1791 hw->phy.ops.read_i2c_eeprom(hw, 1792 IXGBE_SFF_QSFP_DEVICE_TECH, 1793 &device_tech); 1794 1795 if ((connector == 1796 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) && 1797 (cable_length > 0) && 1798 ((device_tech >> 4) == 1799 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL)) 1800 active_cable = TRUE; 1801 } 1802 1803 if (active_cable) { 1804 hw->phy.type = ixgbe_phy_qsfp_active_unknown; 1805 if (hw->bus.lan_id == 0) 1806 hw->phy.sfp_type = 1807 ixgbe_sfp_type_da_act_lmt_core0; 1808 else 1809 hw->phy.sfp_type = 1810 ixgbe_sfp_type_da_act_lmt_core1; 1811 } else { 1812 /* unsupported module type */ 1813 hw->phy.type = ixgbe_phy_sfp_unsupported; 1814 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1815 goto out; 1816 } 1817 } 1818 1819 if (hw->phy.sfp_type != stored_sfp_type) 1820 hw->phy.sfp_setup_needed = TRUE; 1821 1822 /* Determine if the QSFP+ PHY is dual speed or not. */ 1823 hw->phy.multispeed_fiber = FALSE; 1824 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1825 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1826 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1827 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1828 hw->phy.multispeed_fiber = TRUE; 1829 1830 /* Determine PHY vendor for optical modules */ 1831 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1832 IXGBE_SFF_10GBASELR_CAPABLE)) { 1833 status = hw->phy.ops.read_i2c_eeprom(hw, 1834 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0, 1835 &oui_bytes[0]); 1836 1837 if (status != IXGBE_SUCCESS) 1838 goto err_read_i2c_eeprom; 1839 1840 status = hw->phy.ops.read_i2c_eeprom(hw, 1841 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1, 1842 &oui_bytes[1]); 1843 1844 if (status != IXGBE_SUCCESS) 1845 goto err_read_i2c_eeprom; 1846 1847 status = hw->phy.ops.read_i2c_eeprom(hw, 1848 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2, 1849 &oui_bytes[2]); 1850 1851 if (status != IXGBE_SUCCESS) 1852 goto err_read_i2c_eeprom; 1853 1854 vendor_oui = 1855 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1856 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1857 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1858 1859 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL) 1860 hw->phy.type = ixgbe_phy_qsfp_intel; 1861 else 1862 hw->phy.type = ixgbe_phy_qsfp_unknown; 1863 1864 ixgbe_get_device_caps(hw, &enforce_sfp); 1865 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) { 1866 /* Make sure we're a supported PHY type */ 1867 if (hw->phy.type == ixgbe_phy_qsfp_intel) { 1868 status = IXGBE_SUCCESS; 1869 } else { 1870 if (hw->allow_unsupported_sfp == TRUE) { 1871 EWARN(hw, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n"); 1872 status = IXGBE_SUCCESS; 1873 } else { 1874 DEBUGOUT("QSFP module not supported\n"); 1875 hw->phy.type = 1876 ixgbe_phy_sfp_unsupported; 1877 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1878 } 1879 } 1880 } else { 1881 status = IXGBE_SUCCESS; 1882 } 1883 } 1884 1885 out: 1886 if (hw->phy.type == ixgbe_phy_sfp_unsupported) 1887 hw->need_unsupported_sfp_recovery = true; 1888 return status; 1889 1890 err_read_i2c_eeprom: 1891 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1892 hw->phy.id = 0; 1893 hw->phy.type = ixgbe_phy_unknown; 1894 1895 return IXGBE_ERR_SFP_NOT_PRESENT; 1896 } 1897 1898 /** 1899 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 1900 * @hw: pointer to hardware structure 1901 * @list_offset: offset to the SFP ID list 1902 * @data_offset: offset to the SFP data block 1903 * 1904 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 1905 * so it returns the offsets to the phy init sequence block. 1906 **/ 1907 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 1908 u16 *list_offset, 1909 u16 *data_offset) 1910 { 1911 u16 sfp_id; 1912 u16 sfp_type = hw->phy.sfp_type; 1913 1914 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets"); 1915 1916 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 1917 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1918 1919 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1920 return IXGBE_ERR_SFP_NOT_PRESENT; 1921 1922 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 1923 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 1924 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1925 1926 /* 1927 * Limiting active cables and 1G Phys must be initialized as 1928 * SR modules 1929 */ 1930 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 || 1931 sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1932 sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1933 sfp_type == ixgbe_sfp_type_1g_sx_core0) 1934 sfp_type = ixgbe_sfp_type_srlr_core0; 1935 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 || 1936 sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1937 sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1938 sfp_type == ixgbe_sfp_type_1g_sx_core1) 1939 sfp_type = ixgbe_sfp_type_srlr_core1; 1940 1941 /* Read offset to PHY init contents */ 1942 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) { 1943 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1944 "eeprom read at offset %d failed", 1945 IXGBE_PHY_INIT_OFFSET_NL); 1946 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1947 } 1948 1949 if ((!*list_offset) || (*list_offset == 0xFFFF)) 1950 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1951 1952 /* Shift offset to first ID word */ 1953 (*list_offset)++; 1954 1955 /* 1956 * Find the matching SFP ID in the EEPROM 1957 * and program the init sequence 1958 */ 1959 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1960 goto err_phy; 1961 1962 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 1963 if (sfp_id == sfp_type) { 1964 (*list_offset)++; 1965 if (hw->eeprom.ops.read(hw, *list_offset, data_offset)) 1966 goto err_phy; 1967 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 1968 DEBUGOUT("SFP+ module not supported\n"); 1969 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1970 } else { 1971 break; 1972 } 1973 } else { 1974 (*list_offset) += 2; 1975 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1976 goto err_phy; 1977 } 1978 } 1979 1980 if (sfp_id == IXGBE_PHY_INIT_END_NL) { 1981 DEBUGOUT("No matching SFP+ module found\n"); 1982 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1983 } 1984 1985 return IXGBE_SUCCESS; 1986 1987 err_phy: 1988 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1989 "eeprom read at offset %d failed", *list_offset); 1990 return IXGBE_ERR_PHY; 1991 } 1992 1993 /** 1994 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 1995 * @hw: pointer to hardware structure 1996 * @byte_offset: EEPROM byte offset to read 1997 * @eeprom_data: value read 1998 * 1999 * Performs byte read operation to SFP module's EEPROM over I2C interface. 2000 **/ 2001 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 2002 u8 *eeprom_data) 2003 { 2004 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic"); 2005 2006 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 2007 IXGBE_I2C_EEPROM_DEV_ADDR, 2008 eeprom_data); 2009 } 2010 2011 /** 2012 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface 2013 * @hw: pointer to hardware structure 2014 * @byte_offset: byte offset at address 0xA2 2015 * @sff8472_data: value read 2016 * 2017 * Performs byte read operation to SFP module's SFF-8472 data over I2C 2018 **/ 2019 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 2020 u8 *sff8472_data) 2021 { 2022 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 2023 IXGBE_I2C_EEPROM_DEV_ADDR2, 2024 sff8472_data); 2025 } 2026 2027 /** 2028 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 2029 * @hw: pointer to hardware structure 2030 * @byte_offset: EEPROM byte offset to write 2031 * @eeprom_data: value to write 2032 * 2033 * Performs byte write operation to SFP module's EEPROM over I2C interface. 2034 **/ 2035 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 2036 u8 eeprom_data) 2037 { 2038 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic"); 2039 2040 return hw->phy.ops.write_i2c_byte(hw, byte_offset, 2041 IXGBE_I2C_EEPROM_DEV_ADDR, 2042 eeprom_data); 2043 } 2044 2045 /** 2046 * ixgbe_is_sfp_probe - Returns TRUE if SFP is being detected 2047 * @hw: pointer to hardware structure 2048 * @offset: eeprom offset to be read 2049 * @addr: I2C address to be read 2050 */ 2051 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr) 2052 { 2053 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR && 2054 offset == IXGBE_SFF_IDENTIFIER && 2055 hw->phy.sfp_type == ixgbe_sfp_type_not_present) 2056 return TRUE; 2057 return FALSE; 2058 } 2059 2060 /** 2061 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C 2062 * @hw: pointer to hardware structure 2063 * @byte_offset: byte offset to read 2064 * @dev_addr: address to read from 2065 * @data: value read 2066 * @lock: TRUE if to take and release semaphore 2067 * 2068 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2069 * a specified device address. 2070 **/ 2071 static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 2072 u8 dev_addr, u8 *data, bool lock) 2073 { 2074 s32 status; 2075 u32 max_retry = 10; 2076 u32 retry = 0; 2077 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2078 bool nack = 1; 2079 *data = 0; 2080 2081 DEBUGFUNC("ixgbe_read_i2c_byte_generic"); 2082 2083 if (hw->mac.type >= ixgbe_mac_X550) 2084 max_retry = 3; 2085 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr)) 2086 max_retry = IXGBE_SFP_DETECT_RETRIES; 2087 2088 do { 2089 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 2090 return IXGBE_ERR_SWFW_SYNC; 2091 2092 ixgbe_i2c_start(hw); 2093 2094 /* Device Address and write indication */ 2095 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2096 if (status != IXGBE_SUCCESS) 2097 goto fail; 2098 2099 status = ixgbe_get_i2c_ack(hw); 2100 if (status != IXGBE_SUCCESS) 2101 goto fail; 2102 2103 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2104 if (status != IXGBE_SUCCESS) 2105 goto fail; 2106 2107 status = ixgbe_get_i2c_ack(hw); 2108 if (status != IXGBE_SUCCESS) 2109 goto fail; 2110 2111 ixgbe_i2c_start(hw); 2112 2113 /* Device Address and read indication */ 2114 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 2115 if (status != IXGBE_SUCCESS) 2116 goto fail; 2117 2118 status = ixgbe_get_i2c_ack(hw); 2119 if (status != IXGBE_SUCCESS) 2120 goto fail; 2121 2122 ixgbe_clock_in_i2c_byte(hw, data); 2123 2124 status = ixgbe_clock_out_i2c_bit(hw, nack); 2125 if (status != IXGBE_SUCCESS) 2126 goto fail; 2127 2128 ixgbe_i2c_stop(hw); 2129 if (lock) 2130 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2131 return IXGBE_SUCCESS; 2132 2133 fail: 2134 ixgbe_i2c_bus_clear(hw); 2135 if (lock) { 2136 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2137 msec_delay(100); 2138 } 2139 if (retry < max_retry) 2140 DEBUGOUT("I2C byte read error - Retrying.\n"); 2141 else 2142 DEBUGOUT("I2C byte read error.\n"); 2143 retry++; 2144 2145 } while (retry <= max_retry); 2146 2147 return status; 2148 } 2149 2150 /** 2151 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 2152 * @hw: pointer to hardware structure 2153 * @byte_offset: byte offset to read 2154 * @dev_addr: address to read from 2155 * @data: value read 2156 * 2157 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2158 * a specified device address. 2159 **/ 2160 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2161 u8 dev_addr, u8 *data) 2162 { 2163 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2164 data, TRUE); 2165 } 2166 2167 /** 2168 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C 2169 * @hw: pointer to hardware structure 2170 * @byte_offset: byte offset to read 2171 * @dev_addr: address to read from 2172 * @data: value read 2173 * 2174 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2175 * a specified device address. 2176 **/ 2177 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 2178 u8 dev_addr, u8 *data) 2179 { 2180 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2181 data, FALSE); 2182 } 2183 2184 /** 2185 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C 2186 * @hw: pointer to hardware structure 2187 * @byte_offset: byte offset to write 2188 * @dev_addr: address to write to 2189 * @data: value to write 2190 * @lock: TRUE if to take and release semaphore 2191 * 2192 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2193 * a specified device address. 2194 **/ 2195 static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 2196 u8 dev_addr, u8 data, bool lock) 2197 { 2198 s32 status; 2199 u32 max_retry = 2; 2200 u32 retry = 0; 2201 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2202 2203 DEBUGFUNC("ixgbe_write_i2c_byte_generic"); 2204 2205 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 2206 IXGBE_SUCCESS) 2207 return IXGBE_ERR_SWFW_SYNC; 2208 2209 do { 2210 ixgbe_i2c_start(hw); 2211 2212 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2213 if (status != IXGBE_SUCCESS) 2214 goto fail; 2215 2216 status = ixgbe_get_i2c_ack(hw); 2217 if (status != IXGBE_SUCCESS) 2218 goto fail; 2219 2220 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2221 if (status != IXGBE_SUCCESS) 2222 goto fail; 2223 2224 status = ixgbe_get_i2c_ack(hw); 2225 if (status != IXGBE_SUCCESS) 2226 goto fail; 2227 2228 status = ixgbe_clock_out_i2c_byte(hw, data); 2229 if (status != IXGBE_SUCCESS) 2230 goto fail; 2231 2232 status = ixgbe_get_i2c_ack(hw); 2233 if (status != IXGBE_SUCCESS) 2234 goto fail; 2235 2236 ixgbe_i2c_stop(hw); 2237 if (lock) 2238 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2239 return IXGBE_SUCCESS; 2240 2241 fail: 2242 ixgbe_i2c_bus_clear(hw); 2243 if (retry < max_retry) 2244 DEBUGOUT("I2C byte write error - Retrying.\n"); 2245 else 2246 DEBUGOUT("I2C byte write error.\n"); 2247 retry++; 2248 } while (retry <= max_retry); 2249 2250 if (lock) 2251 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2252 2253 return status; 2254 } 2255 2256 /** 2257 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 2258 * @hw: pointer to hardware structure 2259 * @byte_offset: byte offset to write 2260 * @dev_addr: address to write to 2261 * @data: value to write 2262 * 2263 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2264 * a specified device address. 2265 **/ 2266 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2267 u8 dev_addr, u8 data) 2268 { 2269 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2270 data, TRUE); 2271 } 2272 2273 /** 2274 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C 2275 * @hw: pointer to hardware structure 2276 * @byte_offset: byte offset to write 2277 * @dev_addr: address to write to 2278 * @data: value to write 2279 * 2280 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2281 * a specified device address. 2282 **/ 2283 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 2284 u8 dev_addr, u8 data) 2285 { 2286 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2287 data, FALSE); 2288 } 2289 2290 /** 2291 * ixgbe_i2c_start - Sets I2C start condition 2292 * @hw: pointer to hardware structure 2293 * 2294 * Sets I2C start condition (High -> Low on SDA while SCL is High) 2295 * Set bit-bang mode on X550 hardware. 2296 **/ 2297 static void ixgbe_i2c_start(struct ixgbe_hw *hw) 2298 { 2299 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2300 2301 DEBUGFUNC("ixgbe_i2c_start"); 2302 2303 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw); 2304 2305 /* Start condition must begin with data and clock high */ 2306 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2307 ixgbe_raise_i2c_clk(hw, &i2cctl); 2308 2309 /* Setup time for start condition (4.7us) */ 2310 usec_delay(IXGBE_I2C_T_SU_STA); 2311 2312 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2313 2314 /* Hold time for start condition (4us) */ 2315 usec_delay(IXGBE_I2C_T_HD_STA); 2316 2317 ixgbe_lower_i2c_clk(hw, &i2cctl); 2318 2319 /* Minimum low period of clock is 4.7 us */ 2320 usec_delay(IXGBE_I2C_T_LOW); 2321 2322 } 2323 2324 /** 2325 * ixgbe_i2c_stop - Sets I2C stop condition 2326 * @hw: pointer to hardware structure 2327 * 2328 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 2329 * Disables bit-bang mode and negates data output enable on X550 2330 * hardware. 2331 **/ 2332 static void ixgbe_i2c_stop(struct ixgbe_hw *hw) 2333 { 2334 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2335 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2336 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2337 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw); 2338 2339 DEBUGFUNC("ixgbe_i2c_stop"); 2340 2341 /* Stop condition must begin with data low and clock high */ 2342 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2343 ixgbe_raise_i2c_clk(hw, &i2cctl); 2344 2345 /* Setup time for stop condition (4us) */ 2346 usec_delay(IXGBE_I2C_T_SU_STO); 2347 2348 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2349 2350 /* bus free time between stop and start (4.7us)*/ 2351 usec_delay(IXGBE_I2C_T_BUF); 2352 2353 if (bb_en_bit || data_oe_bit || clk_oe_bit) { 2354 i2cctl &= ~bb_en_bit; 2355 i2cctl |= data_oe_bit | clk_oe_bit; 2356 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2357 IXGBE_WRITE_FLUSH(hw); 2358 } 2359 } 2360 2361 /** 2362 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 2363 * @hw: pointer to hardware structure 2364 * @data: data byte to clock in 2365 * 2366 * Clocks in one byte data via I2C data/clock 2367 **/ 2368 static void ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) 2369 { 2370 s32 i; 2371 bool bit = 0; 2372 2373 DEBUGFUNC("ixgbe_clock_in_i2c_byte"); 2374 2375 *data = 0; 2376 for (i = 7; i >= 0; i--) { 2377 ixgbe_clock_in_i2c_bit(hw, &bit); 2378 *data |= bit << i; 2379 } 2380 } 2381 2382 /** 2383 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 2384 * @hw: pointer to hardware structure 2385 * @data: data byte clocked out 2386 * 2387 * Clocks out one byte data via I2C data/clock 2388 **/ 2389 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) 2390 { 2391 s32 status = IXGBE_SUCCESS; 2392 s32 i; 2393 u32 i2cctl; 2394 bool bit; 2395 2396 DEBUGFUNC("ixgbe_clock_out_i2c_byte"); 2397 2398 for (i = 7; i >= 0; i--) { 2399 bit = (data >> i) & 0x1; 2400 status = ixgbe_clock_out_i2c_bit(hw, bit); 2401 2402 if (status != IXGBE_SUCCESS) 2403 break; 2404 } 2405 2406 /* Release SDA line (set high) */ 2407 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2408 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2409 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2410 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2411 IXGBE_WRITE_FLUSH(hw); 2412 2413 return status; 2414 } 2415 2416 /** 2417 * ixgbe_get_i2c_ack - Polls for I2C ACK 2418 * @hw: pointer to hardware structure 2419 * 2420 * Clocks in/out one bit via I2C data/clock 2421 **/ 2422 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 2423 { 2424 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2425 s32 status = IXGBE_SUCCESS; 2426 u32 i = 0; 2427 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2428 u32 timeout = 10; 2429 bool ack = 1; 2430 2431 DEBUGFUNC("ixgbe_get_i2c_ack"); 2432 2433 if (data_oe_bit) { 2434 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2435 i2cctl |= data_oe_bit; 2436 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2437 IXGBE_WRITE_FLUSH(hw); 2438 } 2439 ixgbe_raise_i2c_clk(hw, &i2cctl); 2440 2441 /* Minimum high period of clock is 4us */ 2442 usec_delay(IXGBE_I2C_T_HIGH); 2443 2444 /* Poll for ACK. Note that ACK in I2C spec is 2445 * transition from 1 to 0 */ 2446 for (i = 0; i < timeout; i++) { 2447 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2448 ack = ixgbe_get_i2c_data(hw, &i2cctl); 2449 2450 usec_delay(1); 2451 if (!ack) 2452 break; 2453 } 2454 2455 if (ack) { 2456 DEBUGOUT("I2C ack was not received.\n"); 2457 status = IXGBE_ERR_I2C; 2458 } 2459 2460 ixgbe_lower_i2c_clk(hw, &i2cctl); 2461 2462 /* Minimum low period of clock is 4.7 us */ 2463 usec_delay(IXGBE_I2C_T_LOW); 2464 2465 return status; 2466 } 2467 2468 /** 2469 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 2470 * @hw: pointer to hardware structure 2471 * @data: read data value 2472 * 2473 * Clocks in one bit via I2C data/clock 2474 **/ 2475 static void ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) 2476 { 2477 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2478 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2479 2480 DEBUGFUNC("ixgbe_clock_in_i2c_bit"); 2481 2482 if (data_oe_bit) { 2483 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2484 i2cctl |= data_oe_bit; 2485 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2486 IXGBE_WRITE_FLUSH(hw); 2487 } 2488 ixgbe_raise_i2c_clk(hw, &i2cctl); 2489 2490 /* Minimum high period of clock is 4us */ 2491 usec_delay(IXGBE_I2C_T_HIGH); 2492 2493 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2494 *data = ixgbe_get_i2c_data(hw, &i2cctl); 2495 2496 ixgbe_lower_i2c_clk(hw, &i2cctl); 2497 2498 /* Minimum low period of clock is 4.7 us */ 2499 usec_delay(IXGBE_I2C_T_LOW); 2500 } 2501 2502 /** 2503 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 2504 * @hw: pointer to hardware structure 2505 * @data: data value to write 2506 * 2507 * Clocks out one bit via I2C data/clock 2508 **/ 2509 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) 2510 { 2511 s32 status; 2512 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2513 2514 DEBUGFUNC("ixgbe_clock_out_i2c_bit"); 2515 2516 status = ixgbe_set_i2c_data(hw, &i2cctl, data); 2517 if (status == IXGBE_SUCCESS) { 2518 ixgbe_raise_i2c_clk(hw, &i2cctl); 2519 2520 /* Minimum high period of clock is 4us */ 2521 usec_delay(IXGBE_I2C_T_HIGH); 2522 2523 ixgbe_lower_i2c_clk(hw, &i2cctl); 2524 2525 /* Minimum low period of clock is 4.7 us. 2526 * This also takes care of the data hold time. 2527 */ 2528 usec_delay(IXGBE_I2C_T_LOW); 2529 } else { 2530 status = IXGBE_ERR_I2C; 2531 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2532 "I2C data was not set to %X\n", data); 2533 } 2534 2535 return status; 2536 } 2537 2538 /** 2539 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 2540 * @hw: pointer to hardware structure 2541 * @i2cctl: Current value of I2CCTL register 2542 * 2543 * Raises the I2C clock line '0'->'1' 2544 * Negates the I2C clock output enable on X550 hardware. 2545 **/ 2546 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2547 { 2548 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2549 u32 i = 0; 2550 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT; 2551 u32 i2cctl_r = 0; 2552 2553 DEBUGFUNC("ixgbe_raise_i2c_clk"); 2554 2555 if (clk_oe_bit) { 2556 *i2cctl |= clk_oe_bit; 2557 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2558 } 2559 2560 for (i = 0; i < timeout; i++) { 2561 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw); 2562 2563 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2564 IXGBE_WRITE_FLUSH(hw); 2565 /* SCL rise time (1000ns) */ 2566 usec_delay(IXGBE_I2C_T_RISE); 2567 2568 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2569 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw)) 2570 break; 2571 } 2572 } 2573 2574 /** 2575 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 2576 * @hw: pointer to hardware structure 2577 * @i2cctl: Current value of I2CCTL register 2578 * 2579 * Lowers the I2C clock line '1'->'0' 2580 * Asserts the I2C clock output enable on X550 hardware. 2581 **/ 2582 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2583 { 2584 DEBUGFUNC("ixgbe_lower_i2c_clk"); 2585 2586 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw)); 2587 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2588 2589 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2590 IXGBE_WRITE_FLUSH(hw); 2591 2592 /* SCL fall time (300ns) */ 2593 usec_delay(IXGBE_I2C_T_FALL); 2594 } 2595 2596 /** 2597 * ixgbe_set_i2c_data - Sets the I2C data bit 2598 * @hw: pointer to hardware structure 2599 * @i2cctl: Current value of I2CCTL register 2600 * @data: I2C data value (0 or 1) to set 2601 * 2602 * Sets the I2C data bit 2603 * Asserts the I2C data output enable on X550 hardware. 2604 **/ 2605 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) 2606 { 2607 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2608 s32 status = IXGBE_SUCCESS; 2609 2610 DEBUGFUNC("ixgbe_set_i2c_data"); 2611 2612 if (data) 2613 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2614 else 2615 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw)); 2616 *i2cctl &= ~data_oe_bit; 2617 2618 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2619 IXGBE_WRITE_FLUSH(hw); 2620 2621 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 2622 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 2623 2624 if (!data) /* Can't verify data in this case */ 2625 return IXGBE_SUCCESS; 2626 if (data_oe_bit) { 2627 *i2cctl |= data_oe_bit; 2628 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2629 IXGBE_WRITE_FLUSH(hw); 2630 } 2631 2632 /* Verify data was set correctly */ 2633 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2634 if (data != ixgbe_get_i2c_data(hw, i2cctl)) { 2635 status = IXGBE_ERR_I2C; 2636 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2637 "Error - I2C data was not set to %X.\n", 2638 data); 2639 } 2640 2641 return status; 2642 } 2643 2644 /** 2645 * ixgbe_get_i2c_data - Reads the I2C SDA data bit 2646 * @hw: pointer to hardware structure 2647 * @i2cctl: Current value of I2CCTL register 2648 * 2649 * Returns the I2C data bit value 2650 * Negates the I2C data output enable on X550 hardware. 2651 **/ 2652 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl) 2653 { 2654 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2655 bool data; 2656 2657 DEBUGFUNC("ixgbe_get_i2c_data"); 2658 2659 if (data_oe_bit) { 2660 *i2cctl |= data_oe_bit; 2661 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2662 IXGBE_WRITE_FLUSH(hw); 2663 usec_delay(IXGBE_I2C_T_FALL); 2664 } 2665 2666 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw)) 2667 data = 1; 2668 else 2669 data = 0; 2670 2671 return data; 2672 } 2673 2674 /** 2675 * ixgbe_i2c_bus_clear - Clears the I2C bus 2676 * @hw: pointer to hardware structure 2677 * 2678 * Clears the I2C bus by sending nine clock pulses. 2679 * Used when data line is stuck low. 2680 **/ 2681 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 2682 { 2683 u32 i2cctl; 2684 u32 i; 2685 2686 DEBUGFUNC("ixgbe_i2c_bus_clear"); 2687 2688 ixgbe_i2c_start(hw); 2689 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2690 2691 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2692 2693 for (i = 0; i < 9; i++) { 2694 ixgbe_raise_i2c_clk(hw, &i2cctl); 2695 2696 /* Min high period of clock is 4us */ 2697 usec_delay(IXGBE_I2C_T_HIGH); 2698 2699 ixgbe_lower_i2c_clk(hw, &i2cctl); 2700 2701 /* Min low period of clock is 4.7us*/ 2702 usec_delay(IXGBE_I2C_T_LOW); 2703 } 2704 2705 ixgbe_i2c_start(hw); 2706 2707 /* Put the i2c bus back to default state */ 2708 ixgbe_i2c_stop(hw); 2709 } 2710 2711 /** 2712 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred. 2713 * @hw: pointer to hardware structure 2714 * 2715 * Checks if the LASI temp alarm status was triggered due to overtemp 2716 **/ 2717 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) 2718 { 2719 s32 status = IXGBE_SUCCESS; 2720 u16 phy_data = 0; 2721 2722 DEBUGFUNC("ixgbe_tn_check_overtemp"); 2723 2724 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) 2725 goto out; 2726 2727 /* Check that the LASI temp alarm status was triggered */ 2728 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, 2729 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data); 2730 2731 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM)) 2732 goto out; 2733 2734 status = IXGBE_ERR_OVERTEMP; 2735 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature"); 2736 out: 2737 return status; 2738 } 2739 2740 /** 2741 * ixgbe_set_copper_phy_power - Control power for copper phy 2742 * @hw: pointer to hardware structure 2743 * @on: TRUE for on, FALSE for off 2744 */ 2745 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on) 2746 { 2747 u32 status; 2748 u16 reg; 2749 2750 if (!on && ixgbe_mng_present(hw)) 2751 return 0; 2752 2753 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2754 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2755 ®); 2756 if (status) 2757 return status; 2758 2759 if (on) { 2760 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2761 } else { 2762 if (ixgbe_check_reset_blocked(hw)) 2763 return 0; 2764 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2765 } 2766 2767 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2768 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2769 reg); 2770 return status; 2771 } 2772
Indexes created Tue Sep 23 21:09:50 GMT 2025