1 /* $NetBSD: if_bnxvar.h,v 1.15 2022/09/24 18:12:42 thorpej Exp $ */ 2 /*- 3 * Copyright (c) 2010 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Jean-Yves Migeon <jym (at) NetBSD.org> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 * 30 * $FreeBSD: src/sys/dev/bce/if_bcereg.h,v 1.4 2006/05/04 00:34:07 mjacob Exp $ 31 */ 32 33 #ifndef _DEV_PCI_IF_BNXVAR_H_ 34 #define _DEV_PCI_IF_BNXVAR_H_ 35 36 #ifdef _KERNEL_OPT 37 #include "opt_inet.h" 38 #endif 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/sockio.h> 43 #include <sys/mbuf.h> 44 #include <sys/kernel.h> 45 #include <sys/device.h> 46 #include <sys/socket.h> 47 #include <sys/sysctl.h> 48 #include <sys/workqueue.h> 49 50 #include <net/if.h> 51 #include <net/if_dl.h> 52 #include <net/if_media.h> 53 #include <net/if_ether.h> 54 55 #ifdef INET 56 #include <netinet/in.h> 57 #include <netinet/in_systm.h> 58 #include <netinet/in_var.h> 59 #include <netinet/ip.h> 60 #include <netinet/if_inarp.h> 61 #endif 62 63 #include <net/if_vlanvar.h> 64 65 #include <net/bpf.h> 66 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcidevs.h> 70 71 #include <dev/mii/mii.h> 72 #include <dev/mii/miivar.h> 73 #include <dev/mii/miidevs.h> 74 #include <dev/mii/brgphyreg.h> 75 76 /* 77 * PCI registers defined in the PCI 2.2 spec. 78 */ 79 #define BNX_PCI_BAR0 0x10 80 #define BNX_PCI_PCIX_CMD 0x40 81 82 /****************************************************************************/ 83 /* Convenience definitions. */ 84 /****************************************************************************/ 85 #define REG_WR(sc, reg, val) bus_space_write_4(sc->bnx_btag, sc->bnx_bhandle, reg, val) 86 #define REG_WR16(sc, reg, val) bus_space_write_2(sc->bnx_btag, sc->bnx_bhandle, reg, val) 87 #define REG_RD(sc, reg) bus_space_read_4(sc->bnx_btag, sc->bnx_bhandle, reg) 88 #define REG_RD_IND(sc, offset) bnx_reg_rd_ind(sc, offset) 89 #define REG_WR_IND(sc, offset, val) bnx_reg_wr_ind(sc, offset, val) 90 #define CTX_WR(sc, cid_addr, offset, val) bnx_ctx_wr(sc, cid_addr, offset, val) 91 #define BNX_SETBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) | (x))) 92 #define BNX_CLRBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) & ~(x))) 93 #define PCI_SETBIT(pc, tag, reg, x) pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) | (x))) 94 #define PCI_CLRBIT(pc, tag, reg, x) pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) & ~(x))) 95 96 /****************************************************************************/ 97 /* BNX Device State Data Structure */ 98 /****************************************************************************/ 99 100 #define BNX_STATUS_BLK_SZ sizeof(struct status_block) 101 #define BNX_STATS_BLK_SZ sizeof(struct statistics_block) 102 #define BNX_TX_CHAIN_PAGE_SZ BCM_PAGE_SIZE 103 #define BNX_RX_CHAIN_PAGE_SZ BCM_PAGE_SIZE 104 105 struct bnx_pkt { 106 TAILQ_ENTRY(bnx_pkt) pkt_entry; 107 bus_dmamap_t pkt_dmamap; 108 struct mbuf *pkt_mbuf; 109 uint16_t pkt_end_desc; 110 }; 111 112 TAILQ_HEAD(bnx_pkt_list, bnx_pkt); 113 114 struct bnx_softc 115 { 116 device_t bnx_dev; 117 struct ethercom bnx_ec; 118 struct pci_attach_args bnx_pa; 119 120 struct ifmedia bnx_ifmedia; /* TBI media info */ 121 122 bus_space_tag_t bnx_btag; /* Device bus tag */ 123 bus_space_handle_t bnx_bhandle; /* Device bus handle */ 124 bus_size_t bnx_size; 125 126 pci_intr_handle_t *bnx_ih; 127 void *bnx_intrhand; /* Interrupt handler */ 128 129 /* packet allocation workqueue */ 130 struct workqueue *bnx_wq; 131 struct work bnx_wk; 132 133 /* ASIC Chip ID. */ 134 uint32_t bnx_chipid; 135 136 /* General controller flags. */ 137 uint32_t bnx_flags; 138 139 /* Controller capability flags. */ 140 uint32_t bnx_cap_flags; 141 #define BNX_MSI_CAPABLE_FLAG 0x00000001 142 #define BNX_MSIX_CAPABLE_FLAG 0x00000002 143 #define BNX_PCIE_CAPABLE_FLAG 0x00000004 144 #define BNX_PCIX_CAPABLE_FLAG 0x00000008 145 146 /* PHY specific flags. */ 147 uint32_t bnx_phy_flags; 148 149 /* Values that need to be shared with the PHY driver. */ 150 uint32_t bnx_shared_hw_cfg; 151 uint32_t bnx_port_hw_cfg; 152 153 int bnx_flowflags; 154 155 uint16_t bus_speed_mhz; /* PCI bus speed */ 156 uint16_t link_width; /* PCIe link width */ 157 uint16_t link_speed; /* PCIe link speed */ 158 struct flash_spec *bnx_flash_info; /* Flash NVRAM settings */ 159 uint32_t bnx_flash_size; /* Flash NVRAM size */ 160 uint32_t bnx_shmem_base;/* Shared Memory base address */ 161 char * bnx_name; /* Name string */ 162 163 /* Tracks the version of bootcode firmware. */ 164 char bnx_bc_ver[32]; 165 166 /* Tracks the version of management firmware. */ 167 char bnx_mfw_ver[32]; 168 169 /* Tracks the state of the firmware. 0 = Running while any */ 170 /* other value indicates that the firmware is not responding. */ 171 uint16_t bnx_fw_timed_out; 172 173 /* An incrementing sequence used to coordinate messages passed */ 174 /* from the driver to the firmware. */ 175 uint16_t bnx_fw_wr_seq; 176 177 /* An incrementing sequence used to let the firmware know that */ 178 /* the driver is still operating. Without the pulse, management */ 179 /* firmware such as IPMI or UMP will operate in OS absent state. */ 180 uint16_t bnx_fw_drv_pulse_wr_seq; 181 182 /* Ethernet MAC address. */ 183 u_char eaddr[6]; 184 185 /* These setting are used by the host coalescing (HC) block to */ 186 /* to control how often the status block, statistics block and */ 187 /* interrupts are generated. */ 188 uint16_t bnx_tx_quick_cons_trip_int; 189 uint16_t bnx_tx_quick_cons_trip; 190 uint16_t bnx_rx_quick_cons_trip_int; 191 uint16_t bnx_rx_quick_cons_trip; 192 uint16_t bnx_comp_prod_trip_int; 193 uint16_t bnx_comp_prod_trip; 194 uint16_t bnx_tx_ticks_int; 195 uint16_t bnx_tx_ticks; 196 uint16_t bnx_rx_ticks_int; 197 uint16_t bnx_rx_ticks; 198 uint16_t bnx_com_ticks_int; 199 uint16_t bnx_com_ticks; 200 uint16_t bnx_cmd_ticks_int; 201 uint16_t bnx_cmd_ticks; 202 uint32_t bnx_stats_ticks; 203 204 /* The address of the integrated PHY on the MII bus. */ 205 int bnx_phy_addr; 206 207 /* The device handle for the MII bus child device. */ 208 struct mii_data bnx_mii; 209 210 /* Driver maintained TX chain pointers and byte counter. */ 211 uint16_t rx_prod; 212 uint16_t rx_cons; 213 uint32_t rx_prod_bseq; /* Counts the bytes used. */ 214 uint16_t tx_prod; 215 uint16_t tx_cons; 216 uint32_t tx_prod_bseq; /* Counts the bytes used. */ 217 218 int bnx_link; 219 struct callout bnx_timeout; 220 int bnx_detaching; 221 222 /* Frame size and mbuf allocation size for RX frames. */ 223 uint32_t max_frame_size; 224 int mbuf_alloc_size; 225 226 /* Receive mode settings (i.e promiscuous, multicast, etc.). */ 227 uint32_t rx_mode; 228 229 /* Bus tag for the bnx controller. */ 230 bus_dma_tag_t bnx_dmatag; 231 232 /* H/W maintained TX buffer descriptor chain structure. */ 233 bus_dma_segment_t tx_bd_chain_seg[TX_PAGES]; 234 int tx_bd_chain_rseg[TX_PAGES]; 235 bus_dmamap_t tx_bd_chain_map[TX_PAGES]; 236 struct tx_bd *tx_bd_chain[TX_PAGES]; 237 bus_addr_t tx_bd_chain_paddr[TX_PAGES]; 238 239 /* H/W maintained RX buffer descriptor chain structure. */ 240 bus_dma_segment_t rx_bd_chain_seg[RX_PAGES]; 241 int rx_bd_chain_rseg[RX_PAGES]; 242 bus_dmamap_t rx_bd_chain_map[RX_PAGES]; 243 struct rx_bd *rx_bd_chain[RX_PAGES]; 244 bus_addr_t rx_bd_chain_paddr[RX_PAGES]; 245 246 /* H/W maintained status block. */ 247 bus_dma_segment_t status_seg; 248 int status_rseg; 249 bus_dmamap_t status_map; 250 struct status_block *status_block; /* virtual address */ 251 bus_addr_t status_block_paddr; /* Physical address */ 252 253 /* H/W maintained context block */ 254 int ctx_pages; 255 bus_dma_segment_t ctx_segs[4]; 256 int ctx_rsegs[4]; 257 bus_dmamap_t ctx_map[4]; 258 void *ctx_block[4]; 259 260 /* Driver maintained status block values. */ 261 uint16_t last_status_idx; 262 uint16_t hw_rx_cons; 263 uint16_t hw_tx_cons; 264 265 /* H/W maintained statistics block. */ 266 bus_dma_segment_t stats_seg; 267 int stats_rseg; 268 bus_dmamap_t stats_map; 269 struct statistics_block *stats_block; /* Virtual address */ 270 bus_addr_t stats_block_paddr; /* Physical address */ 271 272 /* Bus tag for RX/TX mbufs. */ 273 bus_dma_segment_t rx_mbuf_seg; 274 int rx_mbuf_rseg; 275 bus_dma_segment_t tx_mbuf_seg; 276 int tx_mbuf_rseg; 277 278 /* S/W maintained mbuf TX chain structure. */ 279 kmutex_t tx_pkt_mtx; 280 uint tx_pkt_count; 281 struct bnx_pkt_list tx_free_pkts; 282 struct bnx_pkt_list tx_used_pkts; 283 284 /* S/W maintained mbuf RX chain structure. */ 285 bus_dmamap_t rx_mbuf_map[TOTAL_RX_BD]; 286 struct mbuf *rx_mbuf_ptr[TOTAL_RX_BD]; 287 288 /* Track the number of rx_bd and tx_bd's in use. */ 289 uint16_t free_rx_bd; 290 uint16_t max_rx_bd; 291 uint16_t used_tx_bd; 292 uint16_t max_tx_bd; 293 294 /* For interfacing with if_stats */ 295 uint64_t if_stat_collisions; 296 uint64_t if_stat_ierrors; 297 uint64_t if_stat_oerrors; 298 299 /* Provides access to hardware statistics through sysctl. */ 300 uint64_t stat_IfHCInOctets; 301 uint64_t stat_IfHCInBadOctets; 302 uint64_t stat_IfHCOutOctets; 303 uint64_t stat_IfHCOutBadOctets; 304 uint64_t stat_IfHCInUcastPkts; 305 uint64_t stat_IfHCInMulticastPkts; 306 uint64_t stat_IfHCInBroadcastPkts; 307 uint64_t stat_IfHCOutUcastPkts; 308 uint64_t stat_IfHCOutMulticastPkts; 309 uint64_t stat_IfHCOutBroadcastPkts; 310 311 uint32_t stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 312 uint32_t stat_Dot3StatsCarrierSenseErrors; 313 uint32_t stat_Dot3StatsFCSErrors; 314 uint32_t stat_Dot3StatsAlignmentErrors; 315 uint32_t stat_Dot3StatsSingleCollisionFrames; 316 uint32_t stat_Dot3StatsMultipleCollisionFrames; 317 uint32_t stat_Dot3StatsDeferredTransmissions; 318 uint32_t stat_Dot3StatsExcessiveCollisions; 319 uint32_t stat_Dot3StatsLateCollisions; 320 uint32_t stat_EtherStatsCollisions; 321 uint32_t stat_EtherStatsFragments; 322 uint32_t stat_EtherStatsJabbers; 323 uint32_t stat_EtherStatsUndersizePkts; 324 uint32_t stat_EtherStatsOverrsizePkts; 325 uint32_t stat_EtherStatsPktsRx64Octets; 326 uint32_t stat_EtherStatsPktsRx65Octetsto127Octets; 327 uint32_t stat_EtherStatsPktsRx128Octetsto255Octets; 328 uint32_t stat_EtherStatsPktsRx256Octetsto511Octets; 329 uint32_t stat_EtherStatsPktsRx512Octetsto1023Octets; 330 uint32_t stat_EtherStatsPktsRx1024Octetsto1522Octets; 331 uint32_t stat_EtherStatsPktsRx1523Octetsto9022Octets; 332 uint32_t stat_EtherStatsPktsTx64Octets; 333 uint32_t stat_EtherStatsPktsTx65Octetsto127Octets; 334 uint32_t stat_EtherStatsPktsTx128Octetsto255Octets; 335 uint32_t stat_EtherStatsPktsTx256Octetsto511Octets; 336 uint32_t stat_EtherStatsPktsTx512Octetsto1023Octets; 337 uint32_t stat_EtherStatsPktsTx1024Octetsto1522Octets; 338 uint32_t stat_EtherStatsPktsTx1523Octetsto9022Octets; 339 uint32_t stat_XonPauseFramesReceived; 340 uint32_t stat_XoffPauseFramesReceived; 341 uint32_t stat_OutXonSent; 342 uint32_t stat_OutXoffSent; 343 uint32_t stat_FlowControlDone; 344 uint32_t stat_MacControlFramesReceived; 345 uint32_t stat_XoffStateEntered; 346 uint32_t stat_IfInFramesL2FilterDiscards; 347 uint32_t stat_IfInRuleCheckerDiscards; 348 uint32_t stat_IfInFTQDiscards; 349 uint32_t stat_IfInMBUFDiscards; 350 uint32_t stat_IfInRuleCheckerP4Hit; 351 uint32_t stat_CatchupInRuleCheckerDiscards; 352 uint32_t stat_CatchupInFTQDiscards; 353 uint32_t stat_CatchupInMBUFDiscards; 354 uint32_t stat_CatchupInRuleCheckerP4Hit; 355 356 /* Mbuf allocation failure counter. */ 357 uint32_t mbuf_alloc_failed; 358 359 /* TX DMA mapping failure counter. */ 360 uint32_t tx_dma_map_failures; 361 362 #ifdef BNX_DEBUG 363 /* Track the number of enqueued mbufs. */ 364 int tx_mbuf_alloc; 365 int rx_mbuf_alloc; 366 367 /* Track the distribution buffer segments. */ 368 uint32_t rx_mbuf_segs[BNX_MAX_SEGMENTS+1]; 369 370 /* Track how many and what type of interrupts are generated. */ 371 uint32_t interrupts_generated; 372 uint32_t interrupts_handled; 373 uint32_t rx_interrupts; 374 uint32_t tx_interrupts; 375 376 uint32_t rx_low_watermark; /* Lowest number of rx_bd's free. */ 377 uint32_t rx_empty_count; /* Number of times the RX chain was empty. */ 378 uint32_t tx_hi_watermark; /* Greatest number of tx_bd's used. */ 379 uint32_t tx_full_count; /* Number of times the TX chain was full. */ 380 uint32_t mbuf_sim_alloc_failed;/* Mbuf simulated allocation failure counter. */ 381 uint32_t l2fhdr_status_errors; 382 uint32_t unexpected_attentions; 383 uint32_t lost_status_block_updates; 384 #endif 385 }; 386 387 struct bnx_firmware_header { 388 int bnx_COM_FwReleaseMajor; 389 int bnx_COM_FwReleaseMinor; 390 int bnx_COM_FwReleaseFix; 391 uint32_t bnx_COM_FwStartAddr; 392 uint32_t bnx_COM_FwTextAddr; 393 int bnx_COM_FwTextLen; 394 uint32_t bnx_COM_FwDataAddr; 395 int bnx_COM_FwDataLen; 396 uint32_t bnx_COM_FwRodataAddr; 397 int bnx_COM_FwRodataLen; 398 uint32_t bnx_COM_FwBssAddr; 399 int bnx_COM_FwBssLen; 400 uint32_t bnx_COM_FwSbssAddr; 401 int bnx_COM_FwSbssLen; 402 403 int bnx_RXP_FwReleaseMajor; 404 int bnx_RXP_FwReleaseMinor; 405 int bnx_RXP_FwReleaseFix; 406 uint32_t bnx_RXP_FwStartAddr; 407 uint32_t bnx_RXP_FwTextAddr; 408 int bnx_RXP_FwTextLen; 409 uint32_t bnx_RXP_FwDataAddr; 410 int bnx_RXP_FwDataLen; 411 uint32_t bnx_RXP_FwRodataAddr; 412 int bnx_RXP_FwRodataLen; 413 uint32_t bnx_RXP_FwBssAddr; 414 int bnx_RXP_FwBssLen; 415 uint32_t bnx_RXP_FwSbssAddr; 416 int bnx_RXP_FwSbssLen; 417 418 int bnx_TPAT_FwReleaseMajor; 419 int bnx_TPAT_FwReleaseMinor; 420 int bnx_TPAT_FwReleaseFix; 421 uint32_t bnx_TPAT_FwStartAddr; 422 uint32_t bnx_TPAT_FwTextAddr; 423 int bnx_TPAT_FwTextLen; 424 uint32_t bnx_TPAT_FwDataAddr; 425 int bnx_TPAT_FwDataLen; 426 uint32_t bnx_TPAT_FwRodataAddr; 427 int bnx_TPAT_FwRodataLen; 428 uint32_t bnx_TPAT_FwBssAddr; 429 int bnx_TPAT_FwBssLen; 430 uint32_t bnx_TPAT_FwSbssAddr; 431 int bnx_TPAT_FwSbssLen; 432 433 int bnx_TXP_FwReleaseMajor; 434 int bnx_TXP_FwReleaseMinor; 435 int bnx_TXP_FwReleaseFix; 436 uint32_t bnx_TXP_FwStartAddr; 437 uint32_t bnx_TXP_FwTextAddr; 438 int bnx_TXP_FwTextLen; 439 uint32_t bnx_TXP_FwDataAddr; 440 int bnx_TXP_FwDataLen; 441 uint32_t bnx_TXP_FwRodataAddr; 442 int bnx_TXP_FwRodataLen; 443 uint32_t bnx_TXP_FwBssAddr; 444 int bnx_TXP_FwBssLen; 445 uint32_t bnx_TXP_FwSbssAddr; 446 int bnx_TXP_FwSbssLen; 447 448 /* Followed by blocks of data, each sized according to 449 * the (rather obvious) block length stated above. 450 * 451 * bnx_COM_FwText, bnx_COM_FwData, bnx_COM_FwRodata, 452 * bnx_COM_FwBss, bnx_COM_FwSbss, 453 * 454 * bnx_RXP_FwText, bnx_RXP_FwData, bnx_RXP_FwRodata, 455 * bnx_RXP_FwBss, bnx_RXP_FwSbss, 456 * 457 * bnx_TPAT_FwText, bnx_TPAT_FwData, bnx_TPAT_FwRodata, 458 * bnx_TPAT_FwBss, bnx_TPAT_FwSbss, 459 * 460 * bnx_TXP_FwText, bnx_TXP_FwData, bnx_TXP_FwRodata, 461 * bnx_TXP_FwBss, bnx_TXP_FwSbss, 462 */ 463 }; 464 465 #endif /* _DEV_PCI_IF_BNXVAR_H_ */ 466
Indexes created Mon Oct 20 00:09:40 GMT 2025